i915/display/intel_vrr.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2020 Intel Corporation
0004  *
0005  */
0006
0007 #include "i915_drv.h"
0008 #include "intel_de.h"
0009 #include "intel_display_types.h"
0010 #include "intel_vrr.h"
0011
0012 bool intel_vrr_is_capable(struct intel_connector *connector)
0013 {
0014     const struct drm_display_info *info = &connector->base.display_info;
0015     struct drm_i915_private *i915 = to_i915(connector->base.dev);
0016     struct intel_dp *intel_dp;
0017
0018     /*
0019      * DP Sink is capable of VRR video timings if
0020      * Ignore MSA bit is set in DPCD.
0021      * EDID monitor range also should be atleast 10 for reasonable
0022      * Adaptive Sync or Variable Refresh Rate end user experience.
0023      */
0024     switch (connector->base.connector_type) {
0025     case DRM_MODE_CONNECTOR_eDP:
0026         if (!connector->panel.vbt.vrr)
0027             return false;
0028         fallthrough;
0029     case DRM_MODE_CONNECTOR_DisplayPort:
0030         intel_dp = intel_attached_dp(connector);
0031
0032         if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
0033             return false;
0034
0035         break;
0036     default:
0037         return false;
0038     }
0039
0040     return HAS_VRR(i915) &&
0041         info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
0042 }
0043
0044 void
0045 intel_vrr_check_modeset(struct intel_atomic_state *state)
0046 {
0047     int i;
0048     struct intel_crtc_state *old_crtc_state, *new_crtc_state;
0049     struct intel_crtc *crtc;
0050
0051     for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
0052                         new_crtc_state, i) {
0053         if (new_crtc_state->uapi.vrr_enabled !=
0054             old_crtc_state->uapi.vrr_enabled)
0055             new_crtc_state->uapi.mode_changed = true;
0056     }
0057 }
0058
0059 /*
0060  * Without VRR registers get latched at:
0061  *  vblank_start
0062  *
0063  * With VRR the earliest registers can get latched is:
0064  *  intel_vrr_vmin_vblank_start(), which if we want to maintain
0065  *  the correct min vtotal is >=vblank_start+1
0066  *
0067  * The latest point registers can get latched is the vmax decision boundary:
0068  *  intel_vrr_vmax_vblank_start()
0069  *
0070  * Between those two points the vblank exit starts (and hence registers get
0071  * latched) ASAP after a push is sent.
0072  *
0073  * framestart_delay is programmable 1-4.
0074  */
0075 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
0076 {
0077     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0078     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0079
0080     /* The hw imposes the extra scanline before frame start */
0081     if (DISPLAY_VER(i915) >= 13)
0082         return crtc_state->vrr.guardband + crtc_state->framestart_delay + 1;
0083     else
0084         return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
0085 }
0086
0087 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
0088 {
0089     /* Min vblank actually determined by flipline that is always >=vmin+1 */
0090     return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
0091 }
0092
0093 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
0094 {
0095     return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
0096 }
0097
0098 void
0099 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
0100              struct drm_connector_state *conn_state)
0101 {
0102     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0103     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0104     struct intel_connector *connector =
0105         to_intel_connector(conn_state->connector);
0106     struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
0107     const struct drm_display_info *info = &connector->base.display_info;
0108     int vmin, vmax;
0109
0110     if (!intel_vrr_is_capable(connector))
0111         return;
0112
0113     if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
0114         return;
0115
0116     if (!crtc_state->uapi.vrr_enabled)
0117         return;
0118
0119     vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
0120                 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
0121     vmax = adjusted_mode->crtc_clock * 1000 /
0122         (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
0123
0124     vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
0125     vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
0126
0127     if (vmin >= vmax)
0128         return;
0129
0130     /*
0131      * flipline determines the min vblank length the hardware will
0132      * generate, and flipline>=vmin+1, hence we reduce vmin by one
0133      * to make sure we can get the actual min vblank length.
0134      */
0135     crtc_state->vrr.vmin = vmin - 1;
0136     crtc_state->vrr.vmax = vmax;
0137     crtc_state->vrr.enable = true;
0138
0139     crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
0140
0141     /*
0142      * For XE_LPD+, we use guardband and pipeline override
0143      * is deprecated.
0144      */
0145     if (DISPLAY_VER(i915) >= 13)
0146         crtc_state->vrr.guardband =
0147             crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
0148             i915->window2_delay;
0149     else
0150         /*
0151          * FIXME: s/4/framestart_delay/ to get consistent
0152          * earliest/latest points for register latching regardless
0153          * of the framestart_delay used?
0154          *
0155          * FIXME: this really needs the extra scanline to provide consistent
0156          * behaviour for all framestart_delay values. Otherwise with
0157          * framestart_delay==4 we will end up extending the min vblank by
0158          * one extra line.
0159          */
0160         crtc_state->vrr.pipeline_full =
0161             min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
0162
0163     crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
0164 }
0165
0166 void intel_vrr_enable(struct intel_encoder *encoder,
0167               const struct intel_crtc_state *crtc_state)
0168 {
0169     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0170     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0171     u32 trans_vrr_ctl;
0172
0173     if (!crtc_state->vrr.enable)
0174         return;
0175
0176     if (DISPLAY_VER(dev_priv) >= 13)
0177         trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
0178             VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
0179             XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
0180     else
0181         trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
0182             VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
0183             VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
0184             VRR_CTL_PIPELINE_FULL_OVERRIDE;
0185
0186     intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
0187     intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
0188     intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl);
0189     intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
0190     intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
0191 }
0192
0193 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
0194 {
0195     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0196     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0197     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0198
0199     if (!crtc_state->vrr.enable)
0200         return;
0201
0202     intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
0203                TRANS_PUSH_EN | TRANS_PUSH_SEND);
0204 }
0205
0206 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
0207 {
0208     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0209     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0210     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0211
0212     if (!crtc_state->vrr.enable)
0213         return false;
0214
0215     return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND;
0216 }
0217
0218 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
0219 {
0220     struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
0221     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0222     enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
0223
0224     if (!old_crtc_state->vrr.enable)
0225         return;
0226
0227     intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
0228     intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
0229 }
0230
0231 void intel_vrr_get_config(struct intel_crtc *crtc,
0232               struct intel_crtc_state *crtc_state)
0233 {
0234     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0235     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0236     u32 trans_vrr_ctl;
0237
0238     trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
0239     crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
0240     if (!crtc_state->vrr.enable)
0241         return;
0242
0243     if (DISPLAY_VER(dev_priv) >= 13)
0244         crtc_state->vrr.guardband =
0245             REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
0246     else
0247         if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
0248             crtc_state->vrr.pipeline_full =
0249                 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
0250     if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
0251         crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
0252     crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
0253     crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
0254
0255     crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
0256 }