i915/display/intel_vga.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #include <linux/pci.h>
0007 #include <linux/vgaarb.h>
0008
0009 #include <drm/i915_drm.h>
0010 #include <video/vga.h>
0011
0012 #include "i915_drv.h"
0013 #include "intel_de.h"
0014 #include "intel_vga.h"
0015
0016 static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
0017 {
0018     if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
0019         return VLV_VGACNTRL;
0020     else if (DISPLAY_VER(i915) >= 5)
0021         return CPU_VGACNTRL;
0022     else
0023         return VGACNTRL;
0024 }
0025
0026 /* Disable the VGA plane that we never use */
0027 void intel_vga_disable(struct drm_i915_private *dev_priv)
0028 {
0029     struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
0030     i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
0031     u8 sr1;
0032
0033     if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)
0034         return;
0035
0036     /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
0037     vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
0038     outb(0x01, VGA_SEQ_I);
0039     sr1 = inb(VGA_SEQ_D);
0040     outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D);
0041     vga_put(pdev, VGA_RSRC_LEGACY_IO);
0042     udelay(300);
0043
0044     intel_de_write(dev_priv, vga_reg, VGA_DISP_DISABLE);
0045     intel_de_posting_read(dev_priv, vga_reg);
0046 }
0047
0048 void intel_vga_redisable_power_on(struct drm_i915_private *dev_priv)
0049 {
0050     i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
0051
0052     if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) {
0053         drm_dbg_kms(&dev_priv->drm,
0054                 "Something enabled VGA plane, disabling it\n");
0055         intel_vga_disable(dev_priv);
0056     }
0057 }
0058
0059 void intel_vga_redisable(struct drm_i915_private *i915)
0060 {
0061     intel_wakeref_t wakeref;
0062
0063     /*
0064      * This function can be called both from intel_modeset_setup_hw_state or
0065      * at a very early point in our resume sequence, where the power well
0066      * structures are not yet restored. Since this function is at a very
0067      * paranoid "someone might have enabled VGA while we were not looking"
0068      * level, just check if the power well is enabled instead of trying to
0069      * follow the "don't touch the power well if we don't need it" policy
0070      * the rest of the driver uses.
0071      */
0072     wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_VGA);
0073     if (!wakeref)
0074         return;
0075
0076     intel_vga_redisable_power_on(i915);
0077
0078     intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref);
0079 }
0080
0081 void intel_vga_reset_io_mem(struct drm_i915_private *i915)
0082 {
0083     struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
0084
0085     /*
0086      * After we re-enable the power well, if we touch VGA register 0x3d5
0087      * we'll get unclaimed register interrupts. This stops after we write
0088      * anything to the VGA MSR register. The vgacon module uses this
0089      * register all the time, so if we unbind our driver and, as a
0090      * consequence, bind vgacon, we'll get stuck in an infinite loop at
0091      * console_unlock(). So make here we touch the VGA MSR register, making
0092      * sure vgacon can keep working normally without triggering interrupts
0093      * and error messages.
0094      */
0095     vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
0096     outb(inb(VGA_MIS_R), VGA_MIS_W);
0097     vga_put(pdev, VGA_RSRC_LEGACY_IO);
0098 }
0099
0100 static int
0101 intel_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
0102 {
0103     unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
0104     u16 gmch_ctrl;
0105
0106     if (pci_read_config_word(i915->bridge_dev, reg, &gmch_ctrl)) {
0107         drm_err(&i915->drm, "failed to read control word\n");
0108         return -EIO;
0109     }
0110
0111     if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
0112         return 0;
0113
0114     if (enable_decode)
0115         gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
0116     else
0117         gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
0118
0119     if (pci_write_config_word(i915->bridge_dev, reg, gmch_ctrl)) {
0120         drm_err(&i915->drm, "failed to write control word\n");
0121         return -EIO;
0122     }
0123
0124     return 0;
0125 }
0126
0127 static unsigned int
0128 intel_vga_set_decode(struct pci_dev *pdev, bool enable_decode)
0129 {
0130     struct drm_i915_private *i915 = pdev_to_i915(pdev);
0131
0132     intel_vga_set_state(i915, enable_decode);
0133
0134     if (enable_decode)
0135         return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
0136                VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
0137     else
0138         return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
0139 }
0140
0141 int intel_vga_register(struct drm_i915_private *i915)
0142 {
0143
0144     struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
0145     int ret;
0146
0147     /*
0148      * If we have > 1 VGA cards, then we need to arbitrate access to the
0149      * common VGA resources.
0150      *
0151      * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
0152      * then we do not take part in VGA arbitration and the
0153      * vga_client_register() fails with -ENODEV.
0154      */
0155     ret = vga_client_register(pdev, intel_vga_set_decode);
0156     if (ret && ret != -ENODEV)
0157         return ret;
0158
0159     return 0;
0160 }
0161
0162 void intel_vga_unregister(struct drm_i915_private *i915)
0163 {
0164     struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
0165
0166     vga_client_unregister(pdev);
0167 }