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0001 /*
0002  * Copyright © 2006-2016 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0020  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0021  * SOFTWARE.
0022  *
0023  * Authors:
0024  *    Eric Anholt <eric@anholt.net>
0025  *
0026  */
0027 
0028 /*
0029  * This information is private to VBT parsing in intel_bios.c.
0030  *
0031  * Please do NOT include anywhere else.
0032  */
0033 #ifndef _INTEL_BIOS_PRIVATE
0034 #error "intel_vbt_defs.h is private to intel_bios.c"
0035 #endif
0036 
0037 #ifndef _INTEL_VBT_DEFS_H_
0038 #define _INTEL_VBT_DEFS_H_
0039 
0040 #include "intel_bios.h"
0041 
0042 /**
0043  * struct vbt_header - VBT Header structure
0044  * @signature:      VBT signature, always starts with "$VBT"
0045  * @version:        Version of this structure
0046  * @header_size:    Size of this structure
0047  * @vbt_size:       Size of VBT (VBT Header, BDB Header and data blocks)
0048  * @vbt_checksum:   Checksum
0049  * @reserved0:      Reserved
0050  * @bdb_offset:     Offset of &struct bdb_header from beginning of VBT
0051  * @aim_offset:     Offsets of add-in data blocks from beginning of VBT
0052  */
0053 struct vbt_header {
0054     u8 signature[20];
0055     u16 version;
0056     u16 header_size;
0057     u16 vbt_size;
0058     u8 vbt_checksum;
0059     u8 reserved0;
0060     u32 bdb_offset;
0061     u32 aim_offset[4];
0062 } __packed;
0063 
0064 /**
0065  * struct bdb_header - BDB Header structure
0066  * @signature:      BDB signature "BIOS_DATA_BLOCK"
0067  * @version:        Version of the data block definitions
0068  * @header_size:    Size of this structure
0069  * @bdb_size:       Size of BDB (BDB Header and data blocks)
0070  */
0071 struct bdb_header {
0072     u8 signature[16];
0073     u16 version;
0074     u16 header_size;
0075     u16 bdb_size;
0076 } __packed;
0077 
0078 /*
0079  * There are several types of BIOS data blocks (BDBs), each block has
0080  * an ID and size in the first 3 bytes (ID in first, size in next 2).
0081  * Known types are listed below.
0082  */
0083 enum bdb_block_id {
0084     BDB_GENERAL_FEATURES        = 1,
0085     BDB_GENERAL_DEFINITIONS     = 2,
0086     BDB_OLD_TOGGLE_LIST     = 3,
0087     BDB_MODE_SUPPORT_LIST       = 4,
0088     BDB_GENERIC_MODE_TABLE      = 5,
0089     BDB_EXT_MMIO_REGS       = 6,
0090     BDB_SWF_IO          = 7,
0091     BDB_SWF_MMIO            = 8,
0092     BDB_PSR             = 9,
0093     BDB_MODE_REMOVAL_TABLE      = 10,
0094     BDB_CHILD_DEVICE_TABLE      = 11,
0095     BDB_DRIVER_FEATURES     = 12,
0096     BDB_DRIVER_PERSISTENCE      = 13,
0097     BDB_EXT_TABLE_PTRS      = 14,
0098     BDB_DOT_CLOCK_OVERRIDE      = 15,
0099     BDB_DISPLAY_SELECT      = 16,
0100     BDB_DRIVER_ROTATION     = 18,
0101     BDB_DISPLAY_REMOVE      = 19,
0102     BDB_OEM_CUSTOM          = 20,
0103     BDB_EFP_LIST            = 21, /* workarounds for VGA hsync/vsync */
0104     BDB_SDVO_LVDS_OPTIONS       = 22,
0105     BDB_SDVO_PANEL_DTDS     = 23,
0106     BDB_SDVO_LVDS_PNP_IDS       = 24,
0107     BDB_SDVO_LVDS_POWER_SEQ     = 25,
0108     BDB_TV_OPTIONS          = 26,
0109     BDB_EDP             = 27,
0110     BDB_LVDS_OPTIONS        = 40,
0111     BDB_LVDS_LFP_DATA_PTRS      = 41,
0112     BDB_LVDS_LFP_DATA       = 42,
0113     BDB_LVDS_BACKLIGHT      = 43,
0114     BDB_LFP_POWER           = 44,
0115     BDB_MIPI_CONFIG         = 52,
0116     BDB_MIPI_SEQUENCE       = 53,
0117     BDB_COMPRESSION_PARAMETERS  = 56,
0118     BDB_GENERIC_DTD         = 58,
0119     BDB_SKIP            = 254, /* VBIOS private block, ignore */
0120 };
0121 
0122 /*
0123  * Block 1 - General Bit Definitions
0124  */
0125 
0126 struct bdb_general_features {
0127         /* bits 1 */
0128     u8 panel_fitting:2;
0129     u8 flexaim:1;
0130     u8 msg_enable:1;
0131     u8 clear_screen:3;
0132     u8 color_flip:1;
0133 
0134         /* bits 2 */
0135     u8 download_ext_vbt:1;
0136     u8 enable_ssc:1;
0137     u8 ssc_freq:1;
0138     u8 enable_lfp_on_override:1;
0139     u8 disable_ssc_ddt:1;
0140     u8 underscan_vga_timings:1;
0141     u8 display_clock_mode:1;
0142     u8 vbios_hotplug_support:1;
0143 
0144         /* bits 3 */
0145     u8 disable_smooth_vision:1;
0146     u8 single_dvi:1;
0147     u8 rotate_180:1;                    /* 181 */
0148     u8 fdi_rx_polarity_inverted:1;
0149     u8 vbios_extended_mode:1;               /* 160 */
0150     u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1;            /* 160 */
0151     u8 panel_best_fit_timing:1;             /* 160 */
0152     u8 ignore_strap_state:1;                /* 160 */
0153 
0154         /* bits 4 */
0155     u8 legacy_monitor_detect;
0156 
0157         /* bits 5 */
0158     u8 int_crt_support:1;
0159     u8 int_tv_support:1;
0160     u8 int_efp_support:1;
0161     u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */
0162     u8 dp_ssc_freq:1;   /* SSC freq for PCH attached eDP */
0163     u8 dp_ssc_dongle_supported:1;
0164     u8 rsvd11:2; /* finish byte */
0165 
0166     /* bits 6 */
0167     u8 tc_hpd_retry_timeout:7; /* 242 */
0168     u8 rsvd12:1;
0169 
0170     /* bits 7 */
0171     u8 afc_startup_config:2;/* 249 */
0172     u8 rsvd13:6;
0173 } __packed;
0174 
0175 /*
0176  * Block 2 - General Bytes Definition
0177  */
0178 
0179 /* pre-915 */
0180 #define GPIO_PIN_DVI_LVDS   0x03 /* "DVI/LVDS DDC GPIO pins" */
0181 #define GPIO_PIN_ADD_I2C    0x05 /* "ADDCARD I2C GPIO pins" */
0182 #define GPIO_PIN_ADD_DDC    0x04 /* "ADDCARD DDC GPIO pins" */
0183 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
0184 
0185 /* Device handle */
0186 #define DEVICE_HANDLE_LFP1  0x0008
0187 #define DEVICE_HANDLE_LFP2  0x0080
0188 
0189 /* Pre 915 */
0190 #define DEVICE_TYPE_NONE    0x00
0191 #define DEVICE_TYPE_CRT     0x01
0192 #define DEVICE_TYPE_TV      0x09
0193 #define DEVICE_TYPE_EFP     0x12
0194 #define DEVICE_TYPE_LFP     0x22
0195 /* On 915+ */
0196 #define DEVICE_TYPE_CRT_DPMS        0x6001
0197 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
0198 #define DEVICE_TYPE_TV_COMPOSITE    0x0209
0199 #define DEVICE_TYPE_TV_MACROVISION  0x0289
0200 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
0201 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
0202 #define DEVICE_TYPE_TV_SCART        0x0209
0203 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
0204 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
0205 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
0206 #define DEVICE_TYPE_EFP_DVI_I       0x6053
0207 #define DEVICE_TYPE_EFP_DVI_D_DUAL  0x6152
0208 #define DEVICE_TYPE_EFP_DVI_D_HDCP  0x60d2
0209 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
0210 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
0211 #define DEVICE_TYPE_LFP_PANELLINK   0x5012
0212 #define DEVICE_TYPE_LFP_CMOS_PWR    0x5042
0213 #define DEVICE_TYPE_LFP_LVDS_PWR    0x5062
0214 #define DEVICE_TYPE_LFP_LVDS_DUAL   0x5162
0215 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
0216 
0217 /* Add the device class for LFP, TV, HDMI */
0218 #define DEVICE_TYPE_INT_LFP     0x1022
0219 #define DEVICE_TYPE_INT_TV      0x1009
0220 #define DEVICE_TYPE_HDMI        0x60D2
0221 #define DEVICE_TYPE_DP          0x68C6
0222 #define DEVICE_TYPE_DP_DUAL_MODE    0x60D6
0223 #define DEVICE_TYPE_eDP         0x78C6
0224 
0225 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
0226 #define DEVICE_TYPE_POWER_MANAGEMENT    (1 << 14)
0227 #define DEVICE_TYPE_HOTPLUG_SIGNALING   (1 << 13)
0228 #define DEVICE_TYPE_INTERNAL_CONNECTOR  (1 << 12)
0229 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
0230 #define DEVICE_TYPE_MIPI_OUTPUT     (1 << 10)
0231 #define DEVICE_TYPE_COMPOSITE_OUTPUT    (1 << 9)
0232 #define DEVICE_TYPE_DUAL_CHANNEL    (1 << 8)
0233 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
0234 #define DEVICE_TYPE_LVDS_SIGNALING  (1 << 5)
0235 #define DEVICE_TYPE_TMDS_DVI_SIGNALING  (1 << 4)
0236 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
0237 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT  (1 << 2)
0238 #define DEVICE_TYPE_DIGITAL_OUTPUT  (1 << 1)
0239 #define DEVICE_TYPE_ANALOG_OUTPUT   (1 << 0)
0240 
0241 #define DEVICE_CFG_NONE     0x00
0242 #define DEVICE_CFG_12BIT_DVOB   0x01
0243 #define DEVICE_CFG_12BIT_DVOC   0x02
0244 #define DEVICE_CFG_24BIT_DVOBC  0x09
0245 #define DEVICE_CFG_24BIT_DVOCB  0x0a
0246 #define DEVICE_CFG_DUAL_DVOB    0x11
0247 #define DEVICE_CFG_DUAL_DVOC    0x12
0248 #define DEVICE_CFG_DUAL_DVOBC   0x13
0249 #define DEVICE_CFG_DUAL_LINK_DVOBC  0x19
0250 #define DEVICE_CFG_DUAL_LINK_DVOCB  0x1a
0251 
0252 #define DEVICE_WIRE_NONE    0x00
0253 #define DEVICE_WIRE_DVOB    0x01
0254 #define DEVICE_WIRE_DVOC    0x02
0255 #define DEVICE_WIRE_DVOBC   0x03
0256 #define DEVICE_WIRE_DVOBB   0x05
0257 #define DEVICE_WIRE_DVOCC   0x06
0258 #define DEVICE_WIRE_DVOB_MASTER 0x0d
0259 #define DEVICE_WIRE_DVOC_MASTER 0x0e
0260 
0261 /* dvo_port pre BDB 155 */
0262 #define DEVICE_PORT_DVOA    0x00 /* none on 845+ */
0263 #define DEVICE_PORT_DVOB    0x01
0264 #define DEVICE_PORT_DVOC    0x02
0265 
0266 /* dvo_port BDB 155+ */
0267 #define DVO_PORT_HDMIA      0
0268 #define DVO_PORT_HDMIB      1
0269 #define DVO_PORT_HDMIC      2
0270 #define DVO_PORT_HDMID      3
0271 #define DVO_PORT_LVDS       4
0272 #define DVO_PORT_TV     5
0273 #define DVO_PORT_CRT        6
0274 #define DVO_PORT_DPB        7
0275 #define DVO_PORT_DPC        8
0276 #define DVO_PORT_DPD        9
0277 #define DVO_PORT_DPA        10
0278 #define DVO_PORT_DPE        11              /* 193 */
0279 #define DVO_PORT_HDMIE      12              /* 193 */
0280 #define DVO_PORT_DPF        13              /* N/A */
0281 #define DVO_PORT_HDMIF      14              /* N/A */
0282 #define DVO_PORT_DPG        15              /* 217 */
0283 #define DVO_PORT_HDMIG      16              /* 217 */
0284 #define DVO_PORT_DPH        17              /* 217 */
0285 #define DVO_PORT_HDMIH      18              /* 217 */
0286 #define DVO_PORT_DPI        19              /* 217 */
0287 #define DVO_PORT_HDMII      20              /* 217 */
0288 #define DVO_PORT_MIPIA      21              /* 171 */
0289 #define DVO_PORT_MIPIB      22              /* 171 */
0290 #define DVO_PORT_MIPIC      23              /* 171 */
0291 #define DVO_PORT_MIPID      24              /* 171 */
0292 
0293 #define HDMI_MAX_DATA_RATE_PLATFORM 0           /* 204 */
0294 #define HDMI_MAX_DATA_RATE_297      1           /* 204 */
0295 #define HDMI_MAX_DATA_RATE_165      2           /* 204 */
0296 #define HDMI_MAX_DATA_RATE_594      3           /* 249 */
0297 #define HDMI_MAX_DATA_RATE_340      4           /* 249 */
0298 #define HDMI_MAX_DATA_RATE_300      5           /* 249 */
0299 
0300 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE     33
0301 
0302 /* DDC Bus DDI Type 155+ */
0303 enum vbt_gmbus_ddi {
0304     DDC_BUS_DDI_B = 0x1,
0305     DDC_BUS_DDI_C,
0306     DDC_BUS_DDI_D,
0307     DDC_BUS_DDI_F,
0308     ICL_DDC_BUS_DDI_A = 0x1,
0309     ICL_DDC_BUS_DDI_B,
0310     TGL_DDC_BUS_DDI_C,
0311     RKL_DDC_BUS_DDI_D = 0x3,
0312     RKL_DDC_BUS_DDI_E,
0313     ICL_DDC_BUS_PORT_1 = 0x4,
0314     ICL_DDC_BUS_PORT_2,
0315     ICL_DDC_BUS_PORT_3,
0316     ICL_DDC_BUS_PORT_4,
0317     TGL_DDC_BUS_PORT_5,
0318     TGL_DDC_BUS_PORT_6,
0319     ADLS_DDC_BUS_PORT_TC1 = 0x2,
0320     ADLS_DDC_BUS_PORT_TC2,
0321     ADLS_DDC_BUS_PORT_TC3,
0322     ADLS_DDC_BUS_PORT_TC4,
0323     ADLP_DDC_BUS_PORT_TC1 = 0x3,
0324     ADLP_DDC_BUS_PORT_TC2,
0325     ADLP_DDC_BUS_PORT_TC3,
0326     ADLP_DDC_BUS_PORT_TC4
0327 
0328 };
0329 
0330 #define DP_AUX_A 0x40
0331 #define DP_AUX_B 0x10
0332 #define DP_AUX_C 0x20
0333 #define DP_AUX_D 0x30
0334 #define DP_AUX_E 0x50
0335 #define DP_AUX_F 0x60
0336 #define DP_AUX_G 0x70
0337 #define DP_AUX_H 0x80
0338 #define DP_AUX_I 0x90
0339 
0340 /* DP max link rate 216+ */
0341 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR3   0
0342 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR2   1
0343 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR    2
0344 #define BDB_216_VBT_DP_MAX_LINK_RATE_LBR    3
0345 
0346 /* DP max link rate 230+ */
0347 #define BDB_230_VBT_DP_MAX_LINK_RATE_DEF    0
0348 #define BDB_230_VBT_DP_MAX_LINK_RATE_LBR    1
0349 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR    2
0350 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR2   3
0351 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR3   4
0352 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10 5
0353 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5   6
0354 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20 7
0355 
0356 /*
0357  * The child device config, aka the display device data structure, provides a
0358  * description of a port and its configuration on the platform.
0359  *
0360  * The child device config size has been increased, and fields have been added
0361  * and their meaning has changed over time. Care must be taken when accessing
0362  * basically any of the fields to ensure the correct interpretation for the BDB
0363  * version in question.
0364  *
0365  * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
0366  * space for the full structure below, and initialize the tail not actually
0367  * present in VBT to zeros. Accessing those fields is fine, as long as the
0368  * default zero is taken into account, again according to the BDB version.
0369  *
0370  * BDB versions 155 and below are considered legacy, and version 155 seems to be
0371  * a baseline for some of the VBT documentation. When adding new fields, please
0372  * include the BDB version when the field was added, if it's above that.
0373  */
0374 struct child_device_config {
0375     u16 handle;
0376     u16 device_type; /* See DEVICE_TYPE_* above */
0377 
0378     union {
0379         u8  device_id[10]; /* ascii string */
0380         struct {
0381             u8 i2c_speed;
0382             u8 dp_onboard_redriver;         /* 158 */
0383             u8 dp_ondock_redriver;          /* 158 */
0384             u8 hdmi_level_shifter_value:5;      /* 169 */
0385             u8 hdmi_max_data_rate:3;        /* 204 */
0386             u16 dtd_buf_ptr;            /* 161 */
0387             u8 edidless_efp:1;          /* 161 */
0388             u8 compression_enable:1;        /* 198 */
0389             u8 compression_method_cps:1;        /* 198 */
0390             u8 ganged_edp:1;            /* 202 */
0391             u8 reserved0:4;
0392             u8 compression_structure_index:4;   /* 198 */
0393             u8 reserved1:4;
0394             u8 slave_port;              /* 202 */
0395             u8 reserved2;
0396         } __packed;
0397     } __packed;
0398 
0399     u16 addin_offset;
0400     u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
0401     u8 i2c_pin;
0402     u8 slave_addr;
0403     u8 ddc_pin;
0404     u16 edid_ptr;
0405     u8 dvo_cfg; /* See DEVICE_CFG_* above */
0406 
0407     union {
0408         struct {
0409             u8 dvo2_port;
0410             u8 i2c2_pin;
0411             u8 slave2_addr;
0412             u8 ddc2_pin;
0413         } __packed;
0414         struct {
0415             u8 efp_routed:1;            /* 158 */
0416             u8 lane_reversal:1;         /* 184 */
0417             u8 lspcon:1;                /* 192 */
0418             u8 iboost:1;                /* 196 */
0419             u8 hpd_invert:1;            /* 196 */
0420             u8 use_vbt_vswing:1;            /* 218 */
0421             u8 flag_reserved:2;
0422             u8 hdmi_support:1;          /* 158 */
0423             u8 dp_support:1;            /* 158 */
0424             u8 tmds_support:1;          /* 158 */
0425             u8 support_reserved:5;
0426             u8 aux_channel;
0427             u8 dongle_detect;
0428         } __packed;
0429     } __packed;
0430 
0431     u8 pipe_cap:2;
0432     u8 sdvo_stall:1;                    /* 158 */
0433     u8 hpd_status:2;
0434     u8 integrated_encoder:1;
0435     u8 capabilities_reserved:2;
0436     u8 dvo_wiring; /* See DEVICE_WIRE_* above */
0437 
0438     union {
0439         u8 dvo2_wiring;
0440         u8 mipi_bridge_type;                /* 171 */
0441     } __packed;
0442 
0443     u16 extended_type;
0444     u8 dvo_function;
0445     u8 dp_usb_type_c:1;                 /* 195 */
0446     u8 tbt:1;                       /* 209 */
0447     u8 flags2_reserved:2;                   /* 195 */
0448     u8 dp_port_trace_length:4;              /* 209 */
0449     u8 dp_gpio_index;                   /* 195 */
0450     u16 dp_gpio_pin_num;                    /* 195 */
0451     u8 dp_iboost_level:4;                   /* 196 */
0452     u8 hdmi_iboost_level:4;                 /* 196 */
0453     u8 dp_max_link_rate:3;                  /* 216/230 GLK+ */
0454     u8 dp_max_link_rate_reserved:5;             /* 216/230 */
0455 } __packed;
0456 
0457 struct bdb_general_definitions {
0458     /* DDC GPIO */
0459     u8 crt_ddc_gmbus_pin;
0460 
0461     /* DPMS bits */
0462     u8 dpms_acpi:1;
0463     u8 skip_boot_crt_detect:1;
0464     u8 dpms_aim:1;
0465     u8 rsvd1:5; /* finish byte */
0466 
0467     /* boot device bits */
0468     u8 boot_display[2];
0469     u8 child_dev_size;
0470 
0471     /*
0472      * Device info:
0473      * If TV is present, it'll be at devices[0].
0474      * LVDS will be next, either devices[0] or [1], if present.
0475      * On some platforms the number of device is 6. But could be as few as
0476      * 4 if both TV and LVDS are missing.
0477      * And the device num is related with the size of general definition
0478      * block. It is obtained by using the following formula:
0479      * number = (block_size - sizeof(bdb_general_definitions))/
0480      *       defs->child_dev_size;
0481      */
0482     u8 devices[];
0483 } __packed;
0484 
0485 /*
0486  * Block 9 - SRD Feature Block
0487  */
0488 
0489 struct psr_table {
0490     /* Feature bits */
0491     u8 full_link:1;
0492     u8 require_aux_to_wakeup:1;
0493     u8 feature_bits_rsvd:6;
0494 
0495     /* Wait times */
0496     u8 idle_frames:4;
0497     u8 lines_to_wait:3;
0498     u8 wait_times_rsvd:1;
0499 
0500     /* TP wake up time in multiple of 100 */
0501     u16 tp1_wakeup_time;
0502     u16 tp2_tp3_wakeup_time;
0503 } __packed;
0504 
0505 struct bdb_psr {
0506     struct psr_table psr_table[16];
0507 
0508     /* PSR2 TP2/TP3 wakeup time for 16 panels */
0509     u32 psr2_tp2_tp3_wakeup_time;
0510 } __packed;
0511 
0512 /*
0513  * Block 12 - Driver Features Data Block
0514  */
0515 
0516 #define BDB_DRIVER_FEATURE_NO_LVDS      0
0517 #define BDB_DRIVER_FEATURE_INT_LVDS     1
0518 #define BDB_DRIVER_FEATURE_SDVO_LVDS        2
0519 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS    3
0520 
0521 struct bdb_driver_features {
0522     u8 boot_dev_algorithm:1;
0523     u8 block_display_switch:1;
0524     u8 allow_display_switch:1;
0525     u8 hotplug_dvo:1;
0526     u8 dual_view_zoom:1;
0527     u8 int15h_hook:1;
0528     u8 sprite_in_clone:1;
0529     u8 primary_lfp_id:1;
0530 
0531     u16 boot_mode_x;
0532     u16 boot_mode_y;
0533     u8 boot_mode_bpp;
0534     u8 boot_mode_refresh;
0535 
0536     u16 enable_lfp_primary:1;
0537     u16 selective_mode_pruning:1;
0538     u16 dual_frequency:1;
0539     u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
0540     u16 nt_clone_support:1;
0541     u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
0542     u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
0543     u16 cui_aspect_scaling:1;
0544     u16 preserve_aspect_ratio:1;
0545     u16 sdvo_device_power_down:1;
0546     u16 crt_hotplug:1;
0547     u16 lvds_config:2;
0548     u16 tv_hotplug:1;
0549     u16 hdmi_config:2;
0550 
0551     u8 static_display:1;
0552     u8 reserved2:7;
0553     u16 legacy_crt_max_x;
0554     u16 legacy_crt_max_y;
0555     u8 legacy_crt_max_refresh;
0556 
0557     u8 hdmi_termination;
0558     u8 custom_vbt_version;
0559     /* Driver features data block */
0560     u16 rmpm_enabled:1;
0561     u16 s2ddt_enabled:1;
0562     u16 dpst_enabled:1;
0563     u16 bltclt_enabled:1;
0564     u16 adb_enabled:1;
0565     u16 drrs_enabled:1;
0566     u16 grs_enabled:1;
0567     u16 gpmt_enabled:1;
0568     u16 tbt_enabled:1;
0569     u16 psr_enabled:1;
0570     u16 ips_enabled:1;
0571     u16 reserved3:1;
0572     u16 dmrrs_enabled:1;
0573     u16 reserved4:2;
0574     u16 pc_feature_valid:1;
0575 } __packed;
0576 
0577 /*
0578  * Block 22 - SDVO LVDS General Options
0579  */
0580 
0581 struct bdb_sdvo_lvds_options {
0582     u8 panel_backlight;
0583     u8 h40_set_panel_type;
0584     u8 panel_type;
0585     u8 ssc_clk_freq;
0586     u16 als_low_trip;
0587     u16 als_high_trip;
0588     u8 sclalarcoeff_tab_row_num;
0589     u8 sclalarcoeff_tab_row_size;
0590     u8 coefficient[8];
0591     u8 panel_misc_bits_1;
0592     u8 panel_misc_bits_2;
0593     u8 panel_misc_bits_3;
0594     u8 panel_misc_bits_4;
0595 } __packed;
0596 
0597 /*
0598  * Block 23 - SDVO LVDS Panel DTDs
0599  */
0600 
0601 struct lvds_dvo_timing {
0602     u16 clock;      /**< In 10khz */
0603     u8 hactive_lo;
0604     u8 hblank_lo;
0605     u8 hblank_hi:4;
0606     u8 hactive_hi:4;
0607     u8 vactive_lo;
0608     u8 vblank_lo;
0609     u8 vblank_hi:4;
0610     u8 vactive_hi:4;
0611     u8 hsync_off_lo;
0612     u8 hsync_pulse_width_lo;
0613     u8 vsync_pulse_width_lo:4;
0614     u8 vsync_off_lo:4;
0615     u8 vsync_pulse_width_hi:2;
0616     u8 vsync_off_hi:2;
0617     u8 hsync_pulse_width_hi:2;
0618     u8 hsync_off_hi:2;
0619     u8 himage_lo;
0620     u8 vimage_lo;
0621     u8 vimage_hi:4;
0622     u8 himage_hi:4;
0623     u8 h_border;
0624     u8 v_border;
0625     u8 rsvd1:3;
0626     u8 digital:2;
0627     u8 vsync_positive:1;
0628     u8 hsync_positive:1;
0629     u8 non_interlaced:1;
0630 } __packed;
0631 
0632 struct bdb_sdvo_panel_dtds {
0633     struct lvds_dvo_timing dtds[4];
0634 } __packed;
0635 
0636 /*
0637  * Block 27 - eDP VBT Block
0638  */
0639 
0640 #define EDP_18BPP   0
0641 #define EDP_24BPP   1
0642 #define EDP_30BPP   2
0643 #define EDP_RATE_1_62   0
0644 #define EDP_RATE_2_7    1
0645 #define EDP_RATE_5_4    2
0646 #define EDP_LANE_1  0
0647 #define EDP_LANE_2  1
0648 #define EDP_LANE_4  3
0649 #define EDP_PREEMPHASIS_NONE    0
0650 #define EDP_PREEMPHASIS_3_5dB   1
0651 #define EDP_PREEMPHASIS_6dB 2
0652 #define EDP_PREEMPHASIS_9_5dB   3
0653 #define EDP_VSWING_0_4V     0
0654 #define EDP_VSWING_0_6V     1
0655 #define EDP_VSWING_0_8V     2
0656 #define EDP_VSWING_1_2V     3
0657 
0658 
0659 struct edp_fast_link_params {
0660     u8 rate:4;
0661     u8 lanes:4;
0662     u8 preemphasis:4;
0663     u8 vswing:4;
0664 } __packed;
0665 
0666 struct edp_pwm_delays {
0667     u16 pwm_on_to_backlight_enable;
0668     u16 backlight_disable_to_pwm_off;
0669 } __packed;
0670 
0671 struct edp_full_link_params {
0672     u8 preemphasis:4;
0673     u8 vswing:4;
0674 } __packed;
0675 
0676 struct edp_apical_params {
0677     u32 panel_oui;
0678     u32 dpcd_base_address;
0679     u32 dpcd_idridix_control_0;
0680     u32 dpcd_option_select;
0681     u32 dpcd_backlight;
0682     u32 ambient_light;
0683     u32 backlight_scale;
0684 } __packed;
0685 
0686 struct bdb_edp {
0687     struct edp_power_seq power_seqs[16];
0688     u32 color_depth;
0689     struct edp_fast_link_params fast_link_params[16];
0690     u32 sdrrs_msa_timing_delay;
0691 
0692     /* ith bit indicates enabled/disabled for (i+1)th panel */
0693     u16 edp_s3d_feature;                    /* 162 */
0694     u16 edp_t3_optimization;                /* 165 */
0695     u64 edp_vswing_preemph;                 /* 173 */
0696     u16 fast_link_training;                 /* 182 */
0697     u16 dpcd_600h_write_required;               /* 185 */
0698     struct edp_pwm_delays pwm_delays[16];           /* 186 */
0699     u16 full_link_params_provided;              /* 199 */
0700     struct edp_full_link_params full_link_params[16];   /* 199 */
0701     u16 apical_enable;                  /* 203 */
0702     struct edp_apical_params apical_params[16];     /* 203 */
0703     u16 edp_fast_link_training_rate[16];            /* 224 */
0704     u16 edp_max_port_link_rate[16];             /* 244 */
0705 } __packed;
0706 
0707 /*
0708  * Block 40 - LFP Data Block
0709  */
0710 
0711 struct bdb_lvds_options {
0712     u8 panel_type;
0713     u8 panel_type2;                     /* 212 */
0714     /* LVDS capabilities, stored in a dword */
0715     u8 pfit_mode:2;
0716     u8 pfit_text_mode_enhanced:1;
0717     u8 pfit_gfx_mode_enhanced:1;
0718     u8 pfit_ratio_auto:1;
0719     u8 pixel_dither:1;
0720     u8 lvds_edid:1;
0721     u8 rsvd2:1;
0722     u8 rsvd4;
0723     /* LVDS Panel channel bits stored here */
0724     u32 lvds_panel_channel_bits;
0725     /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
0726     u16 ssc_bits;
0727     u16 ssc_freq;
0728     u16 ssc_ddt;
0729     /* Panel color depth defined here */
0730     u16 panel_color_depth;
0731     /* LVDS panel type bits stored here */
0732     u32 dps_panel_type_bits;
0733     /* LVDS backlight control type bits stored here */
0734     u32 blt_control_type_bits;
0735 
0736     u16 lcdvcc_s0_enable;                   /* 200 */
0737     u32 rotation;                       /* 228 */
0738     u32 position;                       /* 240 */
0739 } __packed;
0740 
0741 /*
0742  * Block 41 - LFP Data Table Pointers
0743  */
0744 struct lvds_lfp_data_ptr_table {
0745     u16 offset; /* offsets are from start of bdb */
0746     u8 table_size;
0747 } __packed;
0748 
0749 /* LFP pointer table contains entries to the struct below */
0750 struct lvds_lfp_data_ptr {
0751     struct lvds_lfp_data_ptr_table fp_timing;
0752     struct lvds_lfp_data_ptr_table dvo_timing;
0753     struct lvds_lfp_data_ptr_table panel_pnp_id;
0754 } __packed;
0755 
0756 struct bdb_lvds_lfp_data_ptrs {
0757     u8 lvds_entries;
0758     struct lvds_lfp_data_ptr ptr[16];
0759     struct lvds_lfp_data_ptr_table panel_name; /* 156-163? */
0760 } __packed;
0761 
0762 /*
0763  * Block 42 - LFP Data Tables
0764  */
0765 
0766 /* LFP data has 3 blocks per entry */
0767 struct lvds_fp_timing {
0768     u16 x_res;
0769     u16 y_res;
0770     u32 lvds_reg;
0771     u32 lvds_reg_val;
0772     u32 pp_on_reg;
0773     u32 pp_on_reg_val;
0774     u32 pp_off_reg;
0775     u32 pp_off_reg_val;
0776     u32 pp_cycle_reg;
0777     u32 pp_cycle_reg_val;
0778     u32 pfit_reg;
0779     u32 pfit_reg_val;
0780     u16 terminator;
0781 } __packed;
0782 
0783 struct lvds_pnp_id {
0784     u16 mfg_name;
0785     u16 product_code;
0786     u32 serial;
0787     u8 mfg_week;
0788     u8 mfg_year;
0789 } __packed;
0790 
0791 /*
0792  * For reference only. fp_timing has variable size so
0793  * the data must be accessed using the data table pointers.
0794  * Do not use this directly!
0795  */
0796 struct lvds_lfp_data_entry {
0797     struct lvds_fp_timing fp_timing;
0798     struct lvds_dvo_timing dvo_timing;
0799     struct lvds_pnp_id pnp_id;
0800 } __packed;
0801 
0802 struct bdb_lvds_lfp_data {
0803     struct lvds_lfp_data_entry data[16];
0804 } __packed;
0805 
0806 struct lvds_lfp_panel_name {
0807     u8 name[13];
0808 } __packed;
0809 
0810 struct lvds_lfp_black_border {
0811     u8 top; /* 227 */
0812     u8 bottom; /* 227 */
0813     u8 left; /* 238 */
0814     u8 right; /* 238 */
0815 } __packed;
0816 
0817 struct bdb_lvds_lfp_data_tail {
0818     struct lvds_lfp_panel_name panel_name[16]; /* 156-163? */
0819     u16 scaling_enable; /* 187 */
0820     u8 seamless_drrs_min_refresh_rate[16]; /* 188 */
0821     u8 pixel_overlap_count[16]; /* 208 */
0822     struct lvds_lfp_black_border black_border[16]; /* 227 */
0823     u16 dual_lfp_port_sync_enable; /* 231 */
0824     u16 gpu_dithering_for_banding_artifacts; /* 245 */
0825 } __packed;
0826 
0827 /*
0828  * Block 43 - LFP Backlight Control Data Block
0829  */
0830 
0831 #define BDB_BACKLIGHT_TYPE_NONE 0
0832 #define BDB_BACKLIGHT_TYPE_PWM  2
0833 
0834 struct lfp_backlight_data_entry {
0835     u8 type:2;
0836     u8 active_low_pwm:1;
0837     u8 obsolete1:5;
0838     u16 pwm_freq_hz;
0839     u8 min_brightness; /* Obsolete from 234+ */
0840     u8 obsolete2;
0841     u8 obsolete3;
0842 } __packed;
0843 
0844 struct lfp_backlight_control_method {
0845     u8 type:4;
0846     u8 controller:4;
0847 } __packed;
0848 
0849 struct lfp_brightness_level {
0850     u16 level;
0851     u16 reserved;
0852 } __packed;
0853 
0854 #define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \
0855     offsetof(struct bdb_lfp_backlight_data, brightness_level)
0856 #define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \
0857     offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits)
0858 
0859 struct bdb_lfp_backlight_data {
0860     u8 entry_size;
0861     struct lfp_backlight_data_entry data[16];
0862     u8 level[16]; /* Obsolete from 234+ */
0863     struct lfp_backlight_control_method backlight_control[16];
0864     struct lfp_brightness_level brightness_level[16];       /* 234+ */
0865     struct lfp_brightness_level brightness_min_level[16];       /* 234+ */
0866     u8 brightness_precision_bits[16];               /* 236+ */
0867     u16 hdr_dpcd_refresh_timeout[16];               /* 239+ */
0868 } __packed;
0869 
0870 /*
0871  * Block 44 - LFP Power Conservation Features Block
0872  */
0873 struct lfp_power_features {
0874     u8 reserved1:1;
0875     u8 power_conservation_pref:3;
0876     u8 reserved2:1;
0877     u8 lace_enabled_status:1;
0878     u8 lace_support:1;
0879     u8 als_enable:1;
0880 } __packed;
0881 
0882 struct als_data_entry {
0883     u16 backlight_adjust;
0884     u16 lux;
0885 } __packed;
0886 
0887 struct aggressiveness_profile_entry {
0888     u8 dpst_aggressiveness : 4;
0889     u8 lace_aggressiveness : 4;
0890 } __packed;
0891 
0892 struct aggressiveness_profile2_entry {
0893     u8 opst_aggressiveness : 4;
0894     u8 elp_aggressiveness : 4;
0895 } __packed;
0896 
0897 struct bdb_lfp_power {
0898     struct lfp_power_features features;
0899     struct als_data_entry als[5];
0900     u8 lace_aggressiveness_profile:3;
0901     u8 reserved1:5;
0902     u16 dpst;
0903     u16 psr;
0904     u16 drrs;
0905     u16 lace_support;
0906     u16 adt;
0907     u16 dmrrs;
0908     u16 adb;
0909     u16 lace_enabled_status;
0910     struct aggressiveness_profile_entry aggressiveness[16];
0911     u16 hobl; /* 232+ */
0912     u16 vrr_feature_enabled; /* 233+ */
0913     u16 elp; /* 247+ */
0914     u16 opst; /* 247+ */
0915     struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */
0916 } __packed;
0917 
0918 /*
0919  * Block 52 - MIPI Configuration Block
0920  */
0921 
0922 #define MAX_MIPI_CONFIGURATIONS 6
0923 
0924 struct bdb_mipi_config {
0925     struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175 */
0926     struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177 */
0927     struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186 */
0928     u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190 */
0929 } __packed;
0930 
0931 /*
0932  * Block 53 - MIPI Sequence Block
0933  */
0934 
0935 struct bdb_mipi_sequence {
0936     u8 version;
0937     u8 data[]; /* up to 6 variable length blocks */
0938 } __packed;
0939 
0940 /*
0941  * Block 56 - Compression Parameters
0942  */
0943 
0944 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB    0
0945 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB    1
0946 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB   2
0947 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB   3
0948 
0949 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value)    ((vbt_value) + 8) /* bits */
0950 #define VBT_DSC_MAX_BPP(vbt_value)      (6 + (vbt_value) * 2)
0951 
0952 struct dsc_compression_parameters_entry {
0953     u8 version_major:4;
0954     u8 version_minor:4;
0955 
0956     u8 rc_buffer_block_size:2;
0957     u8 reserved1:6;
0958 
0959     /*
0960      * Buffer size in bytes:
0961      *
0962      * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes
0963      */
0964     u8 rc_buffer_size;
0965     u32 slices_per_line;
0966 
0967     u8 line_buffer_depth:4;
0968     u8 reserved2:4;
0969 
0970     /* Flag Bits 1 */
0971     u8 block_prediction_enable:1;
0972     u8 reserved3:7;
0973 
0974     u8 max_bpp; /* mapping */
0975 
0976     /* Color depth capabilities */
0977     u8 reserved4:1;
0978     u8 support_8bpc:1;
0979     u8 support_10bpc:1;
0980     u8 support_12bpc:1;
0981     u8 reserved5:4;
0982 
0983     u16 slice_height;
0984 } __packed;
0985 
0986 struct bdb_compression_parameters {
0987     u16 entry_size;
0988     struct dsc_compression_parameters_entry data[16];
0989 } __packed;
0990 
0991 /*
0992  * Block 58 - Generic DTD Block
0993  */
0994 
0995 struct generic_dtd_entry {
0996     u32 pixel_clock;
0997     u16 hactive;
0998     u16 hblank;
0999     u16 hfront_porch;
1000     u16 hsync;
1001     u16 vactive;
1002     u16 vblank;
1003     u16 vfront_porch;
1004     u16 vsync;
1005     u16 width_mm;
1006     u16 height_mm;
1007 
1008     /* Flags */
1009     u8 rsvd_flags:6;
1010     u8 vsync_positive_polarity:1;
1011     u8 hsync_positive_polarity:1;
1012 
1013     u8 rsvd[3];
1014 } __packed;
1015 
1016 struct bdb_generic_dtd {
1017     u16 gdtd_size;
1018     struct generic_dtd_entry dtd[]; /* up to 24 DTD's */
1019 } __packed;
1020 
1021 #endif /* _INTEL_VBT_DEFS_H_ */
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