0001
0002
0003
0004
0005
0006 #ifndef __INTEL_TC_PHY_REGS__
0007 #define __INTEL_TC_PHY_REGS__
0008
0009 #include "i915_reg_defs.h"
0010
0011 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
0012 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
0013
0014 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
0015 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
0016 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
0017 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
0018 #define MG_TX1_LINK_PARAMS(ln, tc_port) \
0019 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
0020 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
0021 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
0022
0023 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
0024 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
0025 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
0026 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
0027 #define MG_TX2_LINK_PARAMS(ln, tc_port) \
0028 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
0029 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
0030 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
0031 #define CRI_USE_FS32 (1 << 5)
0032
0033 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
0034 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
0035 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
0036 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
0037 #define MG_TX1_PISO_READLOAD(ln, tc_port) \
0038 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
0039 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
0040 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
0041
0042 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
0043 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
0044 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
0045 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
0046 #define MG_TX2_PISO_READLOAD(ln, tc_port) \
0047 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
0048 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
0049 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
0050 #define CRI_CALCINIT (1 << 1)
0051
0052 #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
0053 #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
0054 #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
0055 #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
0056 #define MG_TX1_SWINGCTRL(ln, tc_port) \
0057 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
0058 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
0059 MG_TX_SWINGCTRL_TX1LN1_PORT1)
0060
0061 #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
0062 #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
0063 #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
0064 #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
0065 #define MG_TX2_SWINGCTRL(ln, tc_port) \
0066 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
0067 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
0068 MG_TX_SWINGCTRL_TX2LN1_PORT1)
0069 #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
0070 #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
0071
0072 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
0073 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
0074 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
0075 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
0076 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
0077 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
0078 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
0079 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
0080 #define MG_TX1_DRVCTRL(ln, tc_port) \
0081 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
0082 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
0083 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
0084
0085 #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
0086 #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
0087 #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
0088 #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
0089 #define MG_TX2_DRVCTRL(ln, tc_port) \
0090 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
0091 MG_TX_DRVCTRL_TX2LN0_PORT2, \
0092 MG_TX_DRVCTRL_TX2LN1_PORT1)
0093 #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
0094 #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
0095 #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
0096 #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
0097 #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
0098 #define CRI_LOADGEN_SEL(x) ((x) << 12)
0099 #define CRI_LOADGEN_SEL_MASK (0x3 << 12)
0100
0101 #define MG_CLKHUB_LN0_PORT1 0x16839C
0102 #define MG_CLKHUB_LN1_PORT1 0x16879C
0103 #define MG_CLKHUB_LN0_PORT2 0x16939C
0104 #define MG_CLKHUB_LN1_PORT2 0x16979C
0105 #define MG_CLKHUB(ln, tc_port) \
0106 MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
0107 MG_CLKHUB_LN0_PORT2, \
0108 MG_CLKHUB_LN1_PORT1)
0109 #define CFG_LOW_RATE_LKREN_EN (1 << 11)
0110
0111 #define MG_TX_DCC_TX1LN0_PORT1 0x168110
0112 #define MG_TX_DCC_TX1LN1_PORT1 0x168510
0113 #define MG_TX_DCC_TX1LN0_PORT2 0x169110
0114 #define MG_TX_DCC_TX1LN1_PORT2 0x169510
0115 #define MG_TX1_DCC(ln, tc_port) \
0116 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
0117 MG_TX_DCC_TX1LN0_PORT2, \
0118 MG_TX_DCC_TX1LN1_PORT1)
0119 #define MG_TX_DCC_TX2LN0_PORT1 0x168090
0120 #define MG_TX_DCC_TX2LN1_PORT1 0x168490
0121 #define MG_TX_DCC_TX2LN0_PORT2 0x169090
0122 #define MG_TX_DCC_TX2LN1_PORT2 0x169490
0123 #define MG_TX2_DCC(ln, tc_port) \
0124 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
0125 MG_TX_DCC_TX2LN0_PORT2, \
0126 MG_TX_DCC_TX2LN1_PORT1)
0127 #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
0128 #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
0129 #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
0130
0131 #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
0132 #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
0133 #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
0134 #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
0135 #define MG_DP_MODE(ln, tc_port) \
0136 MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
0137 MG_DP_MODE_LN0_ACU_PORT2, \
0138 MG_DP_MODE_LN1_ACU_PORT1)
0139 #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
0140 #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
0141
0142 #define FIA1_BASE 0x163000
0143 #define FIA2_BASE 0x16E000
0144 #define FIA3_BASE 0x16F000
0145 #define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
0146 #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
0147
0148
0149 #define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
0150 #define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
0151 #define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
0152 #define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
0153 #define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
0154 #define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
0155 #define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
0156
0157 #define _MG_REFCLKIN_CTL_PORT1 0x16892C
0158 #define _MG_REFCLKIN_CTL_PORT2 0x16992C
0159 #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
0160 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
0161 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
0162 _MG_REFCLKIN_CTL_PORT1, \
0163 _MG_REFCLKIN_CTL_PORT2)
0164
0165 #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
0166 #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
0167 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
0168 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
0169 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
0170 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
0171 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
0172 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
0173 _MG_CLKTOP2_CORECLKCTL1_PORT2)
0174
0175 #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
0176 #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
0177 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
0178 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
0179 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
0180 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
0181 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
0182 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
0183 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
0184 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
0185 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
0186 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
0187 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
0188 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
0189 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
0190 _MG_CLKTOP2_HSCLKCTL_PORT1, \
0191 _MG_CLKTOP2_HSCLKCTL_PORT2)
0192
0193 #define _MG_PLL_DIV0_PORT1 0x168A00
0194 #define _MG_PLL_DIV0_PORT2 0x169A00
0195 #define MG_PLL_DIV0_FRACNEN_H (1 << 30)
0196 #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
0197 #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
0198 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
0199 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
0200 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
0201 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
0202 _MG_PLL_DIV0_PORT2)
0203
0204 #define _MG_PLL_DIV1_PORT1 0x168A04
0205 #define _MG_PLL_DIV1_PORT2 0x169A04
0206 #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
0207 #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
0208 #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
0209 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
0210 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
0211 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
0212 #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
0213 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
0214 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
0215 _MG_PLL_DIV1_PORT2)
0216
0217 #define _MG_PLL_LF_PORT1 0x168A08
0218 #define _MG_PLL_LF_PORT2 0x169A08
0219 #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
0220 #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
0221 #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
0222 #define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
0223 #define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
0224 #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
0225 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
0226 _MG_PLL_LF_PORT2)
0227
0228 #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
0229 #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
0230 #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
0231 #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
0232 #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
0233 #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
0234 #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
0235 #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
0236 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
0237 _MG_PLL_FRAC_LOCK_PORT1, \
0238 _MG_PLL_FRAC_LOCK_PORT2)
0239
0240 #define _MG_PLL_SSC_PORT1 0x168A10
0241 #define _MG_PLL_SSC_PORT2 0x169A10
0242 #define MG_PLL_SSC_EN (1 << 28)
0243 #define MG_PLL_SSC_TYPE(x) ((x) << 26)
0244 #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
0245 #define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
0246 #define MG_PLL_SSC_FLLEN (1 << 9)
0247 #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
0248 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
0249 _MG_PLL_SSC_PORT2)
0250
0251 #define _MG_PLL_BIAS_PORT1 0x168A14
0252 #define _MG_PLL_BIAS_PORT2 0x169A14
0253 #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
0254 #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
0255 #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
0256 #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
0257 #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
0258 #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
0259 #define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
0260 #define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
0261 #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
0262 #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
0263 #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
0264 #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
0265 #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
0266 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
0267 _MG_PLL_BIAS_PORT2)
0268
0269 #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
0270 #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
0271 #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
0272 #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
0273 #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
0274 #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
0275 #define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
0276 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
0277 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
0278 _MG_PLL_TDC_COLDST_BIAS_PORT2)
0279
0280 #endif
