i915/display/intel_snps_phy_regs.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_SNPS_PHY_REGS__
0007 #define __INTEL_SNPS_PHY_REGS__
0008
0009 #include "i915_reg_defs.h"
0010
0011 #define _SNPS_PHY_A_BASE            0x168000
0012 #define _SNPS_PHY_B_BASE            0x169000
0013 #define _SNPS_PHY(phy)              _PHY(phy, \
0014                              _SNPS_PHY_A_BASE, \
0015                              _SNPS_PHY_B_BASE)
0016 #define _SNPS2(phy, reg)            (_SNPS_PHY(phy) - \
0017                          _SNPS_PHY_A_BASE + (reg))
0018 #define _MMIO_SNPS(phy, reg)            _MMIO(_SNPS2(phy, reg))
0019 #define _MMIO_SNPS_LN(ln, phy, reg)     _MMIO(_SNPS2(phy, \
0020                                  (reg) + (ln) * 0x10))
0021
0022 #define SNPS_PHY_MPLLB_CP(phy)          _MMIO_SNPS(phy, 0x168000)
0023 #define   SNPS_PHY_MPLLB_CP_INT         REG_GENMASK(31, 25)
0024 #define   SNPS_PHY_MPLLB_CP_INT_GS      REG_GENMASK(23, 17)
0025 #define   SNPS_PHY_MPLLB_CP_PROP        REG_GENMASK(15, 9)
0026 #define   SNPS_PHY_MPLLB_CP_PROP_GS     REG_GENMASK(7, 1)
0027
0028 #define SNPS_PHY_MPLLB_DIV(phy)         _MMIO_SNPS(phy, 0x168004)
0029 #define   SNPS_PHY_MPLLB_FORCE_EN       REG_BIT(31)
0030 #define   SNPS_PHY_MPLLB_DIV_CLK_EN     REG_BIT(30)
0031 #define   SNPS_PHY_MPLLB_DIV5_CLK_EN        REG_BIT(29)
0032 #define   SNPS_PHY_MPLLB_V2I            REG_GENMASK(27, 26)
0033 #define   SNPS_PHY_MPLLB_FREQ_VCO       REG_GENMASK(25, 24)
0034 #define   SNPS_PHY_MPLLB_DIV_MULTIPLIER     REG_GENMASK(23, 16)
0035 #define   SNPS_PHY_MPLLB_PMIX_EN        REG_BIT(10)
0036 #define   SNPS_PHY_MPLLB_DP2_MODE       REG_BIT(9)
0037 #define   SNPS_PHY_MPLLB_WORD_DIV2_EN       REG_BIT(8)
0038 #define   SNPS_PHY_MPLLB_TX_CLK_DIV     REG_GENMASK(7, 5)
0039 #define   SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
0040
0041 #define SNPS_PHY_MPLLB_FRACN1(phy)      _MMIO_SNPS(phy, 0x168008)
0042 #define   SNPS_PHY_MPLLB_FRACN_EN       REG_BIT(31)
0043 #define   SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN    REG_BIT(30)
0044 #define   SNPS_PHY_MPLLB_FRACN_DEN      REG_GENMASK(15, 0)
0045
0046 #define SNPS_PHY_MPLLB_FRACN2(phy)      _MMIO_SNPS(phy, 0x16800C)
0047 #define   SNPS_PHY_MPLLB_FRACN_REM      REG_GENMASK(31, 16)
0048 #define   SNPS_PHY_MPLLB_FRACN_QUOT     REG_GENMASK(15, 0)
0049
0050 #define SNPS_PHY_MPLLB_SSCEN(phy)       _MMIO_SNPS(phy, 0x168014)
0051 #define   SNPS_PHY_MPLLB_SSC_EN         REG_BIT(31)
0052 #define   SNPS_PHY_MPLLB_SSC_UP_SPREAD      REG_BIT(30)
0053 #define   SNPS_PHY_MPLLB_SSC_PEAK       REG_GENMASK(29, 10)
0054
0055 #define SNPS_PHY_MPLLB_SSCSTEP(phy)     _MMIO_SNPS(phy, 0x168018)
0056 #define   SNPS_PHY_MPLLB_SSC_STEPSIZE       REG_GENMASK(31, 11)
0057
0058 #define SNPS_PHY_MPLLB_DIV2(phy)        _MMIO_SNPS(phy, 0x16801C)
0059 #define   SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
0060 #define   SNPS_PHY_MPLLB_HDMI_DIV       REG_GENMASK(17, 15)
0061 #define   SNPS_PHY_MPLLB_REF_CLK_DIV        REG_GENMASK(14, 12)
0062 #define   SNPS_PHY_MPLLB_MULTIPLIER     REG_GENMASK(11, 0)
0063
0064 #define SNPS_PHY_REF_CONTROL(phy)       _MMIO_SNPS(phy, 0x168188)
0065 #define   SNPS_PHY_REF_CONTROL_REF_RANGE    REG_GENMASK(31, 27)
0066
0067 #define SNPS_PHY_TX_REQ(phy)            _MMIO_SNPS(phy, 0x168200)
0068 #define   SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR  REG_GENMASK(31, 30)
0069
0070 #define SNPS_PHY_TX_EQ(ln, phy)         _MMIO_SNPS_LN(ln, phy, 0x168300)
0071 #define   SNPS_PHY_TX_EQ_MAIN           REG_GENMASK(23, 18)
0072 #define   SNPS_PHY_TX_EQ_POST           REG_GENMASK(15, 10)
0073 #define   SNPS_PHY_TX_EQ_PRE            REG_GENMASK(7, 2)
0074
0075 #endif /* __INTEL_SNPS_PHY_REGS__ */