i915/display/intel_sdvo_regs.h

0001 /*
0002  * Copyright © 2006-2007 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0021  * DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors:
0024  *  Eric Anholt <eric@anholt.net>
0025  */
0026
0027 #ifndef __INTEL_SDVO_REGS_H__
0028 #define __INTEL_SDVO_REGS_H__
0029
0030 #include <linux/compiler.h>
0031 #include <linux/types.h>
0032
0033 /*
0034  * SDVO command definitions and structures.
0035  */
0036
0037 #define SDVO_OUTPUT_FIRST   (0)
0038 #define SDVO_OUTPUT_TMDS0   (1 << 0)
0039 #define SDVO_OUTPUT_RGB0    (1 << 1)
0040 #define SDVO_OUTPUT_CVBS0   (1 << 2)
0041 #define SDVO_OUTPUT_SVID0   (1 << 3)
0042 #define SDVO_OUTPUT_YPRPB0  (1 << 4)
0043 #define SDVO_OUTPUT_SCART0  (1 << 5)
0044 #define SDVO_OUTPUT_LVDS0   (1 << 6)
0045 #define SDVO_OUTPUT_TMDS1   (1 << 8)
0046 #define SDVO_OUTPUT_RGB1    (1 << 9)
0047 #define SDVO_OUTPUT_CVBS1   (1 << 10)
0048 #define SDVO_OUTPUT_SVID1   (1 << 11)
0049 #define SDVO_OUTPUT_YPRPB1  (1 << 12)
0050 #define SDVO_OUTPUT_SCART1  (1 << 13)
0051 #define SDVO_OUTPUT_LVDS1   (1 << 14)
0052 #define SDVO_OUTPUT_LAST    (14)
0053
0054 struct intel_sdvo_caps {
0055     u8 vendor_id;
0056     u8 device_id;
0057     u8 device_rev_id;
0058     u8 sdvo_version_major;
0059     u8 sdvo_version_minor;
0060     unsigned int sdvo_inputs_mask:2;
0061     unsigned int smooth_scaling:1;
0062     unsigned int sharp_scaling:1;
0063     unsigned int up_scaling:1;
0064     unsigned int down_scaling:1;
0065     unsigned int stall_support:1;
0066     unsigned int pad:1;
0067     u16 output_flags;
0068 } __packed;
0069
0070 /* Note: SDVO detailed timing flags match EDID misc flags. */
0071 #define DTD_FLAG_HSYNC_POSITIVE (1 << 1)
0072 #define DTD_FLAG_VSYNC_POSITIVE (1 << 2)
0073 #define DTD_FLAG_INTERLACE  (1 << 7)
0074
0075 /* This matches the EDID DTD structure, more or less */
0076 struct intel_sdvo_dtd {
0077     struct {
0078         u16 clock;  /* pixel clock, in 10kHz units */
0079         u8 h_active;    /* lower 8 bits (pixels) */
0080         u8 h_blank; /* lower 8 bits (pixels) */
0081         u8 h_high;  /* upper 4 bits each h_active, h_blank */
0082         u8 v_active;    /* lower 8 bits (lines) */
0083         u8 v_blank; /* lower 8 bits (lines) */
0084         u8 v_high;  /* upper 4 bits each v_active, v_blank */
0085     } part1;
0086
0087     struct {
0088         u8 h_sync_off;  /* lower 8 bits, from hblank start */
0089         u8 h_sync_width;    /* lower 8 bits (pixels) */
0090         /* lower 4 bits each vsync offset, vsync width */
0091         u8 v_sync_off_width;
0092         /*
0093         * 2 high bits of hsync offset, 2 high bits of hsync width,
0094         * bits 4-5 of vsync offset, and 2 high bits of vsync width.
0095         */
0096         u8 sync_off_width_high;
0097         u8 dtd_flags;
0098         u8 sdvo_flags;
0099         /* bits 6-7 of vsync offset at bits 6-7 */
0100         u8 v_sync_off_high;
0101         u8 reserved;
0102     } part2;
0103 } __packed;
0104
0105 struct intel_sdvo_pixel_clock_range {
0106     u16 min;    /* pixel clock, in 10kHz units */
0107     u16 max;    /* pixel clock, in 10kHz units */
0108 } __packed;
0109
0110 struct intel_sdvo_preferred_input_timing_args {
0111     u16 clock;
0112     u16 width;
0113     u16 height;
0114     u8  interlace:1;
0115     u8  scaled:1;
0116     u8  pad:6;
0117 } __packed;
0118
0119 /* I2C registers for SDVO */
0120 #define SDVO_I2C_ARG_0              0x07
0121 #define SDVO_I2C_ARG_1              0x06
0122 #define SDVO_I2C_ARG_2              0x05
0123 #define SDVO_I2C_ARG_3              0x04
0124 #define SDVO_I2C_ARG_4              0x03
0125 #define SDVO_I2C_ARG_5              0x02
0126 #define SDVO_I2C_ARG_6              0x01
0127 #define SDVO_I2C_ARG_7              0x00
0128 #define SDVO_I2C_OPCODE             0x08
0129 #define SDVO_I2C_CMD_STATUS         0x09
0130 #define SDVO_I2C_RETURN_0           0x0a
0131 #define SDVO_I2C_RETURN_1           0x0b
0132 #define SDVO_I2C_RETURN_2           0x0c
0133 #define SDVO_I2C_RETURN_3           0x0d
0134 #define SDVO_I2C_RETURN_4           0x0e
0135 #define SDVO_I2C_RETURN_5           0x0f
0136 #define SDVO_I2C_RETURN_6           0x10
0137 #define SDVO_I2C_RETURN_7           0x11
0138 #define SDVO_I2C_VENDOR_BEGIN           0x20
0139
0140 /* Status results */
0141 #define SDVO_CMD_STATUS_POWER_ON        0x0
0142 #define SDVO_CMD_STATUS_SUCCESS         0x1
0143 #define SDVO_CMD_STATUS_NOTSUPP         0x2
0144 #define SDVO_CMD_STATUS_INVALID_ARG     0x3
0145 #define SDVO_CMD_STATUS_PENDING         0x4
0146 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED    0x5
0147 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP    0x6
0148
0149 /* SDVO commands, argument/result registers */
0150
0151 #define SDVO_CMD_RESET                  0x01
0152
0153 /* Returns a struct intel_sdvo_caps */
0154 #define SDVO_CMD_GET_DEVICE_CAPS            0x02
0155
0156 #define SDVO_CMD_GET_FIRMWARE_REV           0x86
0157 # define SDVO_DEVICE_FIRMWARE_MINOR         SDVO_I2C_RETURN_0
0158 # define SDVO_DEVICE_FIRMWARE_MAJOR         SDVO_I2C_RETURN_1
0159 # define SDVO_DEVICE_FIRMWARE_PATCH         SDVO_I2C_RETURN_2
0160
0161 /*
0162  * Reports which inputs are trained (managed to sync).
0163  *
0164  * Devices must have trained within 2 vsyncs of a mode change.
0165  */
0166 #define SDVO_CMD_GET_TRAINED_INPUTS         0x03
0167 struct intel_sdvo_get_trained_inputs_response {
0168     unsigned int input0_trained:1;
0169     unsigned int input1_trained:1;
0170     unsigned int pad:6;
0171 } __packed;
0172
0173 /* Returns a struct intel_sdvo_output_flags of active outputs. */
0174 #define SDVO_CMD_GET_ACTIVE_OUTPUTS         0x04
0175
0176 /*
0177  * Sets the current set of active outputs.
0178  *
0179  * Takes a struct intel_sdvo_output_flags.  Must be preceded by a SET_IN_OUT_MAP
0180  * on multi-output devices.
0181  */
0182 #define SDVO_CMD_SET_ACTIVE_OUTPUTS         0x05
0183
0184 /*
0185  * Returns the current mapping of SDVO inputs to outputs on the device.
0186  *
0187  * Returns two struct intel_sdvo_output_flags structures.
0188  */
0189 #define SDVO_CMD_GET_IN_OUT_MAP             0x06
0190 struct intel_sdvo_in_out_map {
0191     u16 in0, in1;
0192 };
0193
0194 /*
0195  * Sets the current mapping of SDVO inputs to outputs on the device.
0196  *
0197  * Takes two struct i380_sdvo_output_flags structures.
0198  */
0199 #define SDVO_CMD_SET_IN_OUT_MAP             0x07
0200
0201 /*
0202  * Returns a struct intel_sdvo_output_flags of attached displays.
0203  */
0204 #define SDVO_CMD_GET_ATTACHED_DISPLAYS          0x0b
0205
0206 /*
0207  * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
0208  */
0209 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT           0x0c
0210
0211 /*
0212  * Takes a struct intel_sdvo_output_flags.
0213  */
0214 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG            0x0d
0215
0216 /*
0217  * Returns a struct intel_sdvo_output_flags of displays with hot plug
0218  * interrupts enabled.
0219  */
0220 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG            0x0e
0221
0222 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE     0x0f
0223 struct intel_sdvo_get_interrupt_event_source_response {
0224     u16 interrupt_status;
0225     unsigned int ambient_light_interrupt:1;
0226     unsigned int hdmi_audio_encrypt_change:1;
0227     unsigned int pad:6;
0228 } __packed;
0229
0230 /*
0231  * Selects which input is affected by future input commands.
0232  *
0233  * Commands affected include SET_INPUT_TIMINGS_PART[12],
0234  * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
0235  * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
0236  */
0237 #define SDVO_CMD_SET_TARGET_INPUT           0x10
0238 struct intel_sdvo_set_target_input_args {
0239     unsigned int target_1:1;
0240     unsigned int pad:7;
0241 } __packed;
0242
0243 /*
0244  * Takes a struct intel_sdvo_output_flags of which outputs are targeted by
0245  * future output commands.
0246  *
0247  * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
0248  * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
0249  */
0250 #define SDVO_CMD_SET_TARGET_OUTPUT          0x11
0251
0252 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1        0x12
0253 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2        0x13
0254 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1        0x14
0255 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2        0x15
0256 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1       0x16
0257 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2       0x17
0258 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1       0x18
0259 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2       0x19
0260 /* Part 1 */
0261 # define SDVO_DTD_CLOCK_LOW             SDVO_I2C_ARG_0
0262 # define SDVO_DTD_CLOCK_HIGH                SDVO_I2C_ARG_1
0263 # define SDVO_DTD_H_ACTIVE              SDVO_I2C_ARG_2
0264 # define SDVO_DTD_H_BLANK               SDVO_I2C_ARG_3
0265 # define SDVO_DTD_H_HIGH                SDVO_I2C_ARG_4
0266 # define SDVO_DTD_V_ACTIVE              SDVO_I2C_ARG_5
0267 # define SDVO_DTD_V_BLANK               SDVO_I2C_ARG_6
0268 # define SDVO_DTD_V_HIGH                SDVO_I2C_ARG_7
0269 /* Part 2 */
0270 # define SDVO_DTD_HSYNC_OFF             SDVO_I2C_ARG_0
0271 # define SDVO_DTD_HSYNC_WIDTH               SDVO_I2C_ARG_1
0272 # define SDVO_DTD_VSYNC_OFF_WIDTH           SDVO_I2C_ARG_2
0273 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH           SDVO_I2C_ARG_3
0274 # define SDVO_DTD_DTD_FLAGS             SDVO_I2C_ARG_4
0275 # define SDVO_DTD_DTD_FLAG_INTERLACED               (1 << 7)
0276 # define SDVO_DTD_DTD_FLAG_STEREO_MASK              (3 << 5)
0277 # define SDVO_DTD_DTD_FLAG_INPUT_MASK               (3 << 3)
0278 # define SDVO_DTD_DTD_FLAG_SYNC_MASK                (3 << 1)
0279 # define SDVO_DTD_SDVO_FLAS             SDVO_I2C_ARG_5
0280 # define SDVO_DTD_SDVO_FLAG_STALL               (1 << 7)
0281 # define SDVO_DTD_SDVO_FLAG_CENTERED                (0 << 6)
0282 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT              (1 << 6)
0283 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK            (3 << 4)
0284 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE            (0 << 4)
0285 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP           (1 << 4)
0286 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH          (2 << 4)
0287 # define SDVO_DTD_VSYNC_OFF_HIGH            SDVO_I2C_ARG_6
0288
0289 /*
0290  * Generates a DTD based on the given width, height, and flags.
0291  *
0292  * This will be supported by any device supporting scaling or interlaced
0293  * modes.
0294  */
0295 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING      0x1a
0296 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW      SDVO_I2C_ARG_0
0297 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH     SDVO_I2C_ARG_1
0298 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW      SDVO_I2C_ARG_2
0299 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH     SDVO_I2C_ARG_3
0300 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW     SDVO_I2C_ARG_4
0301 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH    SDVO_I2C_ARG_5
0302 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS      SDVO_I2C_ARG_6
0303 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED       (1 << 0)
0304 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED       (1 << 1)
0305
0306 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1   0x1b
0307 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2   0x1c
0308
0309 /* Returns a struct intel_sdvo_pixel_clock_range */
0310 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE        0x1d
0311 /* Returns a struct intel_sdvo_pixel_clock_range */
0312 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE       0x1e
0313
0314 /* Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
0315 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS     0x1f
0316
0317 /* Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
0318 #define SDVO_CMD_GET_CLOCK_RATE_MULT            0x20
0319 /* Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
0320 #define SDVO_CMD_SET_CLOCK_RATE_MULT            0x21
0321 # define SDVO_CLOCK_RATE_MULT_1X                (1 << 0)
0322 # define SDVO_CLOCK_RATE_MULT_2X                (1 << 1)
0323 # define SDVO_CLOCK_RATE_MULT_4X                (1 << 3)
0324
0325 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS       0x27
0326 /* 6 bytes of bit flags for TV formats shared by all TV format functions */
0327 struct intel_sdvo_tv_format {
0328     unsigned int ntsc_m:1;
0329     unsigned int ntsc_j:1;
0330     unsigned int ntsc_443:1;
0331     unsigned int pal_b:1;
0332     unsigned int pal_d:1;
0333     unsigned int pal_g:1;
0334     unsigned int pal_h:1;
0335     unsigned int pal_i:1;
0336
0337     unsigned int pal_m:1;
0338     unsigned int pal_n:1;
0339     unsigned int pal_nc:1;
0340     unsigned int pal_60:1;
0341     unsigned int secam_b:1;
0342     unsigned int secam_d:1;
0343     unsigned int secam_g:1;
0344     unsigned int secam_k:1;
0345
0346     unsigned int secam_k1:1;
0347     unsigned int secam_l:1;
0348     unsigned int secam_60:1;
0349     unsigned int hdtv_std_smpte_240m_1080i_59:1;
0350     unsigned int hdtv_std_smpte_240m_1080i_60:1;
0351     unsigned int hdtv_std_smpte_260m_1080i_59:1;
0352     unsigned int hdtv_std_smpte_260m_1080i_60:1;
0353     unsigned int hdtv_std_smpte_274m_1080i_50:1;
0354
0355     unsigned int hdtv_std_smpte_274m_1080i_59:1;
0356     unsigned int hdtv_std_smpte_274m_1080i_60:1;
0357     unsigned int hdtv_std_smpte_274m_1080p_23:1;
0358     unsigned int hdtv_std_smpte_274m_1080p_24:1;
0359     unsigned int hdtv_std_smpte_274m_1080p_25:1;
0360     unsigned int hdtv_std_smpte_274m_1080p_29:1;
0361     unsigned int hdtv_std_smpte_274m_1080p_30:1;
0362     unsigned int hdtv_std_smpte_274m_1080p_50:1;
0363
0364     unsigned int hdtv_std_smpte_274m_1080p_59:1;
0365     unsigned int hdtv_std_smpte_274m_1080p_60:1;
0366     unsigned int hdtv_std_smpte_295m_1080i_50:1;
0367     unsigned int hdtv_std_smpte_295m_1080p_50:1;
0368     unsigned int hdtv_std_smpte_296m_720p_59:1;
0369     unsigned int hdtv_std_smpte_296m_720p_60:1;
0370     unsigned int hdtv_std_smpte_296m_720p_50:1;
0371     unsigned int hdtv_std_smpte_293m_480p_59:1;
0372
0373     unsigned int hdtv_std_smpte_170m_480i_59:1;
0374     unsigned int hdtv_std_iturbt601_576i_50:1;
0375     unsigned int hdtv_std_iturbt601_576p_50:1;
0376     unsigned int hdtv_std_eia_7702a_480i_60:1;
0377     unsigned int hdtv_std_eia_7702a_480p_60:1;
0378     unsigned int pad:3;
0379 } __packed;
0380
0381 #define SDVO_CMD_GET_TV_FORMAT              0x28
0382
0383 #define SDVO_CMD_SET_TV_FORMAT              0x29
0384
0385 /* Returns the resolutiosn that can be used with the given TV format */
0386 #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT        0x83
0387 struct intel_sdvo_sdtv_resolution_request {
0388     unsigned int ntsc_m:1;
0389     unsigned int ntsc_j:1;
0390     unsigned int ntsc_443:1;
0391     unsigned int pal_b:1;
0392     unsigned int pal_d:1;
0393     unsigned int pal_g:1;
0394     unsigned int pal_h:1;
0395     unsigned int pal_i:1;
0396
0397     unsigned int pal_m:1;
0398     unsigned int pal_n:1;
0399     unsigned int pal_nc:1;
0400     unsigned int pal_60:1;
0401     unsigned int secam_b:1;
0402     unsigned int secam_d:1;
0403     unsigned int secam_g:1;
0404     unsigned int secam_k:1;
0405
0406     unsigned int secam_k1:1;
0407     unsigned int secam_l:1;
0408     unsigned int secam_60:1;
0409     unsigned int pad:5;
0410 } __packed;
0411
0412 struct intel_sdvo_sdtv_resolution_reply {
0413     unsigned int res_320x200:1;
0414     unsigned int res_320x240:1;
0415     unsigned int res_400x300:1;
0416     unsigned int res_640x350:1;
0417     unsigned int res_640x400:1;
0418     unsigned int res_640x480:1;
0419     unsigned int res_704x480:1;
0420     unsigned int res_704x576:1;
0421
0422     unsigned int res_720x350:1;
0423     unsigned int res_720x400:1;
0424     unsigned int res_720x480:1;
0425     unsigned int res_720x540:1;
0426     unsigned int res_720x576:1;
0427     unsigned int res_768x576:1;
0428     unsigned int res_800x600:1;
0429     unsigned int res_832x624:1;
0430
0431     unsigned int res_920x766:1;
0432     unsigned int res_1024x768:1;
0433     unsigned int res_1280x1024:1;
0434     unsigned int pad:5;
0435 } __packed;
0436
0437 /* Get supported resolution with squire pixel aspect ratio that can be
0438    scaled for the requested HDTV format */
0439 #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT     0x85
0440
0441 struct intel_sdvo_hdtv_resolution_request {
0442     unsigned int hdtv_std_smpte_240m_1080i_59:1;
0443     unsigned int hdtv_std_smpte_240m_1080i_60:1;
0444     unsigned int hdtv_std_smpte_260m_1080i_59:1;
0445     unsigned int hdtv_std_smpte_260m_1080i_60:1;
0446     unsigned int hdtv_std_smpte_274m_1080i_50:1;
0447     unsigned int hdtv_std_smpte_274m_1080i_59:1;
0448     unsigned int hdtv_std_smpte_274m_1080i_60:1;
0449     unsigned int hdtv_std_smpte_274m_1080p_23:1;
0450
0451     unsigned int hdtv_std_smpte_274m_1080p_24:1;
0452     unsigned int hdtv_std_smpte_274m_1080p_25:1;
0453     unsigned int hdtv_std_smpte_274m_1080p_29:1;
0454     unsigned int hdtv_std_smpte_274m_1080p_30:1;
0455     unsigned int hdtv_std_smpte_274m_1080p_50:1;
0456     unsigned int hdtv_std_smpte_274m_1080p_59:1;
0457     unsigned int hdtv_std_smpte_274m_1080p_60:1;
0458     unsigned int hdtv_std_smpte_295m_1080i_50:1;
0459
0460     unsigned int hdtv_std_smpte_295m_1080p_50:1;
0461     unsigned int hdtv_std_smpte_296m_720p_59:1;
0462     unsigned int hdtv_std_smpte_296m_720p_60:1;
0463     unsigned int hdtv_std_smpte_296m_720p_50:1;
0464     unsigned int hdtv_std_smpte_293m_480p_59:1;
0465     unsigned int hdtv_std_smpte_170m_480i_59:1;
0466     unsigned int hdtv_std_iturbt601_576i_50:1;
0467     unsigned int hdtv_std_iturbt601_576p_50:1;
0468
0469     unsigned int hdtv_std_eia_7702a_480i_60:1;
0470     unsigned int hdtv_std_eia_7702a_480p_60:1;
0471     unsigned int pad:6;
0472 } __packed;
0473
0474 struct intel_sdvo_hdtv_resolution_reply {
0475     unsigned int res_640x480:1;
0476     unsigned int res_800x600:1;
0477     unsigned int res_1024x768:1;
0478     unsigned int res_1280x960:1;
0479     unsigned int res_1400x1050:1;
0480     unsigned int res_1600x1200:1;
0481     unsigned int res_1920x1440:1;
0482     unsigned int res_2048x1536:1;
0483
0484     unsigned int res_2560x1920:1;
0485     unsigned int res_3200x2400:1;
0486     unsigned int res_3840x2880:1;
0487     unsigned int pad1:5;
0488
0489     unsigned int res_848x480:1;
0490     unsigned int res_1064x600:1;
0491     unsigned int res_1280x720:1;
0492     unsigned int res_1360x768:1;
0493     unsigned int res_1704x960:1;
0494     unsigned int res_1864x1050:1;
0495     unsigned int res_1920x1080:1;
0496     unsigned int res_2128x1200:1;
0497
0498     unsigned int res_2560x1400:1;
0499     unsigned int res_2728x1536:1;
0500     unsigned int res_3408x1920:1;
0501     unsigned int res_4264x2400:1;
0502     unsigned int res_5120x2880:1;
0503     unsigned int pad2:3;
0504
0505     unsigned int res_768x480:1;
0506     unsigned int res_960x600:1;
0507     unsigned int res_1152x720:1;
0508     unsigned int res_1124x768:1;
0509     unsigned int res_1536x960:1;
0510     unsigned int res_1680x1050:1;
0511     unsigned int res_1728x1080:1;
0512     unsigned int res_1920x1200:1;
0513
0514     unsigned int res_2304x1440:1;
0515     unsigned int res_2456x1536:1;
0516     unsigned int res_3072x1920:1;
0517     unsigned int res_3840x2400:1;
0518     unsigned int res_4608x2880:1;
0519     unsigned int pad3:3;
0520
0521     unsigned int res_1280x1024:1;
0522     unsigned int pad4:7;
0523
0524     unsigned int res_1280x768:1;
0525     unsigned int pad5:7;
0526 } __packed;
0527
0528 /* Get supported power state returns info for encoder and monitor, rely on
0529    last SetTargetInput and SetTargetOutput calls */
0530 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES     0x2a
0531 /* Get power state returns info for encoder and monitor, rely on last
0532    SetTargetInput and SetTargetOutput calls */
0533 #define SDVO_CMD_GET_POWER_STATE            0x2b
0534 #define SDVO_CMD_GET_ENCODER_POWER_STATE        0x2b
0535 #define SDVO_CMD_SET_ENCODER_POWER_STATE        0x2c
0536 # define SDVO_ENCODER_STATE_ON                  (1 << 0)
0537 # define SDVO_ENCODER_STATE_STANDBY             (1 << 1)
0538 # define SDVO_ENCODER_STATE_SUSPEND             (1 << 2)
0539 # define SDVO_ENCODER_STATE_OFF                 (1 << 3)
0540 # define SDVO_MONITOR_STATE_ON                  (1 << 4)
0541 # define SDVO_MONITOR_STATE_STANDBY             (1 << 5)
0542 # define SDVO_MONITOR_STATE_SUSPEND             (1 << 6)
0543 # define SDVO_MONITOR_STATE_OFF                 (1 << 7)
0544
0545 #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING     0x2d
0546 #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING     0x2e
0547 #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING     0x2f
0548 /*
0549  * The panel power sequencing parameters are in units of milliseconds.
0550  * The high fields are bits 8:9 of the 10-bit values.
0551  */
0552 struct sdvo_panel_power_sequencing {
0553     u8 t0;
0554     u8 t1;
0555     u8 t2;
0556     u8 t3;
0557     u8 t4;
0558
0559     unsigned int t0_high:2;
0560     unsigned int t1_high:2;
0561     unsigned int t2_high:2;
0562     unsigned int t3_high:2;
0563
0564     unsigned int t4_high:2;
0565     unsigned int pad:6;
0566 } __packed;
0567
0568 #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL        0x30
0569 struct sdvo_max_backlight_reply {
0570     u8 max_value;
0571     u8 default_value;
0572 } __packed;
0573
0574 #define SDVO_CMD_GET_BACKLIGHT_LEVEL            0x31
0575 #define SDVO_CMD_SET_BACKLIGHT_LEVEL            0x32
0576
0577 #define SDVO_CMD_GET_AMBIENT_LIGHT          0x33
0578 struct sdvo_get_ambient_light_reply {
0579     u16 trip_low;
0580     u16 trip_high;
0581     u16 value;
0582 } __packed;
0583 #define SDVO_CMD_SET_AMBIENT_LIGHT          0x34
0584 struct sdvo_set_ambient_light_reply {
0585     u16 trip_low;
0586     u16 trip_high;
0587     unsigned int enable:1;
0588     unsigned int pad:7;
0589 } __packed;
0590
0591 /* Set display power state */
0592 #define SDVO_CMD_SET_DISPLAY_POWER_STATE        0x7d
0593 # define SDVO_DISPLAY_STATE_ON              (1 << 0)
0594 # define SDVO_DISPLAY_STATE_STANDBY         (1 << 1)
0595 # define SDVO_DISPLAY_STATE_SUSPEND         (1 << 2)
0596 # define SDVO_DISPLAY_STATE_OFF             (1 << 3)
0597
0598 #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS     0x84
0599 struct intel_sdvo_enhancements_reply {
0600     unsigned int flicker_filter:1;
0601     unsigned int flicker_filter_adaptive:1;
0602     unsigned int flicker_filter_2d:1;
0603     unsigned int saturation:1;
0604     unsigned int hue:1;
0605     unsigned int brightness:1;
0606     unsigned int contrast:1;
0607     unsigned int overscan_h:1;
0608
0609     unsigned int overscan_v:1;
0610     unsigned int hpos:1;
0611     unsigned int vpos:1;
0612     unsigned int sharpness:1;
0613     unsigned int dot_crawl:1;
0614     unsigned int dither:1;
0615     unsigned int tv_chroma_filter:1;
0616     unsigned int tv_luma_filter:1;
0617 } __packed;
0618
0619 /* Picture enhancement limits below are dependent on the current TV format,
0620  * and thus need to be queried and set after it.
0621  */
0622 #define SDVO_CMD_GET_MAX_FLICKER_FILTER         0x4d
0623 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE    0x7b
0624 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D      0x52
0625 #define SDVO_CMD_GET_MAX_SATURATION         0x55
0626 #define SDVO_CMD_GET_MAX_HUE                0x58
0627 #define SDVO_CMD_GET_MAX_BRIGHTNESS         0x5b
0628 #define SDVO_CMD_GET_MAX_CONTRAST           0x5e
0629 #define SDVO_CMD_GET_MAX_OVERSCAN_H         0x61
0630 #define SDVO_CMD_GET_MAX_OVERSCAN_V         0x64
0631 #define SDVO_CMD_GET_MAX_HPOS               0x67
0632 #define SDVO_CMD_GET_MAX_VPOS               0x6a
0633 #define SDVO_CMD_GET_MAX_SHARPNESS          0x6d
0634 #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER       0x74
0635 #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER         0x77
0636 struct intel_sdvo_enhancement_limits_reply {
0637     u16 max_value;
0638     u16 default_value;
0639 } __packed;
0640
0641 #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION     0x7f
0642 #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION     0x80
0643 # define SDVO_LVDS_COLOR_DEPTH_18           (0 << 0)
0644 # define SDVO_LVDS_COLOR_DEPTH_24           (1 << 0)
0645 # define SDVO_LVDS_CONNECTOR_SPWG           (0 << 2)
0646 # define SDVO_LVDS_CONNECTOR_OPENLDI            (1 << 2)
0647 # define SDVO_LVDS_SINGLE_CHANNEL           (0 << 4)
0648 # define SDVO_LVDS_DUAL_CHANNEL             (1 << 4)
0649
0650 #define SDVO_CMD_GET_FLICKER_FILTER         0x4e
0651 #define SDVO_CMD_SET_FLICKER_FILTER         0x4f
0652 #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE        0x50
0653 #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE        0x51
0654 #define SDVO_CMD_GET_FLICKER_FILTER_2D          0x53
0655 #define SDVO_CMD_SET_FLICKER_FILTER_2D          0x54
0656 #define SDVO_CMD_GET_SATURATION             0x56
0657 #define SDVO_CMD_SET_SATURATION             0x57
0658 #define SDVO_CMD_GET_HUE                0x59
0659 #define SDVO_CMD_SET_HUE                0x5a
0660 #define SDVO_CMD_GET_BRIGHTNESS             0x5c
0661 #define SDVO_CMD_SET_BRIGHTNESS             0x5d
0662 #define SDVO_CMD_GET_CONTRAST               0x5f
0663 #define SDVO_CMD_SET_CONTRAST               0x60
0664 #define SDVO_CMD_GET_OVERSCAN_H             0x62
0665 #define SDVO_CMD_SET_OVERSCAN_H             0x63
0666 #define SDVO_CMD_GET_OVERSCAN_V             0x65
0667 #define SDVO_CMD_SET_OVERSCAN_V             0x66
0668 #define SDVO_CMD_GET_HPOS               0x68
0669 #define SDVO_CMD_SET_HPOS               0x69
0670 #define SDVO_CMD_GET_VPOS               0x6b
0671 #define SDVO_CMD_SET_VPOS               0x6c
0672 #define SDVO_CMD_GET_SHARPNESS              0x6e
0673 #define SDVO_CMD_SET_SHARPNESS              0x6f
0674 #define SDVO_CMD_GET_TV_CHROMA_FILTER           0x75
0675 #define SDVO_CMD_SET_TV_CHROMA_FILTER           0x76
0676 #define SDVO_CMD_GET_TV_LUMA_FILTER         0x78
0677 #define SDVO_CMD_SET_TV_LUMA_FILTER         0x79
0678 struct intel_sdvo_enhancements_arg {
0679     u16 value;
0680 } __packed;
0681
0682 #define SDVO_CMD_GET_DOT_CRAWL              0x70
0683 #define SDVO_CMD_SET_DOT_CRAWL              0x71
0684 # define SDVO_DOT_CRAWL_ON                  (1 << 0)
0685 # define SDVO_DOT_CRAWL_DEFAULT_ON              (1 << 1)
0686
0687 #define SDVO_CMD_GET_DITHER             0x72
0688 #define SDVO_CMD_SET_DITHER             0x73
0689 # define SDVO_DITHER_ON                     (1 << 0)
0690 # define SDVO_DITHER_DEFAULT_ON                 (1 << 1)
0691
0692 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH         0x7a
0693 # define SDVO_CONTROL_BUS_PROM              (1 << 0)
0694 # define SDVO_CONTROL_BUS_DDC1              (1 << 1)
0695 # define SDVO_CONTROL_BUS_DDC2              (1 << 2)
0696 # define SDVO_CONTROL_BUS_DDC3              (1 << 3)
0697
0698 /* HDMI op codes */
0699 #define SDVO_CMD_GET_SUPP_ENCODE    0x9d
0700 #define SDVO_CMD_GET_ENCODE     0x9e
0701 #define SDVO_CMD_SET_ENCODE     0x9f
0702   #define SDVO_ENCODE_DVI   0x0
0703   #define SDVO_ENCODE_HDMI  0x1
0704 #define SDVO_CMD_SET_PIXEL_REPLI    0x8b
0705 #define SDVO_CMD_GET_PIXEL_REPLI    0x8c
0706 #define SDVO_CMD_GET_COLORIMETRY_CAP    0x8d
0707 #define SDVO_CMD_SET_COLORIMETRY    0x8e
0708   #define SDVO_COLORIMETRY_RGB256   (1 << 0)
0709   #define SDVO_COLORIMETRY_RGB220   (1 << 1)
0710   #define SDVO_COLORIMETRY_YCrCb422 (1 << 2)
0711   #define SDVO_COLORIMETRY_YCrCb444 (1 << 3)
0712 #define SDVO_CMD_GET_COLORIMETRY    0x8f
0713 #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
0714 #define SDVO_CMD_SET_AUDIO_STAT     0x91
0715 #define SDVO_CMD_GET_AUDIO_STAT     0x92
0716   #define SDVO_AUDIO_ELD_VALID      (1 << 0)
0717   #define SDVO_AUDIO_PRESENCE_DETECT    (1 << 1)
0718   #define SDVO_AUDIO_CP_READY       (1 << 2)
0719 #define SDVO_CMD_SET_HBUF_INDEX     0x93
0720   #define SDVO_HBUF_INDEX_ELD       0
0721   #define SDVO_HBUF_INDEX_AVI_IF    1
0722 #define SDVO_CMD_GET_HBUF_INDEX     0x94
0723 #define SDVO_CMD_GET_HBUF_INFO      0x95
0724 #define SDVO_CMD_SET_HBUF_AV_SPLIT  0x96
0725 #define SDVO_CMD_GET_HBUF_AV_SPLIT  0x97
0726 #define SDVO_CMD_SET_HBUF_DATA      0x98
0727 #define SDVO_CMD_GET_HBUF_DATA      0x99
0728 #define SDVO_CMD_SET_HBUF_TXRATE    0x9a
0729 #define SDVO_CMD_GET_HBUF_TXRATE    0x9b
0730   #define SDVO_HBUF_TX_DISABLED (0 << 6)
0731   #define SDVO_HBUF_TX_ONCE (2 << 6)
0732   #define SDVO_HBUF_TX_VSYNC    (3 << 6)
0733 #define SDVO_CMD_GET_AUDIO_TX_INFO  0x9c
0734 #define SDVO_NEED_TO_STALL  (1 << 7)
0735
0736 struct intel_sdvo_encode {
0737     u8 dvi_rev;
0738     u8 hdmi_rev;
0739 } __packed;
0740
0741 #endif /* __INTEL_SDVO_REGS_H__ */