i915/display/intel_plane_initial.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2021 Intel Corporation
0004  */
0005
0006 #include "gem/i915_gem_region.h"
0007 #include "i915_drv.h"
0008 #include "intel_atomic_plane.h"
0009 #include "intel_display.h"
0010 #include "intel_display_types.h"
0011 #include "intel_fb.h"
0012 #include "intel_plane_initial.h"
0013
0014 static bool
0015 intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
0016                   const struct intel_initial_plane_config *plane_config,
0017                   struct drm_framebuffer **fb,
0018                   struct i915_vma **vma)
0019 {
0020     struct intel_crtc *crtc;
0021
0022     for_each_intel_crtc(&i915->drm, crtc) {
0023         struct intel_crtc_state *crtc_state =
0024             to_intel_crtc_state(crtc->base.state);
0025         struct intel_plane *plane =
0026             to_intel_plane(crtc->base.primary);
0027         struct intel_plane_state *plane_state =
0028             to_intel_plane_state(plane->base.state);
0029
0030         if (!crtc_state->uapi.active)
0031             continue;
0032
0033         if (!plane_state->ggtt_vma)
0034             continue;
0035
0036         if (intel_plane_ggtt_offset(plane_state) == plane_config->base) {
0037             *fb = plane_state->hw.fb;
0038             *vma = plane_state->ggtt_vma;
0039             return true;
0040         }
0041     }
0042
0043     return false;
0044 }
0045
0046 static struct i915_vma *
0047 initial_plane_vma(struct drm_i915_private *i915,
0048           struct intel_initial_plane_config *plane_config)
0049 {
0050     struct intel_memory_region *mem;
0051     struct drm_i915_gem_object *obj;
0052     struct i915_vma *vma;
0053     resource_size_t phys_base;
0054     u32 base, size;
0055     u64 pinctl;
0056
0057     if (plane_config->size == 0)
0058         return NULL;
0059
0060     base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
0061     if (IS_DGFX(i915)) {
0062         gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
0063         gen8_pte_t pte;
0064
0065         gte += base / I915_GTT_PAGE_SIZE;
0066
0067         pte = ioread64(gte);
0068         if (!(pte & GEN12_GGTT_PTE_LM)) {
0069             drm_err(&i915->drm,
0070                 "Initial plane programming missing PTE_LM bit\n");
0071             return NULL;
0072         }
0073
0074         phys_base = pte & I915_GTT_PAGE_MASK;
0075         mem = i915->mm.regions[INTEL_REGION_LMEM_0];
0076
0077         /*
0078          * We don't currently expect this to ever be placed in the
0079          * stolen portion.
0080          */
0081         if (phys_base >= resource_size(&mem->region)) {
0082             drm_err(&i915->drm,
0083                 "Initial plane programming using invalid range, phys_base=%pa\n",
0084                 &phys_base);
0085             return NULL;
0086         }
0087
0088         drm_dbg(&i915->drm,
0089             "Using phys_base=%pa, based on initial plane programming\n",
0090             &phys_base);
0091     } else {
0092         phys_base = base;
0093         mem = i915->mm.stolen_region;
0094     }
0095
0096     if (!mem)
0097         return NULL;
0098
0099     size = round_up(plane_config->base + plane_config->size,
0100             mem->min_page_size);
0101     size -= base;
0102
0103     /*
0104      * If the FB is too big, just don't use it since fbdev is not very
0105      * important and we should probably use that space with FBC or other
0106      * features.
0107      */
0108     if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
0109         mem == i915->mm.stolen_region &&
0110         size * 2 > i915->stolen_usable_size)
0111         return NULL;
0112
0113     obj = i915_gem_object_create_region_at(mem, phys_base, size, 0);
0114     if (IS_ERR(obj))
0115         return NULL;
0116
0117     /*
0118      * Mark it WT ahead of time to avoid changing the
0119      * cache_level during fbdev initialization. The
0120      * unbind there would get stuck waiting for rcu.
0121      */
0122     i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
0123                         I915_CACHE_WT : I915_CACHE_NONE);
0124
0125     switch (plane_config->tiling) {
0126     case I915_TILING_NONE:
0127         break;
0128     case I915_TILING_X:
0129     case I915_TILING_Y:
0130         obj->tiling_and_stride =
0131             plane_config->fb->base.pitches[0] |
0132             plane_config->tiling;
0133         break;
0134     default:
0135         MISSING_CASE(plane_config->tiling);
0136         goto err_obj;
0137     }
0138
0139     vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
0140     if (IS_ERR(vma))
0141         goto err_obj;
0142
0143     pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base;
0144     if (HAS_GMCH(i915))
0145         pinctl |= PIN_MAPPABLE;
0146     if (i915_vma_pin(vma, 0, 0, pinctl))
0147         goto err_obj;
0148
0149     if (i915_gem_object_is_tiled(obj) &&
0150         !i915_vma_is_map_and_fenceable(vma))
0151         goto err_obj;
0152
0153     return vma;
0154
0155 err_obj:
0156     i915_gem_object_put(obj);
0157     return NULL;
0158 }
0159
0160 static bool
0161 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
0162                   struct intel_initial_plane_config *plane_config)
0163 {
0164     struct drm_device *dev = crtc->base.dev;
0165     struct drm_i915_private *dev_priv = to_i915(dev);
0166     struct drm_mode_fb_cmd2 mode_cmd = { 0 };
0167     struct drm_framebuffer *fb = &plane_config->fb->base;
0168     struct i915_vma *vma;
0169
0170     switch (fb->modifier) {
0171     case DRM_FORMAT_MOD_LINEAR:
0172     case I915_FORMAT_MOD_X_TILED:
0173     case I915_FORMAT_MOD_Y_TILED:
0174     case I915_FORMAT_MOD_4_TILED:
0175         break;
0176     default:
0177         drm_dbg(&dev_priv->drm,
0178             "Unsupported modifier for initial FB: 0x%llx\n",
0179             fb->modifier);
0180         return false;
0181     }
0182
0183     vma = initial_plane_vma(dev_priv, plane_config);
0184     if (!vma)
0185         return false;
0186
0187     mode_cmd.pixel_format = fb->format->format;
0188     mode_cmd.width = fb->width;
0189     mode_cmd.height = fb->height;
0190     mode_cmd.pitches[0] = fb->pitches[0];
0191     mode_cmd.modifier[0] = fb->modifier;
0192     mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
0193
0194     if (intel_framebuffer_init(to_intel_framebuffer(fb),
0195                    vma->obj, &mode_cmd)) {
0196         drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
0197         goto err_vma;
0198     }
0199
0200     plane_config->vma = vma;
0201     return true;
0202
0203 err_vma:
0204     i915_vma_put(vma);
0205     return false;
0206 }
0207
0208 static void
0209 intel_find_initial_plane_obj(struct intel_crtc *crtc,
0210                  struct intel_initial_plane_config *plane_config)
0211 {
0212     struct drm_device *dev = crtc->base.dev;
0213     struct drm_i915_private *dev_priv = to_i915(dev);
0214     struct intel_plane *plane =
0215         to_intel_plane(crtc->base.primary);
0216     struct intel_plane_state *plane_state =
0217         to_intel_plane_state(plane->base.state);
0218     struct drm_framebuffer *fb;
0219     struct i915_vma *vma;
0220
0221     /*
0222      * TODO:
0223      *   Disable planes if get_initial_plane_config() failed.
0224      *   Make sure things work if the surface base is not page aligned.
0225      */
0226     if (!plane_config->fb)
0227         return;
0228
0229     if (intel_alloc_initial_plane_obj(crtc, plane_config)) {
0230         fb = &plane_config->fb->base;
0231         vma = plane_config->vma;
0232         goto valid_fb;
0233     }
0234
0235     /*
0236      * Failed to alloc the obj, check to see if we should share
0237      * an fb with another CRTC instead
0238      */
0239     if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma))
0240         goto valid_fb;
0241
0242     /*
0243      * We've failed to reconstruct the BIOS FB.  Current display state
0244      * indicates that the primary plane is visible, but has a NULL FB,
0245      * which will lead to problems later if we don't fix it up.  The
0246      * simplest solution is to just disable the primary plane now and
0247      * pretend the BIOS never had it enabled.
0248      */
0249     intel_plane_disable_noatomic(crtc, plane);
0250
0251     return;
0252
0253 valid_fb:
0254     plane_state->uapi.rotation = plane_config->rotation;
0255     intel_fb_fill_view(to_intel_framebuffer(fb),
0256                plane_state->uapi.rotation, &plane_state->view);
0257
0258     __i915_vma_pin(vma);
0259     plane_state->ggtt_vma = i915_vma_get(vma);
0260     if (intel_plane_uses_fence(plane_state) &&
0261         i915_vma_pin_fence(vma) == 0 && vma->fence)
0262         plane_state->flags |= PLANE_HAS_FENCE;
0263
0264     plane_state->uapi.src_x = 0;
0265     plane_state->uapi.src_y = 0;
0266     plane_state->uapi.src_w = fb->width << 16;
0267     plane_state->uapi.src_h = fb->height << 16;
0268
0269     plane_state->uapi.crtc_x = 0;
0270     plane_state->uapi.crtc_y = 0;
0271     plane_state->uapi.crtc_w = fb->width;
0272     plane_state->uapi.crtc_h = fb->height;
0273
0274     if (plane_config->tiling)
0275         dev_priv->preserve_bios_swizzle = true;
0276
0277     plane_state->uapi.fb = fb;
0278     drm_framebuffer_get(fb);
0279
0280     plane_state->uapi.crtc = &crtc->base;
0281     intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);
0282
0283     atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits);
0284 }
0285
0286 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
0287 {
0288     if (plane_config->fb) {
0289         struct drm_framebuffer *fb = &plane_config->fb->base;
0290
0291         /* We may only have the stub and not a full framebuffer */
0292         if (drm_framebuffer_read_refcount(fb))
0293             drm_framebuffer_put(fb);
0294         else
0295             kfree(fb);
0296     }
0297
0298     if (plane_config->vma)
0299         i915_vma_put(plane_config->vma);
0300 }
0301
0302 void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
0303 {
0304     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0305     struct intel_initial_plane_config plane_config = {};
0306
0307     /*
0308      * Note that reserving the BIOS fb up front prevents us
0309      * from stuffing other stolen allocations like the ring
0310      * on top.  This prevents some ugliness at boot time, and
0311      * can even allow for smooth boot transitions if the BIOS
0312      * fb is large enough for the active pipe configuration.
0313      */
0314     dev_priv->display->get_initial_plane_config(crtc, &plane_config);
0315
0316     /*
0317      * If the fb is shared between multiple heads, we'll
0318      * just get the first one.
0319      */
0320     intel_find_initial_plane_obj(crtc, &plane_config);
0321
0322     plane_config_fini(&plane_config);
0323 }