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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2021 Intel Corporation
0004  */
0005 
0006 #include "g4x_dp.h"
0007 #include "intel_crt.h"
0008 #include "intel_de.h"
0009 #include "intel_display_types.h"
0010 #include "intel_fdi.h"
0011 #include "intel_lvds.h"
0012 #include "intel_pch_display.h"
0013 #include "intel_pch_refclk.h"
0014 #include "intel_pps.h"
0015 #include "intel_sdvo.h"
0016 
0017 bool intel_has_pch_trancoder(struct drm_i915_private *i915,
0018                  enum pipe pch_transcoder)
0019 {
0020     return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) ||
0021         (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A);
0022 }
0023 
0024 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
0025 {
0026     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0027 
0028     if (HAS_PCH_LPT(i915))
0029         return PIPE_A;
0030     else
0031         return crtc->pipe;
0032 }
0033 
0034 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
0035                    enum pipe pipe, enum port port,
0036                    i915_reg_t dp_reg)
0037 {
0038     enum pipe port_pipe;
0039     bool state;
0040 
0041     state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
0042 
0043     I915_STATE_WARN(state && port_pipe == pipe,
0044             "PCH DP %c enabled on transcoder %c, should be disabled\n",
0045             port_name(port), pipe_name(pipe));
0046 
0047     I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
0048             "IBX PCH DP %c still using transcoder B\n",
0049             port_name(port));
0050 }
0051 
0052 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
0053                      enum pipe pipe, enum port port,
0054                      i915_reg_t hdmi_reg)
0055 {
0056     enum pipe port_pipe;
0057     bool state;
0058 
0059     state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
0060 
0061     I915_STATE_WARN(state && port_pipe == pipe,
0062             "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
0063             port_name(port), pipe_name(pipe));
0064 
0065     I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
0066             "IBX PCH HDMI %c still using transcoder B\n",
0067             port_name(port));
0068 }
0069 
0070 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
0071                       enum pipe pipe)
0072 {
0073     enum pipe port_pipe;
0074 
0075     assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
0076     assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
0077     assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
0078 
0079     I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
0080             port_pipe == pipe,
0081             "PCH VGA enabled on transcoder %c, should be disabled\n",
0082             pipe_name(pipe));
0083 
0084     I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
0085             port_pipe == pipe,
0086             "PCH LVDS enabled on transcoder %c, should be disabled\n",
0087             pipe_name(pipe));
0088 
0089     /* PCH SDVOB multiplex with HDMIB */
0090     assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
0091     assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
0092     assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
0093 }
0094 
0095 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
0096                        enum pipe pipe)
0097 {
0098     u32 val;
0099     bool enabled;
0100 
0101     val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
0102     enabled = !!(val & TRANS_ENABLE);
0103     I915_STATE_WARN(enabled,
0104             "transcoder assertion failed, should be off on pipe %c but is still active\n",
0105             pipe_name(pipe));
0106 }
0107 
0108 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
0109                        enum port port, i915_reg_t hdmi_reg)
0110 {
0111     u32 val = intel_de_read(dev_priv, hdmi_reg);
0112 
0113     if (val & SDVO_ENABLE ||
0114         (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
0115         return;
0116 
0117     drm_dbg_kms(&dev_priv->drm,
0118             "Sanitizing transcoder select for HDMI %c\n",
0119             port_name(port));
0120 
0121     val &= ~SDVO_PIPE_SEL_MASK;
0122     val |= SDVO_PIPE_SEL(PIPE_A);
0123 
0124     intel_de_write(dev_priv, hdmi_reg, val);
0125 }
0126 
0127 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
0128                      enum port port, i915_reg_t dp_reg)
0129 {
0130     u32 val = intel_de_read(dev_priv, dp_reg);
0131 
0132     if (val & DP_PORT_EN ||
0133         (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
0134         return;
0135 
0136     drm_dbg_kms(&dev_priv->drm,
0137             "Sanitizing transcoder select for DP %c\n",
0138             port_name(port));
0139 
0140     val &= ~DP_PIPE_SEL_MASK;
0141     val |= DP_PIPE_SEL(PIPE_A);
0142 
0143     intel_de_write(dev_priv, dp_reg, val);
0144 }
0145 
0146 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
0147 {
0148     /*
0149      * The BIOS may select transcoder B on some of the PCH
0150      * ports even it doesn't enable the port. This would trip
0151      * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
0152      * Sanitize the transcoder select bits to prevent that. We
0153      * assume that the BIOS never actually enabled the port,
0154      * because if it did we'd actually have to toggle the port
0155      * on and back off to make the transcoder A select stick
0156      * (see. intel_dp_link_down(), intel_disable_hdmi(),
0157      * intel_disable_sdvo()).
0158      */
0159     ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
0160     ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
0161     ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
0162 
0163     /* PCH SDVOB multiplex with HDMIB */
0164     ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
0165     ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
0166     ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
0167 }
0168 
0169 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
0170                        const struct intel_link_m_n *m_n)
0171 {
0172     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0173     enum pipe pipe = crtc->pipe;
0174 
0175     intel_set_m_n(dev_priv, m_n,
0176               PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
0177               PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
0178 }
0179 
0180 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
0181                        const struct intel_link_m_n *m_n)
0182 {
0183     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0184     enum pipe pipe = crtc->pipe;
0185 
0186     intel_set_m_n(dev_priv, m_n,
0187               PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
0188               PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
0189 }
0190 
0191 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
0192                     struct intel_link_m_n *m_n)
0193 {
0194     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0195     enum pipe pipe = crtc->pipe;
0196 
0197     intel_get_m_n(dev_priv, m_n,
0198               PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
0199               PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
0200 }
0201 
0202 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
0203                     struct intel_link_m_n *m_n)
0204 {
0205     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0206     enum pipe pipe = crtc->pipe;
0207 
0208     intel_get_m_n(dev_priv, m_n,
0209               PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
0210               PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
0211 }
0212 
0213 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
0214                        enum pipe pch_transcoder)
0215 {
0216     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0217     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0218     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0219 
0220     intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
0221                intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
0222     intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
0223                intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
0224     intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
0225                intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
0226 
0227     intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
0228                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
0229     intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
0230                intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
0231     intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
0232                intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
0233     intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
0234                intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
0235 }
0236 
0237 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
0238 {
0239     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0240     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0241     enum pipe pipe = crtc->pipe;
0242     i915_reg_t reg;
0243     u32 val, pipeconf_val;
0244 
0245     /* Make sure PCH DPLL is enabled */
0246     assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
0247 
0248     /* FDI must be feeding us bits for PCH ports */
0249     assert_fdi_tx_enabled(dev_priv, pipe);
0250     assert_fdi_rx_enabled(dev_priv, pipe);
0251 
0252     if (HAS_PCH_CPT(dev_priv)) {
0253         reg = TRANS_CHICKEN2(pipe);
0254         val = intel_de_read(dev_priv, reg);
0255         /*
0256          * Workaround: Set the timing override bit
0257          * before enabling the pch transcoder.
0258          */
0259         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
0260         /* Configure frame start delay to match the CPU */
0261         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
0262         val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
0263         intel_de_write(dev_priv, reg, val);
0264     }
0265 
0266     reg = PCH_TRANSCONF(pipe);
0267     val = intel_de_read(dev_priv, reg);
0268     pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
0269 
0270     if (HAS_PCH_IBX(dev_priv)) {
0271         /* Configure frame start delay to match the CPU */
0272         val &= ~TRANS_FRAME_START_DELAY_MASK;
0273         val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
0274 
0275         /*
0276          * Make the BPC in transcoder be consistent with
0277          * that in pipeconf reg. For HDMI we must use 8bpc
0278          * here for both 8bpc and 12bpc.
0279          */
0280         val &= ~PIPECONF_BPC_MASK;
0281         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
0282             val |= PIPECONF_BPC_8;
0283         else
0284             val |= pipeconf_val & PIPECONF_BPC_MASK;
0285     }
0286 
0287     val &= ~TRANS_INTERLACE_MASK;
0288     if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
0289         if (HAS_PCH_IBX(dev_priv) &&
0290             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
0291             val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
0292         else
0293             val |= TRANS_INTERLACE_INTERLACED;
0294     } else {
0295         val |= TRANS_INTERLACE_PROGRESSIVE;
0296     }
0297 
0298     intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
0299     if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
0300         drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
0301             pipe_name(pipe));
0302 }
0303 
0304 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
0305 {
0306     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0307     enum pipe pipe = crtc->pipe;
0308     i915_reg_t reg;
0309     u32 val;
0310 
0311     /* FDI relies on the transcoder */
0312     assert_fdi_tx_disabled(dev_priv, pipe);
0313     assert_fdi_rx_disabled(dev_priv, pipe);
0314 
0315     /* Ports must be off as well */
0316     assert_pch_ports_disabled(dev_priv, pipe);
0317 
0318     reg = PCH_TRANSCONF(pipe);
0319     val = intel_de_read(dev_priv, reg);
0320     val &= ~TRANS_ENABLE;
0321     intel_de_write(dev_priv, reg, val);
0322     /* wait for PCH transcoder off, transcoder state */
0323     if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
0324         drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
0325             pipe_name(pipe));
0326 
0327     if (HAS_PCH_CPT(dev_priv)) {
0328         /* Workaround: Clear the timing override chicken bit again. */
0329         reg = TRANS_CHICKEN2(pipe);
0330         val = intel_de_read(dev_priv, reg);
0331         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
0332         intel_de_write(dev_priv, reg, val);
0333     }
0334 }
0335 
0336 void ilk_pch_pre_enable(struct intel_atomic_state *state,
0337             struct intel_crtc *crtc)
0338 {
0339     const struct intel_crtc_state *crtc_state =
0340         intel_atomic_get_new_crtc_state(state, crtc);
0341 
0342     /*
0343      * Note: FDI PLL enabling _must_ be done before we enable the
0344      * cpu pipes, hence this is separate from all the other fdi/pch
0345      * enabling.
0346      */
0347     ilk_fdi_pll_enable(crtc_state);
0348 }
0349 
0350 /*
0351  * Enable PCH resources required for PCH ports:
0352  *   - PCH PLLs
0353  *   - FDI training & RX/TX
0354  *   - update transcoder timings
0355  *   - DP transcoding bits
0356  *   - transcoder
0357  */
0358 void ilk_pch_enable(struct intel_atomic_state *state,
0359             struct intel_crtc *crtc)
0360 {
0361     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0362     const struct intel_crtc_state *crtc_state =
0363         intel_atomic_get_new_crtc_state(state, crtc);
0364     enum pipe pipe = crtc->pipe;
0365     u32 temp;
0366 
0367     assert_pch_transcoder_disabled(dev_priv, pipe);
0368 
0369     /* For PCH output, training FDI link */
0370     intel_fdi_link_train(crtc, crtc_state);
0371 
0372     /*
0373      * We need to program the right clock selection
0374      * before writing the pixel multiplier into the DPLL.
0375      */
0376     if (HAS_PCH_CPT(dev_priv)) {
0377         u32 sel;
0378 
0379         temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
0380         temp |= TRANS_DPLL_ENABLE(pipe);
0381         sel = TRANS_DPLLB_SEL(pipe);
0382         if (crtc_state->shared_dpll ==
0383             intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
0384             temp |= sel;
0385         else
0386             temp &= ~sel;
0387         intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
0388     }
0389 
0390     /*
0391      * XXX: pch pll's can be enabled any time before we enable the PCH
0392      * transcoder, and we actually should do this to not upset any PCH
0393      * transcoder that already use the clock when we share it.
0394      *
0395      * Note that enable_shared_dpll tries to do the right thing, but
0396      * get_shared_dpll unconditionally resets the pll - we need that
0397      * to have the right LVDS enable sequence.
0398      */
0399     intel_enable_shared_dpll(crtc_state);
0400 
0401     /* set transcoder timing, panel must allow it */
0402     assert_pps_unlocked(dev_priv, pipe);
0403     if (intel_crtc_has_dp_encoder(crtc_state)) {
0404         intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
0405         intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
0406     }
0407     ilk_pch_transcoder_set_timings(crtc_state, pipe);
0408 
0409     intel_fdi_normal_train(crtc);
0410 
0411     /* For PCH DP, enable TRANS_DP_CTL */
0412     if (HAS_PCH_CPT(dev_priv) &&
0413         intel_crtc_has_dp_encoder(crtc_state)) {
0414         const struct drm_display_mode *adjusted_mode =
0415             &crtc_state->hw.adjusted_mode;
0416         u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
0417         i915_reg_t reg = TRANS_DP_CTL(pipe);
0418         enum port port;
0419 
0420         temp = intel_de_read(dev_priv, reg);
0421         temp &= ~(TRANS_DP_PORT_SEL_MASK |
0422               TRANS_DP_VSYNC_ACTIVE_HIGH |
0423               TRANS_DP_HSYNC_ACTIVE_HIGH |
0424               TRANS_DP_BPC_MASK);
0425         temp |= TRANS_DP_OUTPUT_ENABLE;
0426         temp |= bpc << 9; /* same format but at 11:9 */
0427 
0428         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
0429             temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
0430         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
0431             temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
0432 
0433         port = intel_get_crtc_new_encoder(state, crtc_state)->port;
0434         drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
0435         temp |= TRANS_DP_PORT_SEL(port);
0436 
0437         intel_de_write(dev_priv, reg, temp);
0438     }
0439 
0440     ilk_enable_pch_transcoder(crtc_state);
0441 }
0442 
0443 void ilk_pch_disable(struct intel_atomic_state *state,
0444              struct intel_crtc *crtc)
0445 {
0446     ilk_fdi_disable(crtc);
0447 }
0448 
0449 void ilk_pch_post_disable(struct intel_atomic_state *state,
0450               struct intel_crtc *crtc)
0451 {
0452     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0453     enum pipe pipe = crtc->pipe;
0454 
0455     ilk_disable_pch_transcoder(crtc);
0456 
0457     if (HAS_PCH_CPT(dev_priv)) {
0458         i915_reg_t reg;
0459         u32 temp;
0460 
0461         /* disable TRANS_DP_CTL */
0462         reg = TRANS_DP_CTL(pipe);
0463         temp = intel_de_read(dev_priv, reg);
0464         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
0465               TRANS_DP_PORT_SEL_MASK);
0466         temp |= TRANS_DP_PORT_SEL_NONE;
0467         intel_de_write(dev_priv, reg, temp);
0468 
0469         /* disable DPLL_SEL */
0470         temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
0471         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
0472         intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
0473     }
0474 
0475     ilk_fdi_pll_disable(crtc);
0476 }
0477 
0478 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
0479 {
0480     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0481     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0482 
0483     /* read out port_clock from the DPLL */
0484     i9xx_crtc_clock_get(crtc, crtc_state);
0485 
0486     /*
0487      * In case there is an active pipe without active ports,
0488      * we may need some idea for the dotclock anyway.
0489      * Calculate one based on the FDI configuration.
0490      */
0491     crtc_state->hw.adjusted_mode.crtc_clock =
0492         intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
0493                      &crtc_state->fdi_m_n);
0494 }
0495 
0496 void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
0497 {
0498     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0499     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0500     struct intel_shared_dpll *pll;
0501     enum pipe pipe = crtc->pipe;
0502     enum intel_dpll_id pll_id;
0503     bool pll_active;
0504     u32 tmp;
0505 
0506     if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
0507         return;
0508 
0509     crtc_state->has_pch_encoder = true;
0510 
0511     tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
0512     crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
0513                  FDI_DP_PORT_WIDTH_SHIFT) + 1;
0514 
0515     intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
0516                        &crtc_state->fdi_m_n);
0517 
0518     if (HAS_PCH_IBX(dev_priv)) {
0519         /*
0520          * The pipe->pch transcoder and pch transcoder->pll
0521          * mapping is fixed.
0522          */
0523         pll_id = (enum intel_dpll_id) pipe;
0524     } else {
0525         tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
0526         if (tmp & TRANS_DPLLB_SEL(pipe))
0527             pll_id = DPLL_ID_PCH_PLL_B;
0528         else
0529             pll_id = DPLL_ID_PCH_PLL_A;
0530     }
0531 
0532     crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
0533     pll = crtc_state->shared_dpll;
0534 
0535     pll_active = intel_dpll_get_hw_state(dev_priv, pll,
0536                          &crtc_state->dpll_hw_state);
0537     drm_WARN_ON(&dev_priv->drm, !pll_active);
0538 
0539     tmp = crtc_state->dpll_hw_state.dpll;
0540     crtc_state->pixel_multiplier =
0541         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
0542          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
0543 
0544     ilk_pch_clock_get(crtc_state);
0545 }
0546 
0547 static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
0548 {
0549     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0550     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0551     enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0552     u32 val, pipeconf_val;
0553 
0554     /* FDI must be feeding us bits for PCH ports */
0555     assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
0556     assert_fdi_rx_enabled(dev_priv, PIPE_A);
0557 
0558     val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
0559     /* Workaround: set timing override bit. */
0560     val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
0561     /* Configure frame start delay to match the CPU */
0562     val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
0563     val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
0564     intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
0565 
0566     val = TRANS_ENABLE;
0567     pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
0568 
0569     if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
0570         val |= TRANS_INTERLACE_INTERLACED;
0571     else
0572         val |= TRANS_INTERLACE_PROGRESSIVE;
0573 
0574     intel_de_write(dev_priv, LPT_TRANSCONF, val);
0575     if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
0576                   TRANS_STATE_ENABLE, 100))
0577         drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
0578 }
0579 
0580 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
0581 {
0582     u32 val;
0583 
0584     val = intel_de_read(dev_priv, LPT_TRANSCONF);
0585     val &= ~TRANS_ENABLE;
0586     intel_de_write(dev_priv, LPT_TRANSCONF, val);
0587     /* wait for PCH transcoder off, transcoder state */
0588     if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
0589                     TRANS_STATE_ENABLE, 50))
0590         drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
0591 
0592     /* Workaround: clear timing override bit. */
0593     val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
0594     val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
0595     intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
0596 }
0597 
0598 void lpt_pch_enable(struct intel_atomic_state *state,
0599             struct intel_crtc *crtc)
0600 {
0601     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0602     const struct intel_crtc_state *crtc_state =
0603         intel_atomic_get_new_crtc_state(state, crtc);
0604 
0605     assert_pch_transcoder_disabled(dev_priv, PIPE_A);
0606 
0607     lpt_program_iclkip(crtc_state);
0608 
0609     /* Set transcoder timing. */
0610     ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
0611 
0612     lpt_enable_pch_transcoder(crtc_state);
0613 }
0614 
0615 void lpt_pch_disable(struct intel_atomic_state *state,
0616              struct intel_crtc *crtc)
0617 {
0618     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0619 
0620     lpt_disable_pch_transcoder(dev_priv);
0621 
0622     lpt_disable_iclkip(dev_priv);
0623 }
0624 
0625 void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
0626 {
0627     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0628     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0629     u32 tmp;
0630 
0631     if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
0632         return;
0633 
0634     crtc_state->has_pch_encoder = true;
0635 
0636     tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
0637     crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
0638                  FDI_DP_PORT_WIDTH_SHIFT) + 1;
0639 
0640     intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
0641                        &crtc_state->fdi_m_n);
0642 
0643     crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
0644 }
0645 
0646 void intel_pch_sanitize(struct drm_i915_private *i915)
0647 {
0648     if (HAS_PCH_IBX(i915))
0649         ibx_sanitize_pch_ports(i915);
0650 }
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