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0001 /*
0002  * Copyright © 2009
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0020  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0021  * SOFTWARE.
0022  *
0023  * Authors:
0024  *    Daniel Vetter <daniel@ffwll.ch>
0025  *
0026  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
0027  */
0028 
0029 #include <drm/drm_fourcc.h>
0030 
0031 #include "gem/i915_gem_internal.h"
0032 #include "gem/i915_gem_pm.h"
0033 #include "gt/intel_gpu_commands.h"
0034 #include "gt/intel_ring.h"
0035 
0036 #include "i915_drv.h"
0037 #include "i915_reg.h"
0038 #include "intel_de.h"
0039 #include "intel_display_types.h"
0040 #include "intel_frontbuffer.h"
0041 #include "intel_overlay.h"
0042 #include "intel_pci_config.h"
0043 
0044 /* Limits for overlay size. According to intel doc, the real limits are:
0045  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
0046  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
0047  * the mininum of both.  */
0048 #define IMAGE_MAX_WIDTH     2048
0049 #define IMAGE_MAX_HEIGHT    2046 /* 2 * 1023 */
0050 /* on 830 and 845 these large limits result in the card hanging */
0051 #define IMAGE_MAX_WIDTH_LEGACY  1024
0052 #define IMAGE_MAX_HEIGHT_LEGACY 1088
0053 
0054 /* overlay register definitions */
0055 /* OCMD register */
0056 #define OCMD_TILED_SURFACE  (0x1<<19)
0057 #define OCMD_MIRROR_MASK    (0x3<<17)
0058 #define OCMD_MIRROR_MODE    (0x3<<17)
0059 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
0060 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
0061 #define OCMD_MIRROR_BOTH    (0x3<<17)
0062 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
0063 #define OCMD_UV_SWAP        (0x1<<14) /* YVYU */
0064 #define OCMD_Y_SWAP     (0x2<<14) /* UYVY or FOURCC UYVY */
0065 #define OCMD_Y_AND_UV_SWAP  (0x3<<14) /* VYUY */
0066 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
0067 #define OCMD_RGB_888        (0x1<<10) /* not in i965 Intel docs */
0068 #define OCMD_RGB_555        (0x2<<10) /* not in i965 Intel docs */
0069 #define OCMD_RGB_565        (0x3<<10) /* not in i965 Intel docs */
0070 #define OCMD_YUV_422_PACKED (0x8<<10)
0071 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
0072 #define OCMD_YUV_420_PLANAR (0xc<<10)
0073 #define OCMD_YUV_422_PLANAR (0xd<<10)
0074 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
0075 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
0076 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
0077 #define OCMD_BUF_TYPE_MASK  (0x1<<5)
0078 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
0079 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
0080 #define OCMD_TEST_MODE      (0x1<<4)
0081 #define OCMD_BUFFER_SELECT  (0x3<<2)
0082 #define OCMD_BUFFER0        (0x0<<2)
0083 #define OCMD_BUFFER1        (0x1<<2)
0084 #define OCMD_FIELD_SELECT   (0x1<<2)
0085 #define OCMD_FIELD0     (0x0<<1)
0086 #define OCMD_FIELD1     (0x1<<1)
0087 #define OCMD_ENABLE     (0x1<<0)
0088 
0089 /* OCONFIG register */
0090 #define OCONF_PIPE_MASK     (0x1<<18)
0091 #define OCONF_PIPE_A        (0x0<<18)
0092 #define OCONF_PIPE_B        (0x1<<18)
0093 #define OCONF_GAMMA2_ENABLE (0x1<<16)
0094 #define OCONF_CSC_MODE_BT601    (0x0<<5)
0095 #define OCONF_CSC_MODE_BT709    (0x1<<5)
0096 #define OCONF_CSC_BYPASS    (0x1<<4)
0097 #define OCONF_CC_OUT_8BIT   (0x1<<3)
0098 #define OCONF_TEST_MODE     (0x1<<2)
0099 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
0100 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
0101 
0102 /* DCLRKM (dst-key) register */
0103 #define DST_KEY_ENABLE      (0x1<<31)
0104 #define CLK_RGB24_MASK      0x0
0105 #define CLK_RGB16_MASK      0x070307
0106 #define CLK_RGB15_MASK      0x070707
0107 
0108 #define RGB30_TO_COLORKEY(c) \
0109     ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2))
0110 #define RGB16_TO_COLORKEY(c) \
0111     ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3))
0112 #define RGB15_TO_COLORKEY(c) \
0113     ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3))
0114 #define RGB8I_TO_COLORKEY(c) \
0115     ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0))
0116 
0117 /* overlay flip addr flag */
0118 #define OFC_UPDATE      0x1
0119 
0120 /* polyphase filter coefficients */
0121 #define N_HORIZ_Y_TAPS          5
0122 #define N_VERT_Y_TAPS           3
0123 #define N_HORIZ_UV_TAPS         3
0124 #define N_VERT_UV_TAPS          3
0125 #define N_PHASES                17
0126 #define MAX_TAPS                5
0127 
0128 /* memory bufferd overlay registers */
0129 struct overlay_registers {
0130     u32 OBUF_0Y;
0131     u32 OBUF_1Y;
0132     u32 OBUF_0U;
0133     u32 OBUF_0V;
0134     u32 OBUF_1U;
0135     u32 OBUF_1V;
0136     u32 OSTRIDE;
0137     u32 YRGB_VPH;
0138     u32 UV_VPH;
0139     u32 HORZ_PH;
0140     u32 INIT_PHS;
0141     u32 DWINPOS;
0142     u32 DWINSZ;
0143     u32 SWIDTH;
0144     u32 SWIDTHSW;
0145     u32 SHEIGHT;
0146     u32 YRGBSCALE;
0147     u32 UVSCALE;
0148     u32 OCLRC0;
0149     u32 OCLRC1;
0150     u32 DCLRKV;
0151     u32 DCLRKM;
0152     u32 SCLRKVH;
0153     u32 SCLRKVL;
0154     u32 SCLRKEN;
0155     u32 OCONFIG;
0156     u32 OCMD;
0157     u32 RESERVED1; /* 0x6C */
0158     u32 OSTART_0Y;
0159     u32 OSTART_1Y;
0160     u32 OSTART_0U;
0161     u32 OSTART_0V;
0162     u32 OSTART_1U;
0163     u32 OSTART_1V;
0164     u32 OTILEOFF_0Y;
0165     u32 OTILEOFF_1Y;
0166     u32 OTILEOFF_0U;
0167     u32 OTILEOFF_0V;
0168     u32 OTILEOFF_1U;
0169     u32 OTILEOFF_1V;
0170     u32 FASTHSCALE; /* 0xA0 */
0171     u32 UVSCALEV; /* 0xA4 */
0172     u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
0173     u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
0174     u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
0175     u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
0176     u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
0177     u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
0178     u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
0179     u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
0180     u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
0181 };
0182 
0183 struct intel_overlay {
0184     struct drm_i915_private *i915;
0185     struct intel_context *context;
0186     struct intel_crtc *crtc;
0187     struct i915_vma *vma;
0188     struct i915_vma *old_vma;
0189     struct intel_frontbuffer *frontbuffer;
0190     bool active;
0191     bool pfit_active;
0192     u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
0193     u32 color_key:24;
0194     u32 color_key_enabled:1;
0195     u32 brightness, contrast, saturation;
0196     u32 old_xscale, old_yscale;
0197     /* register access */
0198     struct drm_i915_gem_object *reg_bo;
0199     struct overlay_registers __iomem *regs;
0200     u32 flip_addr;
0201     /* flip handling */
0202     struct i915_active last_flip;
0203     void (*flip_complete)(struct intel_overlay *ovl);
0204 };
0205 
0206 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
0207                       bool enable)
0208 {
0209     struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
0210     u8 val;
0211 
0212     /* WA_OVERLAY_CLKGATE:alm */
0213     if (enable)
0214         intel_de_write(dev_priv, DSPCLK_GATE_D, 0);
0215     else
0216         intel_de_write(dev_priv, DSPCLK_GATE_D,
0217                    OVRUNIT_CLOCK_GATE_DISABLE);
0218 
0219     /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
0220     pci_bus_read_config_byte(pdev->bus,
0221                  PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
0222     if (enable)
0223         val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
0224     else
0225         val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
0226     pci_bus_write_config_byte(pdev->bus,
0227                   PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
0228 }
0229 
0230 static struct i915_request *
0231 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *))
0232 {
0233     struct i915_request *rq;
0234     int err;
0235 
0236     overlay->flip_complete = fn;
0237 
0238     rq = i915_request_create(overlay->context);
0239     if (IS_ERR(rq))
0240         return rq;
0241 
0242     err = i915_active_add_request(&overlay->last_flip, rq);
0243     if (err) {
0244         i915_request_add(rq);
0245         return ERR_PTR(err);
0246     }
0247 
0248     return rq;
0249 }
0250 
0251 /* overlay needs to be disable in OCMD reg */
0252 static int intel_overlay_on(struct intel_overlay *overlay)
0253 {
0254     struct drm_i915_private *dev_priv = overlay->i915;
0255     struct i915_request *rq;
0256     u32 *cs;
0257 
0258     drm_WARN_ON(&dev_priv->drm, overlay->active);
0259 
0260     rq = alloc_request(overlay, NULL);
0261     if (IS_ERR(rq))
0262         return PTR_ERR(rq);
0263 
0264     cs = intel_ring_begin(rq, 4);
0265     if (IS_ERR(cs)) {
0266         i915_request_add(rq);
0267         return PTR_ERR(cs);
0268     }
0269 
0270     overlay->active = true;
0271 
0272     if (IS_I830(dev_priv))
0273         i830_overlay_clock_gating(dev_priv, false);
0274 
0275     *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
0276     *cs++ = overlay->flip_addr | OFC_UPDATE;
0277     *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
0278     *cs++ = MI_NOOP;
0279     intel_ring_advance(rq, cs);
0280 
0281     i915_request_add(rq);
0282 
0283     return i915_active_wait(&overlay->last_flip);
0284 }
0285 
0286 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
0287                        struct i915_vma *vma)
0288 {
0289     enum pipe pipe = overlay->crtc->pipe;
0290     struct intel_frontbuffer *frontbuffer = NULL;
0291 
0292     drm_WARN_ON(&overlay->i915->drm, overlay->old_vma);
0293 
0294     if (vma)
0295         frontbuffer = intel_frontbuffer_get(vma->obj);
0296 
0297     intel_frontbuffer_track(overlay->frontbuffer, frontbuffer,
0298                 INTEL_FRONTBUFFER_OVERLAY(pipe));
0299 
0300     if (overlay->frontbuffer)
0301         intel_frontbuffer_put(overlay->frontbuffer);
0302     overlay->frontbuffer = frontbuffer;
0303 
0304     intel_frontbuffer_flip_prepare(overlay->i915,
0305                        INTEL_FRONTBUFFER_OVERLAY(pipe));
0306 
0307     overlay->old_vma = overlay->vma;
0308     if (vma)
0309         overlay->vma = i915_vma_get(vma);
0310     else
0311         overlay->vma = NULL;
0312 }
0313 
0314 /* overlay needs to be enabled in OCMD reg */
0315 static int intel_overlay_continue(struct intel_overlay *overlay,
0316                   struct i915_vma *vma,
0317                   bool load_polyphase_filter)
0318 {
0319     struct drm_i915_private *dev_priv = overlay->i915;
0320     struct i915_request *rq;
0321     u32 flip_addr = overlay->flip_addr;
0322     u32 tmp, *cs;
0323 
0324     drm_WARN_ON(&dev_priv->drm, !overlay->active);
0325 
0326     if (load_polyphase_filter)
0327         flip_addr |= OFC_UPDATE;
0328 
0329     /* check for underruns */
0330     tmp = intel_de_read(dev_priv, DOVSTA);
0331     if (tmp & (1 << 17))
0332         drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp);
0333 
0334     rq = alloc_request(overlay, NULL);
0335     if (IS_ERR(rq))
0336         return PTR_ERR(rq);
0337 
0338     cs = intel_ring_begin(rq, 2);
0339     if (IS_ERR(cs)) {
0340         i915_request_add(rq);
0341         return PTR_ERR(cs);
0342     }
0343 
0344     *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
0345     *cs++ = flip_addr;
0346     intel_ring_advance(rq, cs);
0347 
0348     intel_overlay_flip_prepare(overlay, vma);
0349     i915_request_add(rq);
0350 
0351     return 0;
0352 }
0353 
0354 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
0355 {
0356     struct i915_vma *vma;
0357 
0358     vma = fetch_and_zero(&overlay->old_vma);
0359     if (drm_WARN_ON(&overlay->i915->drm, !vma))
0360         return;
0361 
0362     intel_frontbuffer_flip_complete(overlay->i915,
0363                     INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
0364 
0365     i915_vma_unpin(vma);
0366     i915_vma_put(vma);
0367 }
0368 
0369 static void
0370 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
0371 {
0372     intel_overlay_release_old_vma(overlay);
0373 }
0374 
0375 static void intel_overlay_off_tail(struct intel_overlay *overlay)
0376 {
0377     struct drm_i915_private *dev_priv = overlay->i915;
0378 
0379     intel_overlay_release_old_vma(overlay);
0380 
0381     overlay->crtc->overlay = NULL;
0382     overlay->crtc = NULL;
0383     overlay->active = false;
0384 
0385     if (IS_I830(dev_priv))
0386         i830_overlay_clock_gating(dev_priv, true);
0387 }
0388 
0389 static void intel_overlay_last_flip_retire(struct i915_active *active)
0390 {
0391     struct intel_overlay *overlay =
0392         container_of(active, typeof(*overlay), last_flip);
0393 
0394     if (overlay->flip_complete)
0395         overlay->flip_complete(overlay);
0396 }
0397 
0398 /* overlay needs to be disabled in OCMD reg */
0399 static int intel_overlay_off(struct intel_overlay *overlay)
0400 {
0401     struct i915_request *rq;
0402     u32 *cs, flip_addr = overlay->flip_addr;
0403 
0404     drm_WARN_ON(&overlay->i915->drm, !overlay->active);
0405 
0406     /* According to intel docs the overlay hw may hang (when switching
0407      * off) without loading the filter coeffs. It is however unclear whether
0408      * this applies to the disabling of the overlay or to the switching off
0409      * of the hw. Do it in both cases */
0410     flip_addr |= OFC_UPDATE;
0411 
0412     rq = alloc_request(overlay, intel_overlay_off_tail);
0413     if (IS_ERR(rq))
0414         return PTR_ERR(rq);
0415 
0416     cs = intel_ring_begin(rq, 6);
0417     if (IS_ERR(cs)) {
0418         i915_request_add(rq);
0419         return PTR_ERR(cs);
0420     }
0421 
0422     /* wait for overlay to go idle */
0423     *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
0424     *cs++ = flip_addr;
0425     *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
0426 
0427     /* turn overlay off */
0428     *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
0429     *cs++ = flip_addr;
0430     *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
0431 
0432     intel_ring_advance(rq, cs);
0433 
0434     intel_overlay_flip_prepare(overlay, NULL);
0435     i915_request_add(rq);
0436 
0437     return i915_active_wait(&overlay->last_flip);
0438 }
0439 
0440 /* recover from an interruption due to a signal
0441  * We have to be careful not to repeat work forever an make forward progess. */
0442 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
0443 {
0444     return i915_active_wait(&overlay->last_flip);
0445 }
0446 
0447 /* Wait for pending overlay flip and release old frame.
0448  * Needs to be called before the overlay register are changed
0449  * via intel_overlay_(un)map_regs
0450  */
0451 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
0452 {
0453     struct drm_i915_private *dev_priv = overlay->i915;
0454     struct i915_request *rq;
0455     u32 *cs;
0456 
0457     /*
0458      * Only wait if there is actually an old frame to release to
0459      * guarantee forward progress.
0460      */
0461     if (!overlay->old_vma)
0462         return 0;
0463 
0464     if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
0465         intel_overlay_release_old_vid_tail(overlay);
0466         return 0;
0467     }
0468 
0469     rq = alloc_request(overlay, intel_overlay_release_old_vid_tail);
0470     if (IS_ERR(rq))
0471         return PTR_ERR(rq);
0472 
0473     cs = intel_ring_begin(rq, 2);
0474     if (IS_ERR(cs)) {
0475         i915_request_add(rq);
0476         return PTR_ERR(cs);
0477     }
0478 
0479     *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
0480     *cs++ = MI_NOOP;
0481     intel_ring_advance(rq, cs);
0482 
0483     i915_request_add(rq);
0484 
0485     return i915_active_wait(&overlay->last_flip);
0486 }
0487 
0488 void intel_overlay_reset(struct drm_i915_private *dev_priv)
0489 {
0490     struct intel_overlay *overlay = dev_priv->overlay;
0491 
0492     if (!overlay)
0493         return;
0494 
0495     overlay->old_xscale = 0;
0496     overlay->old_yscale = 0;
0497     overlay->crtc = NULL;
0498     overlay->active = false;
0499 }
0500 
0501 static int packed_depth_bytes(u32 format)
0502 {
0503     switch (format & I915_OVERLAY_DEPTH_MASK) {
0504     case I915_OVERLAY_YUV422:
0505         return 4;
0506     case I915_OVERLAY_YUV411:
0507         /* return 6; not implemented */
0508     default:
0509         return -EINVAL;
0510     }
0511 }
0512 
0513 static int packed_width_bytes(u32 format, short width)
0514 {
0515     switch (format & I915_OVERLAY_DEPTH_MASK) {
0516     case I915_OVERLAY_YUV422:
0517         return width << 1;
0518     default:
0519         return -EINVAL;
0520     }
0521 }
0522 
0523 static int uv_hsubsampling(u32 format)
0524 {
0525     switch (format & I915_OVERLAY_DEPTH_MASK) {
0526     case I915_OVERLAY_YUV422:
0527     case I915_OVERLAY_YUV420:
0528         return 2;
0529     case I915_OVERLAY_YUV411:
0530     case I915_OVERLAY_YUV410:
0531         return 4;
0532     default:
0533         return -EINVAL;
0534     }
0535 }
0536 
0537 static int uv_vsubsampling(u32 format)
0538 {
0539     switch (format & I915_OVERLAY_DEPTH_MASK) {
0540     case I915_OVERLAY_YUV420:
0541     case I915_OVERLAY_YUV410:
0542         return 2;
0543     case I915_OVERLAY_YUV422:
0544     case I915_OVERLAY_YUV411:
0545         return 1;
0546     default:
0547         return -EINVAL;
0548     }
0549 }
0550 
0551 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
0552 {
0553     u32 sw;
0554 
0555     if (DISPLAY_VER(dev_priv) == 2)
0556         sw = ALIGN((offset & 31) + width, 32);
0557     else
0558         sw = ALIGN((offset & 63) + width, 64);
0559 
0560     if (sw == 0)
0561         return 0;
0562 
0563     return (sw - 32) >> 3;
0564 }
0565 
0566 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
0567     [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
0568     [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
0569     [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
0570     [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
0571     [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
0572     [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
0573     [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
0574     [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
0575     [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
0576     [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
0577     [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
0578     [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
0579     [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
0580     [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
0581     [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
0582     [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
0583     [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
0584 };
0585 
0586 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
0587     [ 0] = { 0x3000, 0x1800, 0x1800, },
0588     [ 1] = { 0xb000, 0x18d0, 0x2e60, },
0589     [ 2] = { 0xb000, 0x1990, 0x2ce0, },
0590     [ 3] = { 0xb020, 0x1a68, 0x2b40, },
0591     [ 4] = { 0xb040, 0x1b20, 0x29e0, },
0592     [ 5] = { 0xb060, 0x1bd8, 0x2880, },
0593     [ 6] = { 0xb080, 0x1c88, 0x3e60, },
0594     [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
0595     [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
0596     [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
0597     [10] = { 0xb100, 0x1eb8, 0x3620, },
0598     [11] = { 0xb100, 0x1f18, 0x34a0, },
0599     [12] = { 0xb100, 0x1f68, 0x3360, },
0600     [13] = { 0xb0e0, 0x1fa8, 0x3240, },
0601     [14] = { 0xb0c0, 0x1fe0, 0x3140, },
0602     [15] = { 0xb060, 0x1ff0, 0x30a0, },
0603     [16] = { 0x3000, 0x0800, 0x3000, },
0604 };
0605 
0606 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
0607 {
0608     memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
0609     memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
0610             sizeof(uv_static_hcoeffs));
0611 }
0612 
0613 static bool update_scaling_factors(struct intel_overlay *overlay,
0614                    struct overlay_registers __iomem *regs,
0615                    struct drm_intel_overlay_put_image *params)
0616 {
0617     /* fixed point with a 12 bit shift */
0618     u32 xscale, yscale, xscale_UV, yscale_UV;
0619 #define FP_SHIFT 12
0620 #define FRACT_MASK 0xfff
0621     bool scale_changed = false;
0622     int uv_hscale = uv_hsubsampling(params->flags);
0623     int uv_vscale = uv_vsubsampling(params->flags);
0624 
0625     if (params->dst_width > 1)
0626         xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
0627             params->dst_width;
0628     else
0629         xscale = 1 << FP_SHIFT;
0630 
0631     if (params->dst_height > 1)
0632         yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
0633             params->dst_height;
0634     else
0635         yscale = 1 << FP_SHIFT;
0636 
0637     /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
0638     xscale_UV = xscale/uv_hscale;
0639     yscale_UV = yscale/uv_vscale;
0640     /* make the Y scale to UV scale ratio an exact multiply */
0641     xscale = xscale_UV * uv_hscale;
0642     yscale = yscale_UV * uv_vscale;
0643     /*} else {
0644       xscale_UV = 0;
0645       yscale_UV = 0;
0646       }*/
0647 
0648     if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
0649         scale_changed = true;
0650     overlay->old_xscale = xscale;
0651     overlay->old_yscale = yscale;
0652 
0653     iowrite32(((yscale & FRACT_MASK) << 20) |
0654           ((xscale >> FP_SHIFT)  << 16) |
0655           ((xscale & FRACT_MASK) << 3),
0656          &regs->YRGBSCALE);
0657 
0658     iowrite32(((yscale_UV & FRACT_MASK) << 20) |
0659           ((xscale_UV >> FP_SHIFT)  << 16) |
0660           ((xscale_UV & FRACT_MASK) << 3),
0661          &regs->UVSCALE);
0662 
0663     iowrite32((((yscale    >> FP_SHIFT) << 16) |
0664            ((yscale_UV >> FP_SHIFT) << 0)),
0665          &regs->UVSCALEV);
0666 
0667     if (scale_changed)
0668         update_polyphase_filter(regs);
0669 
0670     return scale_changed;
0671 }
0672 
0673 static void update_colorkey(struct intel_overlay *overlay,
0674                 struct overlay_registers __iomem *regs)
0675 {
0676     const struct intel_plane_state *state =
0677         to_intel_plane_state(overlay->crtc->base.primary->state);
0678     u32 key = overlay->color_key;
0679     u32 format = 0;
0680     u32 flags = 0;
0681 
0682     if (overlay->color_key_enabled)
0683         flags |= DST_KEY_ENABLE;
0684 
0685     if (state->uapi.visible)
0686         format = state->hw.fb->format->format;
0687 
0688     switch (format) {
0689     case DRM_FORMAT_C8:
0690         key = RGB8I_TO_COLORKEY(key);
0691         flags |= CLK_RGB24_MASK;
0692         break;
0693     case DRM_FORMAT_XRGB1555:
0694         key = RGB15_TO_COLORKEY(key);
0695         flags |= CLK_RGB15_MASK;
0696         break;
0697     case DRM_FORMAT_RGB565:
0698         key = RGB16_TO_COLORKEY(key);
0699         flags |= CLK_RGB16_MASK;
0700         break;
0701     case DRM_FORMAT_XRGB2101010:
0702     case DRM_FORMAT_XBGR2101010:
0703         key = RGB30_TO_COLORKEY(key);
0704         flags |= CLK_RGB24_MASK;
0705         break;
0706     default:
0707         flags |= CLK_RGB24_MASK;
0708         break;
0709     }
0710 
0711     iowrite32(key, &regs->DCLRKV);
0712     iowrite32(flags, &regs->DCLRKM);
0713 }
0714 
0715 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
0716 {
0717     u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
0718 
0719     if (params->flags & I915_OVERLAY_YUV_PLANAR) {
0720         switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
0721         case I915_OVERLAY_YUV422:
0722             cmd |= OCMD_YUV_422_PLANAR;
0723             break;
0724         case I915_OVERLAY_YUV420:
0725             cmd |= OCMD_YUV_420_PLANAR;
0726             break;
0727         case I915_OVERLAY_YUV411:
0728         case I915_OVERLAY_YUV410:
0729             cmd |= OCMD_YUV_410_PLANAR;
0730             break;
0731         }
0732     } else { /* YUV packed */
0733         switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
0734         case I915_OVERLAY_YUV422:
0735             cmd |= OCMD_YUV_422_PACKED;
0736             break;
0737         case I915_OVERLAY_YUV411:
0738             cmd |= OCMD_YUV_411_PACKED;
0739             break;
0740         }
0741 
0742         switch (params->flags & I915_OVERLAY_SWAP_MASK) {
0743         case I915_OVERLAY_NO_SWAP:
0744             break;
0745         case I915_OVERLAY_UV_SWAP:
0746             cmd |= OCMD_UV_SWAP;
0747             break;
0748         case I915_OVERLAY_Y_SWAP:
0749             cmd |= OCMD_Y_SWAP;
0750             break;
0751         case I915_OVERLAY_Y_AND_UV_SWAP:
0752             cmd |= OCMD_Y_AND_UV_SWAP;
0753             break;
0754         }
0755     }
0756 
0757     return cmd;
0758 }
0759 
0760 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo)
0761 {
0762     struct i915_gem_ww_ctx ww;
0763     struct i915_vma *vma;
0764     int ret;
0765 
0766     i915_gem_ww_ctx_init(&ww, true);
0767 retry:
0768     ret = i915_gem_object_lock(new_bo, &ww);
0769     if (!ret) {
0770         vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0,
0771                                NULL, PIN_MAPPABLE);
0772         ret = PTR_ERR_OR_ZERO(vma);
0773     }
0774     if (ret == -EDEADLK) {
0775         ret = i915_gem_ww_ctx_backoff(&ww);
0776         if (!ret)
0777             goto retry;
0778     }
0779     i915_gem_ww_ctx_fini(&ww);
0780     if (ret)
0781         return ERR_PTR(ret);
0782 
0783     return vma;
0784 }
0785 
0786 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
0787                       struct drm_i915_gem_object *new_bo,
0788                       struct drm_intel_overlay_put_image *params)
0789 {
0790     struct overlay_registers __iomem *regs = overlay->regs;
0791     struct drm_i915_private *dev_priv = overlay->i915;
0792     u32 swidth, swidthsw, sheight, ostride;
0793     enum pipe pipe = overlay->crtc->pipe;
0794     bool scale_changed = false;
0795     struct i915_vma *vma;
0796     int ret, tmp_width;
0797 
0798     drm_WARN_ON(&dev_priv->drm,
0799             !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
0800 
0801     ret = intel_overlay_release_old_vid(overlay);
0802     if (ret != 0)
0803         return ret;
0804 
0805     atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
0806 
0807     vma = intel_overlay_pin_fb(new_bo);
0808     if (IS_ERR(vma)) {
0809         ret = PTR_ERR(vma);
0810         goto out_pin_section;
0811     }
0812 
0813     i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
0814 
0815     if (!overlay->active) {
0816         const struct intel_crtc_state *crtc_state =
0817             overlay->crtc->config;
0818         u32 oconfig = 0;
0819 
0820         if (crtc_state->gamma_enable &&
0821             crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
0822             oconfig |= OCONF_CC_OUT_8BIT;
0823         if (crtc_state->gamma_enable)
0824             oconfig |= OCONF_GAMMA2_ENABLE;
0825         if (DISPLAY_VER(dev_priv) == 4)
0826             oconfig |= OCONF_CSC_MODE_BT709;
0827         oconfig |= pipe == 0 ?
0828             OCONF_PIPE_A : OCONF_PIPE_B;
0829         iowrite32(oconfig, &regs->OCONFIG);
0830 
0831         ret = intel_overlay_on(overlay);
0832         if (ret != 0)
0833             goto out_unpin;
0834     }
0835 
0836     iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);
0837     iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);
0838 
0839     if (params->flags & I915_OVERLAY_YUV_PACKED)
0840         tmp_width = packed_width_bytes(params->flags,
0841                            params->src_width);
0842     else
0843         tmp_width = params->src_width;
0844 
0845     swidth = params->src_width;
0846     swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
0847     sheight = params->src_height;
0848     iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
0849     ostride = params->stride_Y;
0850 
0851     if (params->flags & I915_OVERLAY_YUV_PLANAR) {
0852         int uv_hscale = uv_hsubsampling(params->flags);
0853         int uv_vscale = uv_vsubsampling(params->flags);
0854         u32 tmp_U, tmp_V;
0855 
0856         swidth |= (params->src_width / uv_hscale) << 16;
0857         sheight |= (params->src_height / uv_vscale) << 16;
0858 
0859         tmp_U = calc_swidthsw(dev_priv, params->offset_U,
0860                       params->src_width / uv_hscale);
0861         tmp_V = calc_swidthsw(dev_priv, params->offset_V,
0862                       params->src_width / uv_hscale);
0863         swidthsw |= max(tmp_U, tmp_V) << 16;
0864 
0865         iowrite32(i915_ggtt_offset(vma) + params->offset_U,
0866               &regs->OBUF_0U);
0867         iowrite32(i915_ggtt_offset(vma) + params->offset_V,
0868               &regs->OBUF_0V);
0869 
0870         ostride |= params->stride_UV << 16;
0871     }
0872 
0873     iowrite32(swidth, &regs->SWIDTH);
0874     iowrite32(swidthsw, &regs->SWIDTHSW);
0875     iowrite32(sheight, &regs->SHEIGHT);
0876     iowrite32(ostride, &regs->OSTRIDE);
0877 
0878     scale_changed = update_scaling_factors(overlay, regs, params);
0879 
0880     update_colorkey(overlay, regs);
0881 
0882     iowrite32(overlay_cmd_reg(params), &regs->OCMD);
0883 
0884     ret = intel_overlay_continue(overlay, vma, scale_changed);
0885     if (ret)
0886         goto out_unpin;
0887 
0888     return 0;
0889 
0890 out_unpin:
0891     i915_vma_unpin(vma);
0892 out_pin_section:
0893     atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
0894 
0895     return ret;
0896 }
0897 
0898 int intel_overlay_switch_off(struct intel_overlay *overlay)
0899 {
0900     struct drm_i915_private *dev_priv = overlay->i915;
0901     int ret;
0902 
0903     drm_WARN_ON(&dev_priv->drm,
0904             !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
0905 
0906     ret = intel_overlay_recover_from_interrupt(overlay);
0907     if (ret != 0)
0908         return ret;
0909 
0910     if (!overlay->active)
0911         return 0;
0912 
0913     ret = intel_overlay_release_old_vid(overlay);
0914     if (ret != 0)
0915         return ret;
0916 
0917     iowrite32(0, &overlay->regs->OCMD);
0918 
0919     return intel_overlay_off(overlay);
0920 }
0921 
0922 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
0923                       struct intel_crtc *crtc)
0924 {
0925     if (!crtc->active)
0926         return -EINVAL;
0927 
0928     /* can't use the overlay with double wide pipe */
0929     if (crtc->config->double_wide)
0930         return -EINVAL;
0931 
0932     return 0;
0933 }
0934 
0935 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
0936 {
0937     struct drm_i915_private *dev_priv = overlay->i915;
0938     u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL);
0939     u32 ratio;
0940 
0941     /* XXX: This is not the same logic as in the xorg driver, but more in
0942      * line with the intel documentation for the i965
0943      */
0944     if (DISPLAY_VER(dev_priv) >= 4) {
0945         /* on i965 use the PGM reg to read out the autoscaler values */
0946         ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
0947     } else {
0948         if (pfit_control & VERT_AUTO_SCALE)
0949             ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
0950         else
0951             ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
0952         ratio >>= PFIT_VERT_SCALE_SHIFT;
0953     }
0954 
0955     overlay->pfit_vscale_ratio = ratio;
0956 }
0957 
0958 static int check_overlay_dst(struct intel_overlay *overlay,
0959                  struct drm_intel_overlay_put_image *rec)
0960 {
0961     const struct intel_crtc_state *crtc_state =
0962         overlay->crtc->config;
0963     struct drm_rect req, clipped;
0964 
0965     drm_rect_init(&req, rec->dst_x, rec->dst_y,
0966               rec->dst_width, rec->dst_height);
0967 
0968     clipped = req;
0969     drm_rect_intersect(&clipped, &crtc_state->pipe_src);
0970 
0971     if (!drm_rect_visible(&clipped) ||
0972         !drm_rect_equals(&clipped, &req))
0973         return -EINVAL;
0974 
0975     return 0;
0976 }
0977 
0978 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
0979 {
0980     u32 tmp;
0981 
0982     /* downscaling limit is 8.0 */
0983     tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
0984     if (tmp > 7)
0985         return -EINVAL;
0986 
0987     tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
0988     if (tmp > 7)
0989         return -EINVAL;
0990 
0991     return 0;
0992 }
0993 
0994 static int check_overlay_src(struct drm_i915_private *dev_priv,
0995                  struct drm_intel_overlay_put_image *rec,
0996                  struct drm_i915_gem_object *new_bo)
0997 {
0998     int uv_hscale = uv_hsubsampling(rec->flags);
0999     int uv_vscale = uv_vsubsampling(rec->flags);
1000     u32 stride_mask;
1001     int depth;
1002     u32 tmp;
1003 
1004     /* check src dimensions */
1005     if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
1006         if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
1007             rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
1008             return -EINVAL;
1009     } else {
1010         if (rec->src_height > IMAGE_MAX_HEIGHT ||
1011             rec->src_width  > IMAGE_MAX_WIDTH)
1012             return -EINVAL;
1013     }
1014 
1015     /* better safe than sorry, use 4 as the maximal subsampling ratio */
1016     if (rec->src_height < N_VERT_Y_TAPS*4 ||
1017         rec->src_width  < N_HORIZ_Y_TAPS*4)
1018         return -EINVAL;
1019 
1020     /* check alignment constraints */
1021     switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1022     case I915_OVERLAY_RGB:
1023         /* not implemented */
1024         return -EINVAL;
1025 
1026     case I915_OVERLAY_YUV_PACKED:
1027         if (uv_vscale != 1)
1028             return -EINVAL;
1029 
1030         depth = packed_depth_bytes(rec->flags);
1031         if (depth < 0)
1032             return depth;
1033 
1034         /* ignore UV planes */
1035         rec->stride_UV = 0;
1036         rec->offset_U = 0;
1037         rec->offset_V = 0;
1038         /* check pixel alignment */
1039         if (rec->offset_Y % depth)
1040             return -EINVAL;
1041         break;
1042 
1043     case I915_OVERLAY_YUV_PLANAR:
1044         if (uv_vscale < 0 || uv_hscale < 0)
1045             return -EINVAL;
1046         /* no offset restrictions for planar formats */
1047         break;
1048 
1049     default:
1050         return -EINVAL;
1051     }
1052 
1053     if (rec->src_width % uv_hscale)
1054         return -EINVAL;
1055 
1056     /* stride checking */
1057     if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1058         stride_mask = 255;
1059     else
1060         stride_mask = 63;
1061 
1062     if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1063         return -EINVAL;
1064     if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)
1065         return -EINVAL;
1066 
1067     tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1068         4096 : 8192;
1069     if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1070         return -EINVAL;
1071 
1072     /* check buffer dimensions */
1073     switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1074     case I915_OVERLAY_RGB:
1075     case I915_OVERLAY_YUV_PACKED:
1076         /* always 4 Y values per depth pixels */
1077         if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1078             return -EINVAL;
1079 
1080         tmp = rec->stride_Y*rec->src_height;
1081         if (rec->offset_Y + tmp > new_bo->base.size)
1082             return -EINVAL;
1083         break;
1084 
1085     case I915_OVERLAY_YUV_PLANAR:
1086         if (rec->src_width > rec->stride_Y)
1087             return -EINVAL;
1088         if (rec->src_width/uv_hscale > rec->stride_UV)
1089             return -EINVAL;
1090 
1091         tmp = rec->stride_Y * rec->src_height;
1092         if (rec->offset_Y + tmp > new_bo->base.size)
1093             return -EINVAL;
1094 
1095         tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1096         if (rec->offset_U + tmp > new_bo->base.size ||
1097             rec->offset_V + tmp > new_bo->base.size)
1098             return -EINVAL;
1099         break;
1100     }
1101 
1102     return 0;
1103 }
1104 
1105 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1106                   struct drm_file *file_priv)
1107 {
1108     struct drm_intel_overlay_put_image *params = data;
1109     struct drm_i915_private *dev_priv = to_i915(dev);
1110     struct intel_overlay *overlay;
1111     struct drm_crtc *drmmode_crtc;
1112     struct intel_crtc *crtc;
1113     struct drm_i915_gem_object *new_bo;
1114     int ret;
1115 
1116     overlay = dev_priv->overlay;
1117     if (!overlay) {
1118         drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1119         return -ENODEV;
1120     }
1121 
1122     if (!(params->flags & I915_OVERLAY_ENABLE)) {
1123         drm_modeset_lock_all(dev);
1124         ret = intel_overlay_switch_off(overlay);
1125         drm_modeset_unlock_all(dev);
1126 
1127         return ret;
1128     }
1129 
1130     drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1131     if (!drmmode_crtc)
1132         return -ENOENT;
1133     crtc = to_intel_crtc(drmmode_crtc);
1134 
1135     new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1136     if (!new_bo)
1137         return -ENOENT;
1138 
1139     drm_modeset_lock_all(dev);
1140 
1141     if (i915_gem_object_is_tiled(new_bo)) {
1142         drm_dbg_kms(&dev_priv->drm,
1143                 "buffer used for overlay image can not be tiled\n");
1144         ret = -EINVAL;
1145         goto out_unlock;
1146     }
1147 
1148     ret = intel_overlay_recover_from_interrupt(overlay);
1149     if (ret != 0)
1150         goto out_unlock;
1151 
1152     if (overlay->crtc != crtc) {
1153         ret = intel_overlay_switch_off(overlay);
1154         if (ret != 0)
1155             goto out_unlock;
1156 
1157         ret = check_overlay_possible_on_crtc(overlay, crtc);
1158         if (ret != 0)
1159             goto out_unlock;
1160 
1161         overlay->crtc = crtc;
1162         crtc->overlay = overlay;
1163 
1164         /* line too wide, i.e. one-line-mode */
1165         if (drm_rect_width(&crtc->config->pipe_src) > 1024 &&
1166             crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1167             overlay->pfit_active = true;
1168             update_pfit_vscale_ratio(overlay);
1169         } else
1170             overlay->pfit_active = false;
1171     }
1172 
1173     ret = check_overlay_dst(overlay, params);
1174     if (ret != 0)
1175         goto out_unlock;
1176 
1177     if (overlay->pfit_active) {
1178         params->dst_y = (((u32)params->dst_y << 12) /
1179                  overlay->pfit_vscale_ratio);
1180         /* shifting right rounds downwards, so add 1 */
1181         params->dst_height = (((u32)params->dst_height << 12) /
1182                  overlay->pfit_vscale_ratio) + 1;
1183     }
1184 
1185     if (params->src_scan_height > params->src_height ||
1186         params->src_scan_width > params->src_width) {
1187         ret = -EINVAL;
1188         goto out_unlock;
1189     }
1190 
1191     ret = check_overlay_src(dev_priv, params, new_bo);
1192     if (ret != 0)
1193         goto out_unlock;
1194 
1195     /* Check scaling after src size to prevent a divide-by-zero. */
1196     ret = check_overlay_scaling(params);
1197     if (ret != 0)
1198         goto out_unlock;
1199 
1200     ret = intel_overlay_do_put_image(overlay, new_bo, params);
1201     if (ret != 0)
1202         goto out_unlock;
1203 
1204     drm_modeset_unlock_all(dev);
1205     i915_gem_object_put(new_bo);
1206 
1207     return 0;
1208 
1209 out_unlock:
1210     drm_modeset_unlock_all(dev);
1211     i915_gem_object_put(new_bo);
1212 
1213     return ret;
1214 }
1215 
1216 static void update_reg_attrs(struct intel_overlay *overlay,
1217                  struct overlay_registers __iomem *regs)
1218 {
1219     iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1220           &regs->OCLRC0);
1221     iowrite32(overlay->saturation, &regs->OCLRC1);
1222 }
1223 
1224 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1225 {
1226     int i;
1227 
1228     if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1229         return false;
1230 
1231     for (i = 0; i < 3; i++) {
1232         if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1233             return false;
1234     }
1235 
1236     return true;
1237 }
1238 
1239 static bool check_gamma5_errata(u32 gamma5)
1240 {
1241     int i;
1242 
1243     for (i = 0; i < 3; i++) {
1244         if (((gamma5 >> i*8) & 0xff) == 0x80)
1245             return false;
1246     }
1247 
1248     return true;
1249 }
1250 
1251 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1252 {
1253     if (!check_gamma_bounds(0, attrs->gamma0) ||
1254         !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1255         !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1256         !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1257         !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1258         !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1259         !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1260         return -EINVAL;
1261 
1262     if (!check_gamma5_errata(attrs->gamma5))
1263         return -EINVAL;
1264 
1265     return 0;
1266 }
1267 
1268 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1269                   struct drm_file *file_priv)
1270 {
1271     struct drm_intel_overlay_attrs *attrs = data;
1272     struct drm_i915_private *dev_priv = to_i915(dev);
1273     struct intel_overlay *overlay;
1274     int ret;
1275 
1276     overlay = dev_priv->overlay;
1277     if (!overlay) {
1278         drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1279         return -ENODEV;
1280     }
1281 
1282     drm_modeset_lock_all(dev);
1283 
1284     ret = -EINVAL;
1285     if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1286         attrs->color_key  = overlay->color_key;
1287         attrs->brightness = overlay->brightness;
1288         attrs->contrast   = overlay->contrast;
1289         attrs->saturation = overlay->saturation;
1290 
1291         if (DISPLAY_VER(dev_priv) != 2) {
1292             attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
1293             attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
1294             attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
1295             attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);
1296             attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);
1297             attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);
1298         }
1299     } else {
1300         if (attrs->brightness < -128 || attrs->brightness > 127)
1301             goto out_unlock;
1302         if (attrs->contrast > 255)
1303             goto out_unlock;
1304         if (attrs->saturation > 1023)
1305             goto out_unlock;
1306 
1307         overlay->color_key  = attrs->color_key;
1308         overlay->brightness = attrs->brightness;
1309         overlay->contrast   = attrs->contrast;
1310         overlay->saturation = attrs->saturation;
1311 
1312         update_reg_attrs(overlay, overlay->regs);
1313 
1314         if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1315             if (DISPLAY_VER(dev_priv) == 2)
1316                 goto out_unlock;
1317 
1318             if (overlay->active) {
1319                 ret = -EBUSY;
1320                 goto out_unlock;
1321             }
1322 
1323             ret = check_gamma(attrs);
1324             if (ret)
1325                 goto out_unlock;
1326 
1327             intel_de_write(dev_priv, OGAMC0, attrs->gamma0);
1328             intel_de_write(dev_priv, OGAMC1, attrs->gamma1);
1329             intel_de_write(dev_priv, OGAMC2, attrs->gamma2);
1330             intel_de_write(dev_priv, OGAMC3, attrs->gamma3);
1331             intel_de_write(dev_priv, OGAMC4, attrs->gamma4);
1332             intel_de_write(dev_priv, OGAMC5, attrs->gamma5);
1333         }
1334     }
1335     overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1336 
1337     ret = 0;
1338 out_unlock:
1339     drm_modeset_unlock_all(dev);
1340 
1341     return ret;
1342 }
1343 
1344 static int get_registers(struct intel_overlay *overlay, bool use_phys)
1345 {
1346     struct drm_i915_private *i915 = overlay->i915;
1347     struct drm_i915_gem_object *obj;
1348     struct i915_vma *vma;
1349     int err;
1350 
1351     obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
1352     if (IS_ERR(obj))
1353         obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1354     if (IS_ERR(obj))
1355         return PTR_ERR(obj);
1356 
1357     vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1358     if (IS_ERR(vma)) {
1359         err = PTR_ERR(vma);
1360         goto err_put_bo;
1361     }
1362 
1363     if (use_phys)
1364         overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1365     else
1366         overlay->flip_addr = i915_ggtt_offset(vma);
1367     overlay->regs = i915_vma_pin_iomap(vma);
1368     i915_vma_unpin(vma);
1369 
1370     if (IS_ERR(overlay->regs)) {
1371         err = PTR_ERR(overlay->regs);
1372         goto err_put_bo;
1373     }
1374 
1375     overlay->reg_bo = obj;
1376     return 0;
1377 
1378 err_put_bo:
1379     i915_gem_object_put(obj);
1380     return err;
1381 }
1382 
1383 void intel_overlay_setup(struct drm_i915_private *dev_priv)
1384 {
1385     struct intel_overlay *overlay;
1386     struct intel_engine_cs *engine;
1387     int ret;
1388 
1389     if (!HAS_OVERLAY(dev_priv))
1390         return;
1391 
1392     engine = to_gt(dev_priv)->engine[RCS0];
1393     if (!engine || !engine->kernel_context)
1394         return;
1395 
1396     overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1397     if (!overlay)
1398         return;
1399 
1400     overlay->i915 = dev_priv;
1401     overlay->context = engine->kernel_context;
1402     overlay->color_key = 0x0101fe;
1403     overlay->color_key_enabled = true;
1404     overlay->brightness = -19;
1405     overlay->contrast = 75;
1406     overlay->saturation = 146;
1407 
1408     i915_active_init(&overlay->last_flip,
1409              NULL, intel_overlay_last_flip_retire, 0);
1410 
1411     ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1412     if (ret)
1413         goto out_free;
1414 
1415     memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1416     update_polyphase_filter(overlay->regs);
1417     update_reg_attrs(overlay, overlay->regs);
1418 
1419     dev_priv->overlay = overlay;
1420     drm_info(&dev_priv->drm, "Initialized overlay support.\n");
1421     return;
1422 
1423 out_free:
1424     kfree(overlay);
1425 }
1426 
1427 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1428 {
1429     struct intel_overlay *overlay;
1430 
1431     overlay = fetch_and_zero(&dev_priv->overlay);
1432     if (!overlay)
1433         return;
1434 
1435     /*
1436      * The bo's should be free'd by the generic code already.
1437      * Furthermore modesetting teardown happens beforehand so the
1438      * hardware should be off already.
1439      */
1440     drm_WARN_ON(&dev_priv->drm, overlay->active);
1441 
1442     i915_gem_object_put(overlay->reg_bo);
1443     i915_active_fini(&overlay->last_flip);
1444 
1445     kfree(overlay);
1446 }
1447 
1448 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1449 
1450 struct intel_overlay_error_state {
1451     struct overlay_registers regs;
1452     unsigned long base;
1453     u32 dovsta;
1454     u32 isr;
1455 };
1456 
1457 struct intel_overlay_error_state *
1458 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1459 {
1460     struct intel_overlay *overlay = dev_priv->overlay;
1461     struct intel_overlay_error_state *error;
1462 
1463     if (!overlay || !overlay->active)
1464         return NULL;
1465 
1466     error = kmalloc(sizeof(*error), GFP_ATOMIC);
1467     if (error == NULL)
1468         return NULL;
1469 
1470     error->dovsta = intel_de_read(dev_priv, DOVSTA);
1471     error->isr = intel_de_read(dev_priv, GEN2_ISR);
1472     error->base = overlay->flip_addr;
1473 
1474     memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1475 
1476     return error;
1477 }
1478 
1479 void
1480 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1481                 struct intel_overlay_error_state *error)
1482 {
1483     i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1484               error->dovsta, error->isr);
1485     i915_error_printf(m, "  Register file at 0x%08lx:\n",
1486               error->base);
1487 
1488 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1489     P(OBUF_0Y);
1490     P(OBUF_1Y);
1491     P(OBUF_0U);
1492     P(OBUF_0V);
1493     P(OBUF_1U);
1494     P(OBUF_1V);
1495     P(OSTRIDE);
1496     P(YRGB_VPH);
1497     P(UV_VPH);
1498     P(HORZ_PH);
1499     P(INIT_PHS);
1500     P(DWINPOS);
1501     P(DWINSZ);
1502     P(SWIDTH);
1503     P(SWIDTHSW);
1504     P(SHEIGHT);
1505     P(YRGBSCALE);
1506     P(UVSCALE);
1507     P(OCLRC0);
1508     P(OCLRC1);
1509     P(DCLRKV);
1510     P(DCLRKM);
1511     P(SCLRKVH);
1512     P(SCLRKVL);
1513     P(SCLRKEN);
1514     P(OCONFIG);
1515     P(OCMD);
1516     P(OSTART_0Y);
1517     P(OSTART_1Y);
1518     P(OSTART_0U);
1519     P(OSTART_0V);
1520     P(OSTART_1U);
1521     P(OSTART_1V);
1522     P(OTILEOFF_0Y);
1523     P(OTILEOFF_1Y);
1524     P(OTILEOFF_0U);
1525     P(OTILEOFF_0V);
1526     P(OTILEOFF_1U);
1527     P(OTILEOFF_1V);
1528     P(FASTHSCALE);
1529     P(UVSCALEV);
1530 #undef P
1531 }
1532 
1533 #endif
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