i915/display/intel_gmbus.c

0001 /*
0002  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
0003  * Copyright © 2006-2008,2010 Intel Corporation
0004  *   Jesse Barnes <jesse.barnes@intel.com>
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the next
0014  * paragraph) shall be included in all copies or substantial portions of the
0015  * Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0018  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0019  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0020  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0021  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0022  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0023  * DEALINGS IN THE SOFTWARE.
0024  *
0025  * Authors:
0026  *  Eric Anholt <eric@anholt.net>
0027  *  Chris Wilson <chris@chris-wilson.co.uk>
0028  */
0029
0030 #include <linux/export.h>
0031 #include <linux/i2c-algo-bit.h>
0032 #include <linux/i2c.h>
0033
0034 #include <drm/display/drm_hdcp_helper.h>
0035
0036 #include "i915_drv.h"
0037 #include "intel_de.h"
0038 #include "intel_display_types.h"
0039 #include "intel_gmbus.h"
0040
0041 struct intel_gmbus {
0042     struct i2c_adapter adapter;
0043 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
0044     u32 force_bit;
0045     u32 reg0;
0046     i915_reg_t gpio_reg;
0047     struct i2c_algo_bit_data bit_algo;
0048     struct drm_i915_private *dev_priv;
0049 };
0050
0051 struct gmbus_pin {
0052     const char *name;
0053     enum i915_gpio gpio;
0054 };
0055
0056 /* Map gmbus pin pairs to names and registers. */
0057 static const struct gmbus_pin gmbus_pins[] = {
0058     [GMBUS_PIN_SSC] = { "ssc", GPIOB },
0059     [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
0060     [GMBUS_PIN_PANEL] = { "panel", GPIOC },
0061     [GMBUS_PIN_DPC] = { "dpc", GPIOD },
0062     [GMBUS_PIN_DPB] = { "dpb", GPIOE },
0063     [GMBUS_PIN_DPD] = { "dpd", GPIOF },
0064 };
0065
0066 static const struct gmbus_pin gmbus_pins_bdw[] = {
0067     [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
0068     [GMBUS_PIN_DPC] = { "dpc", GPIOD },
0069     [GMBUS_PIN_DPB] = { "dpb", GPIOE },
0070     [GMBUS_PIN_DPD] = { "dpd", GPIOF },
0071 };
0072
0073 static const struct gmbus_pin gmbus_pins_skl[] = {
0074     [GMBUS_PIN_DPC] = { "dpc", GPIOD },
0075     [GMBUS_PIN_DPB] = { "dpb", GPIOE },
0076     [GMBUS_PIN_DPD] = { "dpd", GPIOF },
0077 };
0078
0079 static const struct gmbus_pin gmbus_pins_bxt[] = {
0080     [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
0081     [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
0082     [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
0083 };
0084
0085 static const struct gmbus_pin gmbus_pins_cnp[] = {
0086     [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
0087     [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
0088     [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
0089     [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
0090 };
0091
0092 static const struct gmbus_pin gmbus_pins_icp[] = {
0093     [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
0094     [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
0095     [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
0096     [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
0097     [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
0098     [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
0099     [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
0100     [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
0101     [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
0102 };
0103
0104 static const struct gmbus_pin gmbus_pins_dg1[] = {
0105     [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
0106     [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
0107     [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
0108     [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
0109 };
0110
0111 static const struct gmbus_pin gmbus_pins_dg2[] = {
0112     [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
0113     [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
0114     [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
0115     [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
0116     [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
0117 };
0118
0119 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
0120                          unsigned int pin)
0121 {
0122     const struct gmbus_pin *pins;
0123     size_t size;
0124
0125     if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
0126         pins = gmbus_pins_dg2;
0127         size = ARRAY_SIZE(gmbus_pins_dg2);
0128     } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
0129         pins = gmbus_pins_dg1;
0130         size = ARRAY_SIZE(gmbus_pins_dg1);
0131     } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
0132         pins = gmbus_pins_icp;
0133         size = ARRAY_SIZE(gmbus_pins_icp);
0134     } else if (HAS_PCH_CNP(i915)) {
0135         pins = gmbus_pins_cnp;
0136         size = ARRAY_SIZE(gmbus_pins_cnp);
0137     } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
0138         pins = gmbus_pins_bxt;
0139         size = ARRAY_SIZE(gmbus_pins_bxt);
0140     } else if (DISPLAY_VER(i915) == 9) {
0141         pins = gmbus_pins_skl;
0142         size = ARRAY_SIZE(gmbus_pins_skl);
0143     } else if (IS_BROADWELL(i915)) {
0144         pins = gmbus_pins_bdw;
0145         size = ARRAY_SIZE(gmbus_pins_bdw);
0146     } else {
0147         pins = gmbus_pins;
0148         size = ARRAY_SIZE(gmbus_pins);
0149     }
0150
0151     if (pin >= size || !pins[pin].name)
0152         return NULL;
0153
0154     return &pins[pin];
0155 }
0156
0157 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
0158 {
0159     return get_gmbus_pin(i915, pin);
0160 }
0161
0162 /* Intel GPIO access functions */
0163
0164 #define I2C_RISEFALL_TIME 10
0165
0166 static inline struct intel_gmbus *
0167 to_intel_gmbus(struct i2c_adapter *i2c)
0168 {
0169     return container_of(i2c, struct intel_gmbus, adapter);
0170 }
0171
0172 void
0173 intel_gmbus_reset(struct drm_i915_private *dev_priv)
0174 {
0175     intel_de_write(dev_priv, GMBUS0, 0);
0176     intel_de_write(dev_priv, GMBUS4, 0);
0177 }
0178
0179 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
0180                    bool enable)
0181 {
0182     u32 val;
0183
0184     /* When using bit bashing for I2C, this bit needs to be set to 1 */
0185     val = intel_de_read(dev_priv, DSPCLK_GATE_D);
0186     if (!enable)
0187         val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
0188     else
0189         val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
0190     intel_de_write(dev_priv, DSPCLK_GATE_D, val);
0191 }
0192
0193 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
0194                    bool enable)
0195 {
0196     u32 val;
0197
0198     val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
0199     if (!enable)
0200         val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
0201     else
0202         val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
0203     intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
0204 }
0205
0206 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
0207                    bool enable)
0208 {
0209     u32 val;
0210
0211     val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
0212     if (!enable)
0213         val |= BXT_GMBUS_GATING_DIS;
0214     else
0215         val &= ~BXT_GMBUS_GATING_DIS;
0216     intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
0217 }
0218
0219 static u32 get_reserved(struct intel_gmbus *bus)
0220 {
0221     struct drm_i915_private *i915 = bus->dev_priv;
0222     struct intel_uncore *uncore = &i915->uncore;
0223     u32 reserved = 0;
0224
0225     /* On most chips, these bits must be preserved in software. */
0226     if (!IS_I830(i915) && !IS_I845G(i915))
0227         reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
0228                (GPIO_DATA_PULLUP_DISABLE |
0229                 GPIO_CLOCK_PULLUP_DISABLE);
0230
0231     return reserved;
0232 }
0233
0234 static int get_clock(void *data)
0235 {
0236     struct intel_gmbus *bus = data;
0237     struct intel_uncore *uncore = &bus->dev_priv->uncore;
0238     u32 reserved = get_reserved(bus);
0239
0240     intel_uncore_write_notrace(uncore,
0241                    bus->gpio_reg,
0242                    reserved | GPIO_CLOCK_DIR_MASK);
0243     intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
0244
0245     return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
0246         GPIO_CLOCK_VAL_IN) != 0;
0247 }
0248
0249 static int get_data(void *data)
0250 {
0251     struct intel_gmbus *bus = data;
0252     struct intel_uncore *uncore = &bus->dev_priv->uncore;
0253     u32 reserved = get_reserved(bus);
0254
0255     intel_uncore_write_notrace(uncore,
0256                    bus->gpio_reg,
0257                    reserved | GPIO_DATA_DIR_MASK);
0258     intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
0259
0260     return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
0261         GPIO_DATA_VAL_IN) != 0;
0262 }
0263
0264 static void set_clock(void *data, int state_high)
0265 {
0266     struct intel_gmbus *bus = data;
0267     struct intel_uncore *uncore = &bus->dev_priv->uncore;
0268     u32 reserved = get_reserved(bus);
0269     u32 clock_bits;
0270
0271     if (state_high)
0272         clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
0273     else
0274         clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
0275                  GPIO_CLOCK_VAL_MASK;
0276
0277     intel_uncore_write_notrace(uncore,
0278                    bus->gpio_reg,
0279                    reserved | clock_bits);
0280     intel_uncore_posting_read(uncore, bus->gpio_reg);
0281 }
0282
0283 static void set_data(void *data, int state_high)
0284 {
0285     struct intel_gmbus *bus = data;
0286     struct intel_uncore *uncore = &bus->dev_priv->uncore;
0287     u32 reserved = get_reserved(bus);
0288     u32 data_bits;
0289
0290     if (state_high)
0291         data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
0292     else
0293         data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
0294             GPIO_DATA_VAL_MASK;
0295
0296     intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
0297     intel_uncore_posting_read(uncore, bus->gpio_reg);
0298 }
0299
0300 static int
0301 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
0302 {
0303     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0304     struct drm_i915_private *dev_priv = bus->dev_priv;
0305
0306     intel_gmbus_reset(dev_priv);
0307
0308     if (IS_PINEVIEW(dev_priv))
0309         pnv_gmbus_clock_gating(dev_priv, false);
0310
0311     set_data(bus, 1);
0312     set_clock(bus, 1);
0313     udelay(I2C_RISEFALL_TIME);
0314     return 0;
0315 }
0316
0317 static void
0318 intel_gpio_post_xfer(struct i2c_adapter *adapter)
0319 {
0320     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0321     struct drm_i915_private *dev_priv = bus->dev_priv;
0322
0323     set_data(bus, 1);
0324     set_clock(bus, 1);
0325
0326     if (IS_PINEVIEW(dev_priv))
0327         pnv_gmbus_clock_gating(dev_priv, true);
0328 }
0329
0330 static void
0331 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
0332 {
0333     struct i2c_algo_bit_data *algo;
0334
0335     algo = &bus->bit_algo;
0336
0337     bus->gpio_reg = gpio_reg;
0338     bus->adapter.algo_data = algo;
0339     algo->setsda = set_data;
0340     algo->setscl = set_clock;
0341     algo->getsda = get_data;
0342     algo->getscl = get_clock;
0343     algo->pre_xfer = intel_gpio_pre_xfer;
0344     algo->post_xfer = intel_gpio_post_xfer;
0345     algo->udelay = I2C_RISEFALL_TIME;
0346     algo->timeout = usecs_to_jiffies(2200);
0347     algo->data = bus;
0348 }
0349
0350 static bool has_gmbus_irq(struct drm_i915_private *i915)
0351 {
0352     /*
0353      * encoder->shutdown() may want to use GMBUS
0354      * after irqs have already been disabled.
0355      */
0356     return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
0357 }
0358
0359 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
0360 {
0361     DEFINE_WAIT(wait);
0362     u32 gmbus2;
0363     int ret;
0364
0365     /* Important: The hw handles only the first bit, so set only one! Since
0366      * we also need to check for NAKs besides the hw ready/idle signal, we
0367      * need to wake up periodically and check that ourselves.
0368      */
0369     if (!has_gmbus_irq(dev_priv))
0370         irq_en = 0;
0371
0372     add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
0373     intel_de_write_fw(dev_priv, GMBUS4, irq_en);
0374
0375     status |= GMBUS_SATOER;
0376     ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
0377               2);
0378     if (ret)
0379         ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
0380                    50);
0381
0382     intel_de_write_fw(dev_priv, GMBUS4, 0);
0383     remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
0384
0385     if (gmbus2 & GMBUS_SATOER)
0386         return -ENXIO;
0387
0388     return ret;
0389 }
0390
0391 static int
0392 gmbus_wait_idle(struct drm_i915_private *dev_priv)
0393 {
0394     DEFINE_WAIT(wait);
0395     u32 irq_enable;
0396     int ret;
0397
0398     /* Important: The hw handles only the first bit, so set only one! */
0399     irq_enable = 0;
0400     if (has_gmbus_irq(dev_priv))
0401         irq_enable = GMBUS_IDLE_EN;
0402
0403     add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
0404     intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
0405
0406     ret = intel_wait_for_register_fw(&dev_priv->uncore,
0407                      GMBUS2, GMBUS_ACTIVE, 0,
0408                      10);
0409
0410     intel_de_write_fw(dev_priv, GMBUS4, 0);
0411     remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
0412
0413     return ret;
0414 }
0415
0416 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
0417 {
0418     return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
0419            GMBUS_BYTE_COUNT_MAX;
0420 }
0421
0422 static int
0423 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
0424               unsigned short addr, u8 *buf, unsigned int len,
0425               u32 gmbus0_reg, u32 gmbus1_index)
0426 {
0427     unsigned int size = len;
0428     bool burst_read = len > gmbus_max_xfer_size(dev_priv);
0429     bool extra_byte_added = false;
0430
0431     if (burst_read) {
0432         /*
0433          * As per HW Spec, for 512Bytes need to read extra Byte and
0434          * Ignore the extra byte read.
0435          */
0436         if (len == 512) {
0437             extra_byte_added = true;
0438             len++;
0439         }
0440         size = len % 256 + 256;
0441         intel_de_write_fw(dev_priv, GMBUS0,
0442                   gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
0443     }
0444
0445     intel_de_write_fw(dev_priv, GMBUS1,
0446               gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
0447     while (len) {
0448         int ret;
0449         u32 val, loop = 0;
0450
0451         ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
0452         if (ret)
0453             return ret;
0454
0455         val = intel_de_read_fw(dev_priv, GMBUS3);
0456         do {
0457             if (extra_byte_added && len == 1)
0458                 break;
0459
0460             *buf++ = val & 0xff;
0461             val >>= 8;
0462         } while (--len && ++loop < 4);
0463
0464         if (burst_read && len == size - 4)
0465             /* Reset the override bit */
0466             intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
0467     }
0468
0469     return 0;
0470 }
0471
0472 /*
0473  * HW spec says that 512Bytes in Burst read need special treatment.
0474  * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
0475  * an I2C slave, which supports such a lengthy burst read too for experiments.
0476  *
0477  * So until things get clarified on HW support, to avoid the burst read length
0478  * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
0479  */
0480 #define INTEL_GMBUS_BURST_READ_MAX_LEN      767U
0481
0482 static int
0483 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
0484         u32 gmbus0_reg, u32 gmbus1_index)
0485 {
0486     u8 *buf = msg->buf;
0487     unsigned int rx_size = msg->len;
0488     unsigned int len;
0489     int ret;
0490
0491     do {
0492         if (HAS_GMBUS_BURST_READ(dev_priv))
0493             len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
0494         else
0495             len = min(rx_size, gmbus_max_xfer_size(dev_priv));
0496
0497         ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
0498                         gmbus0_reg, gmbus1_index);
0499         if (ret)
0500             return ret;
0501
0502         rx_size -= len;
0503         buf += len;
0504     } while (rx_size != 0);
0505
0506     return 0;
0507 }
0508
0509 static int
0510 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
0511                unsigned short addr, u8 *buf, unsigned int len,
0512                u32 gmbus1_index)
0513 {
0514     unsigned int chunk_size = len;
0515     u32 val, loop;
0516
0517     val = loop = 0;
0518     while (len && loop < 4) {
0519         val |= *buf++ << (8 * loop++);
0520         len -= 1;
0521     }
0522
0523     intel_de_write_fw(dev_priv, GMBUS3, val);
0524     intel_de_write_fw(dev_priv, GMBUS1,
0525               gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
0526     while (len) {
0527         int ret;
0528
0529         val = loop = 0;
0530         do {
0531             val |= *buf++ << (8 * loop);
0532         } while (--len && ++loop < 4);
0533
0534         intel_de_write_fw(dev_priv, GMBUS3, val);
0535
0536         ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
0537         if (ret)
0538             return ret;
0539     }
0540
0541     return 0;
0542 }
0543
0544 static int
0545 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
0546          u32 gmbus1_index)
0547 {
0548     u8 *buf = msg->buf;
0549     unsigned int tx_size = msg->len;
0550     unsigned int len;
0551     int ret;
0552
0553     do {
0554         len = min(tx_size, gmbus_max_xfer_size(dev_priv));
0555
0556         ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
0557                          gmbus1_index);
0558         if (ret)
0559             return ret;
0560
0561         buf += len;
0562         tx_size -= len;
0563     } while (tx_size != 0);
0564
0565     return 0;
0566 }
0567
0568 /*
0569  * The gmbus controller can combine a 1 or 2 byte write with another read/write
0570  * that immediately follows it by using an "INDEX" cycle.
0571  */
0572 static bool
0573 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
0574 {
0575     return (i + 1 < num &&
0576         msgs[i].addr == msgs[i + 1].addr &&
0577         !(msgs[i].flags & I2C_M_RD) &&
0578         (msgs[i].len == 1 || msgs[i].len == 2) &&
0579         msgs[i + 1].len > 0);
0580 }
0581
0582 static int
0583 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
0584          u32 gmbus0_reg)
0585 {
0586     u32 gmbus1_index = 0;
0587     u32 gmbus5 = 0;
0588     int ret;
0589
0590     if (msgs[0].len == 2)
0591         gmbus5 = GMBUS_2BYTE_INDEX_EN |
0592              msgs[0].buf[1] | (msgs[0].buf[0] << 8);
0593     if (msgs[0].len == 1)
0594         gmbus1_index = GMBUS_CYCLE_INDEX |
0595                    (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
0596
0597     /* GMBUS5 holds 16-bit index */
0598     if (gmbus5)
0599         intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
0600
0601     if (msgs[1].flags & I2C_M_RD)
0602         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
0603                       gmbus1_index);
0604     else
0605         ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
0606
0607     /* Clear GMBUS5 after each index transfer */
0608     if (gmbus5)
0609         intel_de_write_fw(dev_priv, GMBUS5, 0);
0610
0611     return ret;
0612 }
0613
0614 static int
0615 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
0616           u32 gmbus0_source)
0617 {
0618     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0619     struct drm_i915_private *dev_priv = bus->dev_priv;
0620     int i = 0, inc, try = 0;
0621     int ret = 0;
0622
0623     /* Display WA #0868: skl,bxt,kbl,cfl,glk */
0624     if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
0625         bxt_gmbus_clock_gating(dev_priv, false);
0626     else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
0627         pch_gmbus_clock_gating(dev_priv, false);
0628
0629 retry:
0630     intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
0631
0632     for (; i < num; i += inc) {
0633         inc = 1;
0634         if (gmbus_is_index_xfer(msgs, i, num)) {
0635             ret = gmbus_index_xfer(dev_priv, &msgs[i],
0636                            gmbus0_source | bus->reg0);
0637             inc = 2; /* an index transmission is two msgs */
0638         } else if (msgs[i].flags & I2C_M_RD) {
0639             ret = gmbus_xfer_read(dev_priv, &msgs[i],
0640                           gmbus0_source | bus->reg0, 0);
0641         } else {
0642             ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
0643         }
0644
0645         if (!ret)
0646             ret = gmbus_wait(dev_priv,
0647                      GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
0648         if (ret == -ETIMEDOUT)
0649             goto timeout;
0650         else if (ret)
0651             goto clear_err;
0652     }
0653
0654     /* Generate a STOP condition on the bus. Note that gmbus can't generata
0655      * a STOP on the very first cycle. To simplify the code we
0656      * unconditionally generate the STOP condition with an additional gmbus
0657      * cycle. */
0658     intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
0659
0660     /* Mark the GMBUS interface as disabled after waiting for idle.
0661      * We will re-enable it at the start of the next xfer,
0662      * till then let it sleep.
0663      */
0664     if (gmbus_wait_idle(dev_priv)) {
0665         drm_dbg_kms(&dev_priv->drm,
0666                 "GMBUS [%s] timed out waiting for idle\n",
0667                 adapter->name);
0668         ret = -ETIMEDOUT;
0669     }
0670     intel_de_write_fw(dev_priv, GMBUS0, 0);
0671     ret = ret ?: i;
0672     goto out;
0673
0674 clear_err:
0675     /*
0676      * Wait for bus to IDLE before clearing NAK.
0677      * If we clear the NAK while bus is still active, then it will stay
0678      * active and the next transaction may fail.
0679      *
0680      * If no ACK is received during the address phase of a transaction, the
0681      * adapter must report -ENXIO. It is not clear what to return if no ACK
0682      * is received at other times. But we have to be careful to not return
0683      * spurious -ENXIO because that will prevent i2c and drm edid functions
0684      * from retrying. So return -ENXIO only when gmbus properly quiescents -
0685      * timing out seems to happen when there _is_ a ddc chip present, but
0686      * it's slow responding and only answers on the 2nd retry.
0687      */
0688     ret = -ENXIO;
0689     if (gmbus_wait_idle(dev_priv)) {
0690         drm_dbg_kms(&dev_priv->drm,
0691                 "GMBUS [%s] timed out after NAK\n",
0692                 adapter->name);
0693         ret = -ETIMEDOUT;
0694     }
0695
0696     /* Toggle the Software Clear Interrupt bit. This has the effect
0697      * of resetting the GMBUS controller and so clearing the
0698      * BUS_ERROR raised by the slave's NAK.
0699      */
0700     intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
0701     intel_de_write_fw(dev_priv, GMBUS1, 0);
0702     intel_de_write_fw(dev_priv, GMBUS0, 0);
0703
0704     drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
0705             adapter->name, msgs[i].addr,
0706             (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
0707
0708     /*
0709      * Passive adapters sometimes NAK the first probe. Retry the first
0710      * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
0711      * has retries internally. See also the retry loop in
0712      * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
0713      */
0714     if (ret == -ENXIO && i == 0 && try++ == 0) {
0715         drm_dbg_kms(&dev_priv->drm,
0716                 "GMBUS [%s] NAK on first message, retry\n",
0717                 adapter->name);
0718         goto retry;
0719     }
0720
0721     goto out;
0722
0723 timeout:
0724     drm_dbg_kms(&dev_priv->drm,
0725             "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
0726             bus->adapter.name, bus->reg0 & 0xff);
0727     intel_de_write_fw(dev_priv, GMBUS0, 0);
0728
0729     /*
0730      * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
0731      * instead. Use EAGAIN to have i2c core retry.
0732      */
0733     ret = -EAGAIN;
0734
0735 out:
0736     /* Display WA #0868: skl,bxt,kbl,cfl,glk */
0737     if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
0738         bxt_gmbus_clock_gating(dev_priv, true);
0739     else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
0740         pch_gmbus_clock_gating(dev_priv, true);
0741
0742     return ret;
0743 }
0744
0745 static int
0746 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
0747 {
0748     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0749     struct drm_i915_private *dev_priv = bus->dev_priv;
0750     intel_wakeref_t wakeref;
0751     int ret;
0752
0753     wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
0754
0755     if (bus->force_bit) {
0756         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
0757         if (ret < 0)
0758             bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
0759     } else {
0760         ret = do_gmbus_xfer(adapter, msgs, num, 0);
0761         if (ret == -EAGAIN)
0762             bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
0763     }
0764
0765     intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
0766
0767     return ret;
0768 }
0769
0770 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
0771 {
0772     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0773     struct drm_i915_private *dev_priv = bus->dev_priv;
0774     u8 cmd = DRM_HDCP_DDC_AKSV;
0775     u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
0776     struct i2c_msg msgs[] = {
0777         {
0778             .addr = DRM_HDCP_DDC_ADDR,
0779             .flags = 0,
0780             .len = sizeof(cmd),
0781             .buf = &cmd,
0782         },
0783         {
0784             .addr = DRM_HDCP_DDC_ADDR,
0785             .flags = 0,
0786             .len = sizeof(buf),
0787             .buf = buf,
0788         }
0789     };
0790     intel_wakeref_t wakeref;
0791     int ret;
0792
0793     wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
0794     mutex_lock(&dev_priv->gmbus_mutex);
0795
0796     /*
0797      * In order to output Aksv to the receiver, use an indexed write to
0798      * pass the i2c command, and tell GMBUS to use the HW-provided value
0799      * instead of sourcing GMBUS3 for the data.
0800      */
0801     ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
0802
0803     mutex_unlock(&dev_priv->gmbus_mutex);
0804     intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
0805
0806     return ret;
0807 }
0808
0809 static u32 gmbus_func(struct i2c_adapter *adapter)
0810 {
0811     return i2c_bit_algo.functionality(adapter) &
0812         (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
0813         /* I2C_FUNC_10BIT_ADDR | */
0814         I2C_FUNC_SMBUS_READ_BLOCK_DATA |
0815         I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
0816 }
0817
0818 static const struct i2c_algorithm gmbus_algorithm = {
0819     .master_xfer    = gmbus_xfer,
0820     .functionality  = gmbus_func
0821 };
0822
0823 static void gmbus_lock_bus(struct i2c_adapter *adapter,
0824                unsigned int flags)
0825 {
0826     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0827     struct drm_i915_private *dev_priv = bus->dev_priv;
0828
0829     mutex_lock(&dev_priv->gmbus_mutex);
0830 }
0831
0832 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
0833                  unsigned int flags)
0834 {
0835     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0836     struct drm_i915_private *dev_priv = bus->dev_priv;
0837
0838     return mutex_trylock(&dev_priv->gmbus_mutex);
0839 }
0840
0841 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
0842                  unsigned int flags)
0843 {
0844     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0845     struct drm_i915_private *dev_priv = bus->dev_priv;
0846
0847     mutex_unlock(&dev_priv->gmbus_mutex);
0848 }
0849
0850 static const struct i2c_lock_operations gmbus_lock_ops = {
0851     .lock_bus =    gmbus_lock_bus,
0852     .trylock_bus = gmbus_trylock_bus,
0853     .unlock_bus =  gmbus_unlock_bus,
0854 };
0855
0856 /**
0857  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
0858  * @dev_priv: i915 device private
0859  */
0860 int intel_gmbus_setup(struct drm_i915_private *dev_priv)
0861 {
0862     struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
0863     unsigned int pin;
0864     int ret;
0865
0866     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0867         dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
0868     else if (!HAS_GMCH(dev_priv))
0869         /*
0870          * Broxton uses the same PCH offsets for South Display Engine,
0871          * even though it doesn't have a PCH.
0872          */
0873         dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
0874
0875     mutex_init(&dev_priv->gmbus_mutex);
0876     init_waitqueue_head(&dev_priv->gmbus_wait_queue);
0877
0878     for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
0879         const struct gmbus_pin *gmbus_pin;
0880         struct intel_gmbus *bus;
0881
0882         gmbus_pin = get_gmbus_pin(dev_priv, pin);
0883         if (!gmbus_pin)
0884             continue;
0885
0886         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
0887         if (!bus) {
0888             ret = -ENOMEM;
0889             goto err;
0890         }
0891
0892         bus->adapter.owner = THIS_MODULE;
0893         bus->adapter.class = I2C_CLASS_DDC;
0894         snprintf(bus->adapter.name,
0895              sizeof(bus->adapter.name),
0896              "i915 gmbus %s", gmbus_pin->name);
0897
0898         bus->adapter.dev.parent = &pdev->dev;
0899         bus->dev_priv = dev_priv;
0900
0901         bus->adapter.algo = &gmbus_algorithm;
0902         bus->adapter.lock_ops = &gmbus_lock_ops;
0903
0904         /*
0905          * We wish to retry with bit banging
0906          * after a timed out GMBUS attempt.
0907          */
0908         bus->adapter.retries = 1;
0909
0910         /* By default use a conservative clock rate */
0911         bus->reg0 = pin | GMBUS_RATE_100KHZ;
0912
0913         /* gmbus seems to be broken on i830 */
0914         if (IS_I830(dev_priv))
0915             bus->force_bit = 1;
0916
0917         intel_gpio_setup(bus, GPIO(gmbus_pin->gpio));
0918
0919         ret = i2c_add_adapter(&bus->adapter);
0920         if (ret) {
0921             kfree(bus);
0922             goto err;
0923         }
0924
0925         dev_priv->gmbus[pin] = bus;
0926     }
0927
0928     intel_gmbus_reset(dev_priv);
0929
0930     return 0;
0931
0932 err:
0933     intel_gmbus_teardown(dev_priv);
0934
0935     return ret;
0936 }
0937
0938 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
0939                         unsigned int pin)
0940 {
0941     if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->gmbus) ||
0942             !dev_priv->gmbus[pin]))
0943         return NULL;
0944
0945     return &dev_priv->gmbus[pin]->adapter;
0946 }
0947
0948 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
0949 {
0950     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0951     struct drm_i915_private *dev_priv = bus->dev_priv;
0952
0953     mutex_lock(&dev_priv->gmbus_mutex);
0954
0955     bus->force_bit += force_bit ? 1 : -1;
0956     drm_dbg_kms(&dev_priv->drm,
0957             "%sabling bit-banging on %s. force bit now %d\n",
0958             force_bit ? "en" : "dis", adapter->name,
0959             bus->force_bit);
0960
0961     mutex_unlock(&dev_priv->gmbus_mutex);
0962 }
0963
0964 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
0965 {
0966     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0967
0968     return bus->force_bit;
0969 }
0970
0971 void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
0972 {
0973     unsigned int pin;
0974
0975     for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
0976         struct intel_gmbus *bus;
0977
0978         bus = dev_priv->gmbus[pin];
0979         if (!bus)
0980             continue;
0981
0982         i2c_del_adapter(&bus->adapter);
0983
0984         kfree(bus);
0985         dev_priv->gmbus[pin] = NULL;
0986     }
0987 }