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0001 /*
0002  * Copyright © 2014 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0021  * DEALINGS IN THE SOFTWARE.
0022  *
0023  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
0024  *
0025  */
0026 
0027 #include <linux/gpio/consumer.h>
0028 #include <linux/gpio/machine.h>
0029 #include <linux/mfd/intel_soc_pmic.h>
0030 #include <linux/pinctrl/consumer.h>
0031 #include <linux/pinctrl/machine.h>
0032 #include <linux/slab.h>
0033 #include <linux/string_helpers.h>
0034 
0035 #include <asm/unaligned.h>
0036 
0037 #include <drm/drm_crtc.h>
0038 #include <drm/drm_edid.h>
0039 
0040 #include <video/mipi_display.h>
0041 
0042 #include "i915_drv.h"
0043 #include "i915_reg.h"
0044 #include "intel_display_types.h"
0045 #include "intel_dsi.h"
0046 #include "intel_dsi_vbt.h"
0047 #include "vlv_dsi.h"
0048 #include "vlv_dsi_regs.h"
0049 #include "vlv_sideband.h"
0050 
0051 #define MIPI_TRANSFER_MODE_SHIFT    0
0052 #define MIPI_VIRTUAL_CHANNEL_SHIFT  1
0053 #define MIPI_PORT_SHIFT         3
0054 
0055 /* base offsets for gpio pads */
0056 #define VLV_GPIO_NC_0_HV_DDI0_HPD   0x4130
0057 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
0058 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
0059 #define VLV_GPIO_NC_3_PANEL0_VDDEN  0x4140
0060 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
0061 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL    0x4160
0062 #define VLV_GPIO_NC_6_HV_DDI1_HPD   0x4180
0063 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA   0x4190
0064 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL   0x4170
0065 #define VLV_GPIO_NC_9_PANEL1_VDDEN  0x4100
0066 #define VLV_GPIO_NC_10_PANEL1_BKLTEN    0x40E0
0067 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL   0x40F0
0068 
0069 #define VLV_GPIO_PCONF0(base_offset)    (base_offset)
0070 #define VLV_GPIO_PAD_VAL(base_offset)   ((base_offset) + 8)
0071 
0072 struct gpio_map {
0073     u16 base_offset;
0074     bool init;
0075 };
0076 
0077 static struct gpio_map vlv_gpio_table[] = {
0078     { VLV_GPIO_NC_0_HV_DDI0_HPD },
0079     { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
0080     { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
0081     { VLV_GPIO_NC_3_PANEL0_VDDEN },
0082     { VLV_GPIO_NC_4_PANEL0_BKLTEN },
0083     { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
0084     { VLV_GPIO_NC_6_HV_DDI1_HPD },
0085     { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
0086     { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
0087     { VLV_GPIO_NC_9_PANEL1_VDDEN },
0088     { VLV_GPIO_NC_10_PANEL1_BKLTEN },
0089     { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
0090 };
0091 
0092 struct i2c_adapter_lookup {
0093     u16 slave_addr;
0094     struct intel_dsi *intel_dsi;
0095     acpi_handle dev_handle;
0096 };
0097 
0098 #define CHV_GPIO_IDX_START_N        0
0099 #define CHV_GPIO_IDX_START_E        73
0100 #define CHV_GPIO_IDX_START_SW       100
0101 #define CHV_GPIO_IDX_START_SE       198
0102 
0103 #define CHV_VBT_MAX_PINS_PER_FMLY   15
0104 
0105 #define CHV_GPIO_PAD_CFG0(f, i)     (0x4400 + (f) * 0x400 + (i) * 8)
0106 #define  CHV_GPIO_GPIOEN        (1 << 15)
0107 #define  CHV_GPIO_GPIOCFG_GPIO      (0 << 8)
0108 #define  CHV_GPIO_GPIOCFG_GPO       (1 << 8)
0109 #define  CHV_GPIO_GPIOCFG_GPI       (2 << 8)
0110 #define  CHV_GPIO_GPIOCFG_HIZ       (3 << 8)
0111 #define  CHV_GPIO_GPIOTXSTATE(state)    ((!!(state)) << 1)
0112 
0113 #define CHV_GPIO_PAD_CFG1(f, i)     (0x4400 + (f) * 0x400 + (i) * 8 + 4)
0114 #define  CHV_GPIO_CFGLOCK       (1 << 31)
0115 
0116 /* ICL DSI Display GPIO Pins */
0117 #define  ICL_GPIO_DDSP_HPD_A        0
0118 #define  ICL_GPIO_L_VDDEN_1     1
0119 #define  ICL_GPIO_L_BKLTEN_1        2
0120 #define  ICL_GPIO_DDPA_CTRLCLK_1    3
0121 #define  ICL_GPIO_DDPA_CTRLDATA_1   4
0122 #define  ICL_GPIO_DDSP_HPD_B        5
0123 #define  ICL_GPIO_L_VDDEN_2     6
0124 #define  ICL_GPIO_L_BKLTEN_2        7
0125 #define  ICL_GPIO_DDPA_CTRLCLK_2    8
0126 #define  ICL_GPIO_DDPA_CTRLDATA_2   9
0127 
0128 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
0129                         u8 seq_port)
0130 {
0131     /*
0132      * If single link DSI is being used on any port, the VBT sequence block
0133      * send packet apparently always has 0 for the port. Just use the port
0134      * we have configured, and ignore the sequence block port.
0135      */
0136     if (hweight8(intel_dsi->ports) == 1)
0137         return ffs(intel_dsi->ports) - 1;
0138 
0139     if (seq_port) {
0140         if (intel_dsi->ports & PORT_B)
0141             return PORT_B;
0142         else if (intel_dsi->ports & PORT_C)
0143             return PORT_C;
0144     }
0145 
0146     return PORT_A;
0147 }
0148 
0149 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
0150                        const u8 *data)
0151 {
0152     struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
0153     struct mipi_dsi_device *dsi_device;
0154     u8 type, flags, seq_port;
0155     u16 len;
0156     enum port port;
0157 
0158     drm_dbg_kms(&dev_priv->drm, "\n");
0159 
0160     flags = *data++;
0161     type = *data++;
0162 
0163     len = *((u16 *) data);
0164     data += 2;
0165 
0166     seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
0167 
0168     port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
0169 
0170     if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
0171         goto out;
0172 
0173     dsi_device = intel_dsi->dsi_hosts[port]->device;
0174     if (!dsi_device) {
0175         drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
0176                 port_name(port));
0177         goto out;
0178     }
0179 
0180     if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
0181         dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
0182     else
0183         dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
0184 
0185     dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
0186 
0187     switch (type) {
0188     case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
0189         mipi_dsi_generic_write(dsi_device, NULL, 0);
0190         break;
0191     case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
0192         mipi_dsi_generic_write(dsi_device, data, 1);
0193         break;
0194     case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
0195         mipi_dsi_generic_write(dsi_device, data, 2);
0196         break;
0197     case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
0198     case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
0199     case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
0200         drm_dbg(&dev_priv->drm,
0201             "Generic Read not yet implemented or used\n");
0202         break;
0203     case MIPI_DSI_GENERIC_LONG_WRITE:
0204         mipi_dsi_generic_write(dsi_device, data, len);
0205         break;
0206     case MIPI_DSI_DCS_SHORT_WRITE:
0207         mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
0208         break;
0209     case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
0210         mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
0211         break;
0212     case MIPI_DSI_DCS_READ:
0213         drm_dbg(&dev_priv->drm,
0214             "DCS Read not yet implemented or used\n");
0215         break;
0216     case MIPI_DSI_DCS_LONG_WRITE:
0217         mipi_dsi_dcs_write_buffer(dsi_device, data, len);
0218         break;
0219     }
0220 
0221     if (DISPLAY_VER(dev_priv) < 11)
0222         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
0223 
0224 out:
0225     data += len;
0226 
0227     return data;
0228 }
0229 
0230 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
0231 {
0232     struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
0233     u32 delay = *((const u32 *) data);
0234 
0235     drm_dbg_kms(&i915->drm, "\n");
0236 
0237     usleep_range(delay, delay + 10);
0238     data += 4;
0239 
0240     return data;
0241 }
0242 
0243 static void vlv_exec_gpio(struct intel_connector *connector,
0244               u8 gpio_source, u8 gpio_index, bool value)
0245 {
0246     struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0247     struct gpio_map *map;
0248     u16 pconf0, padval;
0249     u32 tmp;
0250     u8 port;
0251 
0252     if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
0253         drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",
0254                 gpio_index);
0255         return;
0256     }
0257 
0258     map = &vlv_gpio_table[gpio_index];
0259 
0260     if (connector->panel.vbt.dsi.seq_version >= 3) {
0261         /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
0262         port = IOSF_PORT_GPIO_NC;
0263     } else {
0264         if (gpio_source == 0) {
0265             port = IOSF_PORT_GPIO_NC;
0266         } else if (gpio_source == 1) {
0267             drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
0268             return;
0269         } else {
0270             drm_dbg_kms(&dev_priv->drm,
0271                     "unknown gpio source %u\n", gpio_source);
0272             return;
0273         }
0274     }
0275 
0276     pconf0 = VLV_GPIO_PCONF0(map->base_offset);
0277     padval = VLV_GPIO_PAD_VAL(map->base_offset);
0278 
0279     vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
0280     if (!map->init) {
0281         /* FIXME: remove constant below */
0282         vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
0283         map->init = true;
0284     }
0285 
0286     tmp = 0x4 | value;
0287     vlv_iosf_sb_write(dev_priv, port, padval, tmp);
0288     vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
0289 }
0290 
0291 static void chv_exec_gpio(struct intel_connector *connector,
0292               u8 gpio_source, u8 gpio_index, bool value)
0293 {
0294     struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0295     u16 cfg0, cfg1;
0296     u16 family_num;
0297     u8 port;
0298 
0299     if (connector->panel.vbt.dsi.seq_version >= 3) {
0300         if (gpio_index >= CHV_GPIO_IDX_START_SE) {
0301             /* XXX: it's unclear whether 255->57 is part of SE. */
0302             gpio_index -= CHV_GPIO_IDX_START_SE;
0303             port = CHV_IOSF_PORT_GPIO_SE;
0304         } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
0305             gpio_index -= CHV_GPIO_IDX_START_SW;
0306             port = CHV_IOSF_PORT_GPIO_SW;
0307         } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
0308             gpio_index -= CHV_GPIO_IDX_START_E;
0309             port = CHV_IOSF_PORT_GPIO_E;
0310         } else {
0311             port = CHV_IOSF_PORT_GPIO_N;
0312         }
0313     } else {
0314         /* XXX: The spec is unclear about CHV GPIO on seq v2 */
0315         if (gpio_source != 0) {
0316             drm_dbg_kms(&dev_priv->drm,
0317                     "unknown gpio source %u\n", gpio_source);
0318             return;
0319         }
0320 
0321         if (gpio_index >= CHV_GPIO_IDX_START_E) {
0322             drm_dbg_kms(&dev_priv->drm,
0323                     "invalid gpio index %u for GPIO N\n",
0324                     gpio_index);
0325             return;
0326         }
0327 
0328         port = CHV_IOSF_PORT_GPIO_N;
0329     }
0330 
0331     family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
0332     gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
0333 
0334     cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
0335     cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
0336 
0337     vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
0338     vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
0339     vlv_iosf_sb_write(dev_priv, port, cfg0,
0340               CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
0341               CHV_GPIO_GPIOTXSTATE(value));
0342     vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
0343 }
0344 
0345 static void bxt_exec_gpio(struct intel_connector *connector,
0346               u8 gpio_source, u8 gpio_index, bool value)
0347 {
0348     struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0349     /* XXX: this table is a quick ugly hack. */
0350     static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
0351     struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
0352 
0353     if (!gpio_desc) {
0354         gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
0355                          NULL, gpio_index,
0356                          value ? GPIOD_OUT_LOW :
0357                          GPIOD_OUT_HIGH);
0358 
0359         if (IS_ERR_OR_NULL(gpio_desc)) {
0360             drm_err(&dev_priv->drm,
0361                 "GPIO index %u request failed (%ld)\n",
0362                 gpio_index, PTR_ERR(gpio_desc));
0363             return;
0364         }
0365 
0366         bxt_gpio_table[gpio_index] = gpio_desc;
0367     }
0368 
0369     gpiod_set_value(gpio_desc, value);
0370 }
0371 
0372 static void icl_exec_gpio(struct intel_connector *connector,
0373               u8 gpio_source, u8 gpio_index, bool value)
0374 {
0375     struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0376 
0377     drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
0378 }
0379 
0380 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
0381 {
0382     struct drm_device *dev = intel_dsi->base.base.dev;
0383     struct drm_i915_private *dev_priv = to_i915(dev);
0384     struct intel_connector *connector = intel_dsi->attached_connector;
0385     u8 gpio_source, gpio_index = 0, gpio_number;
0386     bool value;
0387 
0388     drm_dbg_kms(&dev_priv->drm, "\n");
0389 
0390     if (connector->panel.vbt.dsi.seq_version >= 3)
0391         gpio_index = *data++;
0392 
0393     gpio_number = *data++;
0394 
0395     /* gpio source in sequence v2 only */
0396     if (connector->panel.vbt.dsi.seq_version == 2)
0397         gpio_source = (*data >> 1) & 3;
0398     else
0399         gpio_source = 0;
0400 
0401     /* pull up/down */
0402     value = *data++ & 1;
0403 
0404     if (DISPLAY_VER(dev_priv) >= 11)
0405         icl_exec_gpio(connector, gpio_source, gpio_index, value);
0406     else if (IS_VALLEYVIEW(dev_priv))
0407         vlv_exec_gpio(connector, gpio_source, gpio_number, value);
0408     else if (IS_CHERRYVIEW(dev_priv))
0409         chv_exec_gpio(connector, gpio_source, gpio_number, value);
0410     else
0411         bxt_exec_gpio(connector, gpio_source, gpio_index, value);
0412 
0413     return data;
0414 }
0415 
0416 #ifdef CONFIG_ACPI
0417 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
0418 {
0419     struct i2c_adapter_lookup *lookup = data;
0420     struct intel_dsi *intel_dsi = lookup->intel_dsi;
0421     struct acpi_resource_i2c_serialbus *sb;
0422     struct i2c_adapter *adapter;
0423     acpi_handle adapter_handle;
0424     acpi_status status;
0425 
0426     if (!i2c_acpi_get_i2c_resource(ares, &sb))
0427         return 1;
0428 
0429     if (lookup->slave_addr != sb->slave_address)
0430         return 1;
0431 
0432     status = acpi_get_handle(lookup->dev_handle,
0433                  sb->resource_source.string_ptr,
0434                  &adapter_handle);
0435     if (ACPI_FAILURE(status))
0436         return 1;
0437 
0438     adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
0439     if (adapter)
0440         intel_dsi->i2c_bus_num = adapter->nr;
0441 
0442     return 1;
0443 }
0444 
0445 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
0446                   const u16 slave_addr)
0447 {
0448     struct drm_device *drm_dev = intel_dsi->base.base.dev;
0449     struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
0450     struct i2c_adapter_lookup lookup = {
0451         .slave_addr = slave_addr,
0452         .intel_dsi = intel_dsi,
0453         .dev_handle = acpi_device_handle(adev),
0454     };
0455     LIST_HEAD(resource_list);
0456 
0457     acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
0458     acpi_dev_free_resource_list(&resource_list);
0459 }
0460 #else
0461 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
0462                      const u16 slave_addr)
0463 {
0464 }
0465 #endif
0466 
0467 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
0468 {
0469     struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
0470     struct i2c_adapter *adapter;
0471     struct i2c_msg msg;
0472     int ret;
0473     u8 vbt_i2c_bus_num = *(data + 2);
0474     u16 slave_addr = *(u16 *)(data + 3);
0475     u8 reg_offset = *(data + 5);
0476     u8 payload_size = *(data + 6);
0477     u8 *payload_data;
0478 
0479     if (intel_dsi->i2c_bus_num < 0) {
0480         intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
0481         i2c_acpi_find_adapter(intel_dsi, slave_addr);
0482     }
0483 
0484     adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
0485     if (!adapter) {
0486         drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n");
0487         goto err_bus;
0488     }
0489 
0490     payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
0491     if (!payload_data)
0492         goto err_alloc;
0493 
0494     payload_data[0] = reg_offset;
0495     memcpy(&payload_data[1], (data + 7), payload_size);
0496 
0497     msg.addr = slave_addr;
0498     msg.flags = 0;
0499     msg.len = payload_size + 1;
0500     msg.buf = payload_data;
0501 
0502     ret = i2c_transfer(adapter, &msg, 1);
0503     if (ret < 0)
0504         drm_err(&i915->drm,
0505             "Failed to xfer payload of size (%u) to reg (%u)\n",
0506             payload_size, reg_offset);
0507 
0508     kfree(payload_data);
0509 err_alloc:
0510     i2c_put_adapter(adapter);
0511 err_bus:
0512     return data + payload_size + 7;
0513 }
0514 
0515 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
0516 {
0517     struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
0518 
0519     drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
0520 
0521     return data + *(data + 5) + 6;
0522 }
0523 
0524 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
0525 {
0526     struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
0527 #ifdef CONFIG_PMIC_OPREGION
0528     u32 value, mask, reg_address;
0529     u16 i2c_address;
0530     int ret;
0531 
0532     /* byte 0 aka PMIC Flag is reserved */
0533     i2c_address = get_unaligned_le16(data + 1);
0534     reg_address = get_unaligned_le32(data + 3);
0535     value       = get_unaligned_le32(data + 7);
0536     mask        = get_unaligned_le32(data + 11);
0537 
0538     ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
0539                             reg_address,
0540                             value, mask);
0541     if (ret)
0542         drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
0543 #else
0544     drm_err(&i915->drm,
0545         "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
0546 #endif
0547 
0548     return data + 15;
0549 }
0550 
0551 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
0552                     const u8 *data);
0553 static const fn_mipi_elem_exec exec_elem[] = {
0554     [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
0555     [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
0556     [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
0557     [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
0558     [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
0559     [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
0560 };
0561 
0562 /*
0563  * MIPI Sequence from VBT #53 parsing logic
0564  * We have already separated each seqence during bios parsing
0565  * Following is generic execution function for any sequence
0566  */
0567 
0568 static const char * const seq_name[] = {
0569     [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
0570     [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
0571     [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
0572     [MIPI_SEQ_DISPLAY_OFF]  = "MIPI_SEQ_DISPLAY_OFF",
0573     [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
0574     [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
0575     [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
0576     [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
0577     [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
0578     [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
0579     [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
0580 };
0581 
0582 static const char *sequence_name(enum mipi_seq seq_id)
0583 {
0584     if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
0585         return seq_name[seq_id];
0586     else
0587         return "(unknown)";
0588 }
0589 
0590 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
0591                    enum mipi_seq seq_id)
0592 {
0593     struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
0594     struct intel_connector *connector = intel_dsi->attached_connector;
0595     const u8 *data;
0596     fn_mipi_elem_exec mipi_elem_exec;
0597 
0598     if (drm_WARN_ON(&dev_priv->drm,
0599             seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence)))
0600         return;
0601 
0602     data = connector->panel.vbt.dsi.sequence[seq_id];
0603     if (!data)
0604         return;
0605 
0606     drm_WARN_ON(&dev_priv->drm, *data != seq_id);
0607 
0608     drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
0609             seq_id, sequence_name(seq_id));
0610 
0611     /* Skip Sequence Byte. */
0612     data++;
0613 
0614     /* Skip Size of Sequence. */
0615     if (connector->panel.vbt.dsi.seq_version >= 3)
0616         data += 4;
0617 
0618     while (1) {
0619         u8 operation_byte = *data++;
0620         u8 operation_size = 0;
0621 
0622         if (operation_byte == MIPI_SEQ_ELEM_END)
0623             break;
0624 
0625         if (operation_byte < ARRAY_SIZE(exec_elem))
0626             mipi_elem_exec = exec_elem[operation_byte];
0627         else
0628             mipi_elem_exec = NULL;
0629 
0630         /* Size of Operation. */
0631         if (connector->panel.vbt.dsi.seq_version >= 3)
0632             operation_size = *data++;
0633 
0634         if (mipi_elem_exec) {
0635             const u8 *next = data + operation_size;
0636 
0637             data = mipi_elem_exec(intel_dsi, data);
0638 
0639             /* Consistency check if we have size. */
0640             if (operation_size && data != next) {
0641                 drm_err(&dev_priv->drm,
0642                     "Inconsistent operation size\n");
0643                 return;
0644             }
0645         } else if (operation_size) {
0646             /* We have size, skip. */
0647             drm_dbg_kms(&dev_priv->drm,
0648                     "Unsupported MIPI operation byte %u\n",
0649                     operation_byte);
0650             data += operation_size;
0651         } else {
0652             /* No size, can't skip without parsing. */
0653             drm_err(&dev_priv->drm,
0654                 "Unsupported MIPI operation byte %u\n",
0655                 operation_byte);
0656             return;
0657         }
0658     }
0659 }
0660 
0661 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
0662                  enum mipi_seq seq_id)
0663 {
0664     if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
0665         gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
0666     if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
0667         gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
0668 
0669     intel_dsi_vbt_exec(intel_dsi, seq_id);
0670 
0671     if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
0672         gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
0673     if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
0674         gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
0675 }
0676 
0677 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
0678 {
0679     struct intel_connector *connector = intel_dsi->attached_connector;
0680 
0681     /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
0682     if (is_vid_mode(intel_dsi) && connector->panel.vbt.dsi.seq_version >= 3)
0683         return;
0684 
0685     msleep(msec);
0686 }
0687 
0688 void intel_dsi_log_params(struct intel_dsi *intel_dsi)
0689 {
0690     struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
0691 
0692     drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
0693     drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
0694             intel_dsi->pixel_overlap);
0695     drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
0696     drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
0697     drm_dbg_kms(&i915->drm, "Video mode format %s\n",
0698             intel_dsi->video_mode == NON_BURST_SYNC_PULSE ?
0699             "non-burst with sync pulse" :
0700             intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ?
0701             "non-burst with sync events" :
0702             intel_dsi->video_mode == BURST_MODE ?
0703             "burst" : "<unknown>");
0704     drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
0705             intel_dsi->burst_mode_ratio);
0706     drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
0707     drm_dbg_kms(&i915->drm, "Eot %s\n",
0708             str_enabled_disabled(intel_dsi->eotp_pkt));
0709     drm_dbg_kms(&i915->drm, "Clockstop %s\n",
0710             str_enabled_disabled(!intel_dsi->clock_stop));
0711     drm_dbg_kms(&i915->drm, "Mode %s\n",
0712             intel_dsi->operation_mode ? "command" : "video");
0713     if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
0714         drm_dbg_kms(&i915->drm,
0715                 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
0716     else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
0717         drm_dbg_kms(&i915->drm,
0718                 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
0719     else
0720         drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
0721     drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
0722     drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
0723     drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
0724             intel_dsi->lp_rx_timeout);
0725     drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
0726             intel_dsi->turn_arnd_val);
0727     drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
0728     drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
0729             intel_dsi->hs_to_lp_count);
0730     drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
0731     drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
0732     drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
0733             intel_dsi->clk_lp_to_hs_count);
0734     drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
0735             intel_dsi->clk_hs_to_lp_count);
0736     drm_dbg_kms(&i915->drm, "BTA %s\n",
0737             str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
0738 }
0739 
0740 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
0741 {
0742     struct drm_device *dev = intel_dsi->base.base.dev;
0743     struct drm_i915_private *dev_priv = to_i915(dev);
0744     struct intel_connector *connector = intel_dsi->attached_connector;
0745     struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
0746     struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;
0747     struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode;
0748     u16 burst_mode_ratio;
0749     enum port port;
0750 
0751     drm_dbg_kms(&dev_priv->drm, "\n");
0752 
0753     intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
0754     intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
0755     intel_dsi->lane_count = mipi_config->lane_cnt + 1;
0756     intel_dsi->pixel_format =
0757             pixel_format_from_register_bits(
0758                 mipi_config->videomode_color_format << 7);
0759 
0760     intel_dsi->dual_link = mipi_config->dual_link;
0761     intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
0762     intel_dsi->operation_mode = mipi_config->is_cmd_mode;
0763     intel_dsi->video_mode = mipi_config->video_transfer_mode;
0764     intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
0765     intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
0766     intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
0767     intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
0768     intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
0769     intel_dsi->init_count = mipi_config->master_init_timer;
0770     intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
0771     intel_dsi->video_frmt_cfg_bits =
0772         mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
0773     intel_dsi->bgr_enabled = mipi_config->rgb_flip;
0774 
0775     /* Starting point, adjusted depending on dual link and burst mode */
0776     intel_dsi->pclk = mode->clock;
0777 
0778     /* In dual link mode each port needs half of pixel clock */
0779     if (intel_dsi->dual_link) {
0780         intel_dsi->pclk /= 2;
0781 
0782         /* we can enable pixel_overlap if needed by panel. In this
0783          * case we need to increase the pixelclock for extra pixels
0784          */
0785         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
0786             intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
0787         }
0788     }
0789 
0790     /* Burst Mode Ratio
0791      * Target ddr frequency from VBT / non burst ddr freq
0792      * multiply by 100 to preserve remainder
0793      */
0794     if (intel_dsi->video_mode == BURST_MODE) {
0795         if (mipi_config->target_burst_mode_freq) {
0796             u32 bitrate = intel_dsi_bitrate(intel_dsi);
0797 
0798             /*
0799              * Sometimes the VBT contains a slightly lower clock,
0800              * then the bitrate we have calculated, in this case
0801              * just replace it with the calculated bitrate.
0802              */
0803             if (mipi_config->target_burst_mode_freq < bitrate &&
0804                 intel_fuzzy_clock_check(
0805                     mipi_config->target_burst_mode_freq,
0806                     bitrate))
0807                 mipi_config->target_burst_mode_freq = bitrate;
0808 
0809             if (mipi_config->target_burst_mode_freq < bitrate) {
0810                 drm_err(&dev_priv->drm,
0811                     "Burst mode freq is less than computed\n");
0812                 return false;
0813             }
0814 
0815             burst_mode_ratio = DIV_ROUND_UP(
0816                 mipi_config->target_burst_mode_freq * 100,
0817                 bitrate);
0818 
0819             intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
0820         } else {
0821             drm_err(&dev_priv->drm,
0822                 "Burst mode target is not set\n");
0823             return false;
0824         }
0825     } else
0826         burst_mode_ratio = 100;
0827 
0828     intel_dsi->burst_mode_ratio = burst_mode_ratio;
0829 
0830     /* delays in VBT are in unit of 100us, so need to convert
0831      * here in ms
0832      * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
0833     intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
0834     intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
0835     intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
0836     intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
0837     intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
0838 
0839     intel_dsi->i2c_bus_num = -1;
0840 
0841     /* a regular driver would get the device in probe */
0842     for_each_dsi_port(port, intel_dsi->ports) {
0843         mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
0844     }
0845 
0846     return true;
0847 }
0848 
0849 /*
0850  * On some BYT/CHT devs some sequences are incomplete and we need to manually
0851  * control some GPIOs. We need to add a GPIO lookup table before we get these.
0852  * If the GOP did not initialize the panel (HDMI inserted) we may need to also
0853  * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
0854  */
0855 static struct gpiod_lookup_table pmic_panel_gpio_table = {
0856     /* Intel GFX is consumer */
0857     .dev_id = "0000:00:02.0",
0858     .table = {
0859         /* Panel EN/DISABLE */
0860         GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
0861         { }
0862     },
0863 };
0864 
0865 static struct gpiod_lookup_table soc_panel_gpio_table = {
0866     .dev_id = "0000:00:02.0",
0867     .table = {
0868         GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
0869         GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
0870         { }
0871     },
0872 };
0873 
0874 static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
0875     PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
0876               "pwm0_grp", "pwm"),
0877 };
0878 
0879 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
0880 {
0881     struct drm_device *dev = intel_dsi->base.base.dev;
0882     struct drm_i915_private *dev_priv = to_i915(dev);
0883     struct intel_connector *connector = intel_dsi->attached_connector;
0884     struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
0885     enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
0886     bool want_backlight_gpio = false;
0887     bool want_panel_gpio = false;
0888     struct pinctrl *pinctrl;
0889     int ret;
0890 
0891     if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
0892         mipi_config->pwm_blc == PPS_BLC_PMIC) {
0893         gpiod_add_lookup_table(&pmic_panel_gpio_table);
0894         want_panel_gpio = true;
0895     }
0896 
0897     if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
0898         gpiod_add_lookup_table(&soc_panel_gpio_table);
0899         want_panel_gpio = true;
0900         want_backlight_gpio = true;
0901 
0902         /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
0903         ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
0904                          ARRAY_SIZE(soc_pwm_pinctrl_map));
0905         if (ret)
0906             drm_err(&dev_priv->drm,
0907                 "Failed to register pwm0 pinmux mapping\n");
0908 
0909         pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
0910         if (IS_ERR(pinctrl))
0911             drm_err(&dev_priv->drm,
0912                 "Failed to set pinmux to PWM\n");
0913     }
0914 
0915     if (want_panel_gpio) {
0916         intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
0917         if (IS_ERR(intel_dsi->gpio_panel)) {
0918             drm_err(&dev_priv->drm,
0919                 "Failed to own gpio for panel control\n");
0920             intel_dsi->gpio_panel = NULL;
0921         }
0922     }
0923 
0924     if (want_backlight_gpio) {
0925         intel_dsi->gpio_backlight =
0926             gpiod_get(dev->dev, "backlight", flags);
0927         if (IS_ERR(intel_dsi->gpio_backlight)) {
0928             drm_err(&dev_priv->drm,
0929                 "Failed to own gpio for backlight control\n");
0930             intel_dsi->gpio_backlight = NULL;
0931         }
0932     }
0933 }
0934 
0935 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
0936 {
0937     struct drm_device *dev = intel_dsi->base.base.dev;
0938     struct drm_i915_private *dev_priv = to_i915(dev);
0939     struct intel_connector *connector = intel_dsi->attached_connector;
0940     struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
0941 
0942     if (intel_dsi->gpio_panel) {
0943         gpiod_put(intel_dsi->gpio_panel);
0944         intel_dsi->gpio_panel = NULL;
0945     }
0946 
0947     if (intel_dsi->gpio_backlight) {
0948         gpiod_put(intel_dsi->gpio_backlight);
0949         intel_dsi->gpio_backlight = NULL;
0950     }
0951 
0952     if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
0953         mipi_config->pwm_blc == PPS_BLC_PMIC)
0954         gpiod_remove_lookup_table(&pmic_panel_gpio_table);
0955 
0956     if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
0957         pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
0958         gpiod_remove_lookup_table(&soc_panel_gpio_table);
0959     }
0960 }
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