i915/display/intel_dsb.h

0001 /* SPDX-License-Identifier: MIT
0002  *
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef _INTEL_DSB_H
0007 #define _INTEL_DSB_H
0008
0009 #include <linux/types.h>
0010
0011 #include "i915_reg_defs.h"
0012
0013 struct intel_crtc_state;
0014 struct i915_vma;
0015
0016 enum dsb_id {
0017     INVALID_DSB = -1,
0018     DSB1,
0019     DSB2,
0020     DSB3,
0021     MAX_DSB_PER_PIPE
0022 };
0023
0024 struct intel_dsb {
0025     enum dsb_id id;
0026     u32 *cmd_buf;
0027     struct i915_vma *vma;
0028
0029     /*
0030      * free_pos will point the first free entry position
0031      * and help in calculating tail of command buffer.
0032      */
0033     int free_pos;
0034
0035     /*
0036      * ins_start_offset will help to store start address of the dsb
0037      * instuction and help in identifying the batch of auto-increment
0038      * register.
0039      */
0040     u32 ins_start_offset;
0041 };
0042
0043 void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
0044 void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
0045 void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
0046              i915_reg_t reg, u32 val);
0047 void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
0048                  i915_reg_t reg, u32 val);
0049 void intel_dsb_commit(const struct intel_crtc_state *crtc_state);
0050
0051 #endif