i915/display/intel_drrs.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2021 Intel Corporation
0004  */
0005
0006 #include "i915_drv.h"
0007 #include "intel_atomic.h"
0008 #include "intel_de.h"
0009 #include "intel_display_types.h"
0010 #include "intel_drrs.h"
0011 #include "intel_panel.h"
0012
0013 /**
0014  * DOC: Display Refresh Rate Switching (DRRS)
0015  *
0016  * Display Refresh Rate Switching (DRRS) is a power conservation feature
0017  * which enables swtching between low and high refresh rates,
0018  * dynamically, based on the usage scenario. This feature is applicable
0019  * for internal panels.
0020  *
0021  * Indication that the panel supports DRRS is given by the panel EDID, which
0022  * would list multiple refresh rates for one resolution.
0023  *
0024  * DRRS is of 2 types - static and seamless.
0025  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
0026  * (may appear as a blink on screen) and is used in dock-undock scenario.
0027  * Seamless DRRS involves changing RR without any visual effect to the user
0028  * and can be used during normal system usage. This is done by programming
0029  * certain registers.
0030  *
0031  * Support for static/seamless DRRS may be indicated in the VBT based on
0032  * inputs from the panel spec.
0033  *
0034  * DRRS saves power by switching to low RR based on usage scenarios.
0035  *
0036  * The implementation is based on frontbuffer tracking implementation.  When
0037  * there is a disturbance on the screen triggered by user activity or a periodic
0038  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
0039  * no movement on screen, after a timeout of 1 second, a switch to low RR is
0040  * made.
0041  *
0042  * For integration with frontbuffer tracking code, intel_drrs_invalidate()
0043  * and intel_drrs_flush() are called.
0044  *
0045  * DRRS can be further extended to support other internal panels and also
0046  * the scenario of video playback wherein RR is set based on the rate
0047  * requested by userspace.
0048  */
0049
0050 const char *intel_drrs_type_str(enum drrs_type drrs_type)
0051 {
0052     static const char * const str[] = {
0053         [DRRS_TYPE_NONE] = "none",
0054         [DRRS_TYPE_STATIC] = "static",
0055         [DRRS_TYPE_SEAMLESS] = "seamless",
0056     };
0057
0058     if (drrs_type >= ARRAY_SIZE(str))
0059         return "<invalid>";
0060
0061     return str[drrs_type];
0062 }
0063
0064 static void
0065 intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc,
0066                      enum drrs_refresh_rate refresh_rate)
0067 {
0068     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0069     enum transcoder cpu_transcoder = crtc->drrs.cpu_transcoder;
0070     u32 val, bit;
0071
0072     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0073         bit = PIPECONF_REFRESH_RATE_ALT_VLV;
0074     else
0075         bit = PIPECONF_REFRESH_RATE_ALT_ILK;
0076
0077     val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
0078
0079     if (refresh_rate == DRRS_REFRESH_RATE_LOW)
0080         val |= bit;
0081     else
0082         val &= ~bit;
0083
0084     intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
0085 }
0086
0087 static void
0088 intel_drrs_set_refresh_rate_m_n(struct intel_crtc *crtc,
0089                 enum drrs_refresh_rate refresh_rate)
0090 {
0091     intel_cpu_transcoder_set_m1_n1(crtc, crtc->drrs.cpu_transcoder,
0092                        refresh_rate == DRRS_REFRESH_RATE_LOW ?
0093                        &crtc->drrs.m2_n2 : &crtc->drrs.m_n);
0094 }
0095
0096 bool intel_drrs_is_active(struct intel_crtc *crtc)
0097 {
0098     return crtc->drrs.cpu_transcoder != INVALID_TRANSCODER;
0099 }
0100
0101 static void intel_drrs_set_state(struct intel_crtc *crtc,
0102                  enum drrs_refresh_rate refresh_rate)
0103 {
0104     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0105
0106     if (refresh_rate == crtc->drrs.refresh_rate)
0107         return;
0108
0109     if (intel_cpu_transcoder_has_m2_n2(dev_priv, crtc->drrs.cpu_transcoder))
0110         intel_drrs_set_refresh_rate_pipeconf(crtc, refresh_rate);
0111     else
0112         intel_drrs_set_refresh_rate_m_n(crtc, refresh_rate);
0113
0114     crtc->drrs.refresh_rate = refresh_rate;
0115 }
0116
0117 static void intel_drrs_schedule_work(struct intel_crtc *crtc)
0118 {
0119     mod_delayed_work(system_wq, &crtc->drrs.work, msecs_to_jiffies(1000));
0120 }
0121
0122 static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *crtc_state)
0123 {
0124     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0125     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0126     unsigned int frontbuffer_bits;
0127
0128     frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
0129
0130     for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,
0131                      crtc_state->bigjoiner_pipes)
0132         frontbuffer_bits |= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
0133
0134     return frontbuffer_bits;
0135 }
0136
0137 /**
0138  * intel_drrs_activate - activate DRRS
0139  * @crtc_state: the crtc state
0140  *
0141  * Activates DRRS on the crtc.
0142  */
0143 void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
0144 {
0145     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0146
0147     if (!crtc_state->has_drrs)
0148         return;
0149
0150     if (!crtc_state->hw.active)
0151         return;
0152
0153     if (intel_crtc_is_bigjoiner_slave(crtc_state))
0154         return;
0155
0156     mutex_lock(&crtc->drrs.mutex);
0157
0158     crtc->drrs.cpu_transcoder = crtc_state->cpu_transcoder;
0159     crtc->drrs.m_n = crtc_state->dp_m_n;
0160     crtc->drrs.m2_n2 = crtc_state->dp_m2_n2;
0161     crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state);
0162     crtc->drrs.busy_frontbuffer_bits = 0;
0163
0164     intel_drrs_schedule_work(crtc);
0165
0166     mutex_unlock(&crtc->drrs.mutex);
0167 }
0168
0169 /**
0170  * intel_drrs_deactivate - deactivate DRRS
0171  * @old_crtc_state: the old crtc state
0172  *
0173  * Deactivates DRRS on the crtc.
0174  */
0175 void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state)
0176 {
0177     struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
0178
0179     if (!old_crtc_state->has_drrs)
0180         return;
0181
0182     if (!old_crtc_state->hw.active)
0183         return;
0184
0185     if (intel_crtc_is_bigjoiner_slave(old_crtc_state))
0186         return;
0187
0188     mutex_lock(&crtc->drrs.mutex);
0189
0190     if (intel_drrs_is_active(crtc))
0191         intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH);
0192
0193     crtc->drrs.cpu_transcoder = INVALID_TRANSCODER;
0194     crtc->drrs.frontbuffer_bits = 0;
0195     crtc->drrs.busy_frontbuffer_bits = 0;
0196
0197     mutex_unlock(&crtc->drrs.mutex);
0198
0199     cancel_delayed_work_sync(&crtc->drrs.work);
0200 }
0201
0202 static void intel_drrs_downclock_work(struct work_struct *work)
0203 {
0204     struct intel_crtc *crtc = container_of(work, typeof(*crtc), drrs.work.work);
0205
0206     mutex_lock(&crtc->drrs.mutex);
0207
0208     if (intel_drrs_is_active(crtc) && !crtc->drrs.busy_frontbuffer_bits)
0209         intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_LOW);
0210
0211     mutex_unlock(&crtc->drrs.mutex);
0212 }
0213
0214 static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv,
0215                       unsigned int all_frontbuffer_bits,
0216                       bool invalidate)
0217 {
0218     struct intel_crtc *crtc;
0219
0220     for_each_intel_crtc(&dev_priv->drm, crtc) {
0221         unsigned int frontbuffer_bits;
0222
0223         mutex_lock(&crtc->drrs.mutex);
0224
0225         frontbuffer_bits = all_frontbuffer_bits & crtc->drrs.frontbuffer_bits;
0226         if (!frontbuffer_bits) {
0227             mutex_unlock(&crtc->drrs.mutex);
0228             continue;
0229         }
0230
0231         if (invalidate)
0232             crtc->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
0233         else
0234             crtc->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
0235
0236         /* flush/invalidate means busy screen hence upclock */
0237         intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH);
0238
0239         /*
0240          * flush also means no more activity hence schedule downclock, if all
0241          * other fbs are quiescent too
0242          */
0243         if (!crtc->drrs.busy_frontbuffer_bits)
0244             intel_drrs_schedule_work(crtc);
0245         else
0246             cancel_delayed_work(&crtc->drrs.work);
0247
0248         mutex_unlock(&crtc->drrs.mutex);
0249     }
0250 }
0251
0252 /**
0253  * intel_drrs_invalidate - Disable Idleness DRRS
0254  * @dev_priv: i915 device
0255  * @frontbuffer_bits: frontbuffer plane tracking bits
0256  *
0257  * This function gets called everytime rendering on the given planes start.
0258  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
0259  *
0260  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
0261  */
0262 void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
0263                unsigned int frontbuffer_bits)
0264 {
0265     intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true);
0266 }
0267
0268 /**
0269  * intel_drrs_flush - Restart Idleness DRRS
0270  * @dev_priv: i915 device
0271  * @frontbuffer_bits: frontbuffer plane tracking bits
0272  *
0273  * This function gets called every time rendering on the given planes has
0274  * completed or flip on a crtc is completed. So DRRS should be upclocked
0275  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
0276  * if no other planes are dirty.
0277  *
0278  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
0279  */
0280 void intel_drrs_flush(struct drm_i915_private *dev_priv,
0281               unsigned int frontbuffer_bits)
0282 {
0283     intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false);
0284 }
0285
0286 /**
0287  * intel_crtc_drrs_init - Init DRRS for CRTC
0288  * @crtc: crtc
0289  *
0290  * This function is called only once at driver load to initialize basic
0291  * DRRS stuff.
0292  *
0293  */
0294 void intel_crtc_drrs_init(struct intel_crtc *crtc)
0295 {
0296     INIT_DELAYED_WORK(&crtc->drrs.work, intel_drrs_downclock_work);
0297     mutex_init(&crtc->drrs.mutex);
0298     crtc->drrs.cpu_transcoder = INVALID_TRANSCODER;
0299 }