i915/display/intel_dpll_mgr.h

0001 /*
0002  * Copyright © 2012-2016 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  *
0023  */
0024
0025 #ifndef _INTEL_DPLL_MGR_H_
0026 #define _INTEL_DPLL_MGR_H_
0027
0028 #include <linux/types.h>
0029
0030 #include "intel_wakeref.h"
0031
0032 /*FIXME: Move this to a more appropriate place. */
0033 #define abs_diff(a, b) ({           \
0034     typeof(a) __a = (a);            \
0035     typeof(b) __b = (b);            \
0036     (void) (&__a == &__b);          \
0037     __a > __b ? (__a - __b) : (__b - __a); })
0038
0039 enum tc_port;
0040 struct drm_i915_private;
0041 struct intel_atomic_state;
0042 struct intel_crtc;
0043 struct intel_crtc_state;
0044 struct intel_encoder;
0045 struct intel_shared_dpll;
0046 struct intel_shared_dpll_funcs;
0047
0048 /**
0049  * enum intel_dpll_id - possible DPLL ids
0050  *
0051  * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
0052  */
0053 enum intel_dpll_id {
0054     /**
0055      * @DPLL_ID_PRIVATE: non-shared dpll in use
0056      */
0057     DPLL_ID_PRIVATE = -1,
0058
0059     /**
0060      * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
0061      */
0062     DPLL_ID_PCH_PLL_A = 0,
0063     /**
0064      * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
0065      */
0066     DPLL_ID_PCH_PLL_B = 1,
0067
0068
0069     /**
0070      * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
0071      */
0072     DPLL_ID_WRPLL1 = 0,
0073     /**
0074      * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
0075      */
0076     DPLL_ID_WRPLL2 = 1,
0077     /**
0078      * @DPLL_ID_SPLL: HSW and BDW SPLL
0079      */
0080     DPLL_ID_SPLL = 2,
0081     /**
0082      * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
0083      */
0084     DPLL_ID_LCPLL_810 = 3,
0085     /**
0086      * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
0087      */
0088     DPLL_ID_LCPLL_1350 = 4,
0089     /**
0090      * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
0091      */
0092     DPLL_ID_LCPLL_2700 = 5,
0093
0094
0095     /**
0096      * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
0097      */
0098     DPLL_ID_SKL_DPLL0 = 0,
0099     /**
0100      * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
0101      */
0102     DPLL_ID_SKL_DPLL1 = 1,
0103     /**
0104      * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
0105      */
0106     DPLL_ID_SKL_DPLL2 = 2,
0107     /**
0108      * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
0109      */
0110     DPLL_ID_SKL_DPLL3 = 3,
0111
0112
0113     /**
0114      * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
0115      */
0116     DPLL_ID_ICL_DPLL0 = 0,
0117     /**
0118      * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
0119      */
0120     DPLL_ID_ICL_DPLL1 = 1,
0121     /**
0122      * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
0123      */
0124     DPLL_ID_EHL_DPLL4 = 2,
0125     /**
0126      * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
0127      */
0128     DPLL_ID_ICL_TBTPLL = 2,
0129     /**
0130      * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
0131      *                      TGL TC PLL 1 port 1 (TC1)
0132      */
0133     DPLL_ID_ICL_MGPLL1 = 3,
0134     /**
0135      * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
0136      *                      TGL TC PLL 1 port 2 (TC2)
0137      */
0138     DPLL_ID_ICL_MGPLL2 = 4,
0139     /**
0140      * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
0141      *                      TGL TC PLL 1 port 3 (TC3)
0142      */
0143     DPLL_ID_ICL_MGPLL3 = 5,
0144     /**
0145      * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
0146      *                      TGL TC PLL 1 port 4 (TC4)
0147      */
0148     DPLL_ID_ICL_MGPLL4 = 6,
0149     /**
0150      * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
0151      */
0152     DPLL_ID_TGL_MGPLL5 = 7,
0153     /**
0154      * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
0155      */
0156     DPLL_ID_TGL_MGPLL6 = 8,
0157
0158     /**
0159      * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
0160      */
0161     DPLL_ID_DG1_DPLL0 = 0,
0162     /**
0163      * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
0164      */
0165     DPLL_ID_DG1_DPLL1 = 1,
0166     /**
0167      * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
0168      */
0169     DPLL_ID_DG1_DPLL2 = 2,
0170     /**
0171      * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
0172      */
0173     DPLL_ID_DG1_DPLL3 = 3,
0174 };
0175
0176 #define I915_NUM_PLLS 9
0177
0178 enum icl_port_dpll_id {
0179     ICL_PORT_DPLL_DEFAULT,
0180     ICL_PORT_DPLL_MG_PHY,
0181
0182     ICL_PORT_DPLL_COUNT,
0183 };
0184
0185 struct intel_dpll_hw_state {
0186     /* i9xx, pch plls */
0187     u32 dpll;
0188     u32 dpll_md;
0189     u32 fp0;
0190     u32 fp1;
0191
0192     /* hsw, bdw */
0193     u32 wrpll;
0194     u32 spll;
0195
0196     /* skl */
0197     /*
0198      * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
0199      * lower part of ctrl1 and they get shifted into position when writing
0200      * the register.  This allows us to easily compare the state to share
0201      * the DPLL.
0202      */
0203     u32 ctrl1;
0204     /* HDMI only, 0 when used for DP */
0205     u32 cfgcr1, cfgcr2;
0206
0207     /* icl */
0208     u32 cfgcr0;
0209
0210     /* tgl */
0211     u32 div0;
0212
0213     /* bxt */
0214     u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
0215
0216     /*
0217      * ICL uses the following, already defined:
0218      * u32 cfgcr0, cfgcr1;
0219      */
0220     u32 mg_refclkin_ctl;
0221     u32 mg_clktop2_coreclkctl1;
0222     u32 mg_clktop2_hsclkctl;
0223     u32 mg_pll_div0;
0224     u32 mg_pll_div1;
0225     u32 mg_pll_lf;
0226     u32 mg_pll_frac_lock;
0227     u32 mg_pll_ssc;
0228     u32 mg_pll_bias;
0229     u32 mg_pll_tdc_coldst_bias;
0230     u32 mg_pll_bias_mask;
0231     u32 mg_pll_tdc_coldst_bias_mask;
0232 };
0233
0234 /**
0235  * struct intel_shared_dpll_state - hold the DPLL atomic state
0236  *
0237  * This structure holds an atomic state for the DPLL, that can represent
0238  * either its current state (in struct &intel_shared_dpll) or a desired
0239  * future state which would be applied by an atomic mode set (stored in
0240  * a struct &intel_atomic_state).
0241  *
0242  * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
0243  */
0244 struct intel_shared_dpll_state {
0245     /**
0246      * @pipe_mask: mask of pipes using this DPLL, active or not
0247      */
0248     u8 pipe_mask;
0249
0250     /**
0251      * @hw_state: hardware configuration for the DPLL stored in
0252      * struct &intel_dpll_hw_state.
0253      */
0254     struct intel_dpll_hw_state hw_state;
0255 };
0256
0257 /**
0258  * struct dpll_info - display PLL platform specific info
0259  */
0260 struct dpll_info {
0261     /**
0262      * @name: DPLL name; used for logging
0263      */
0264     const char *name;
0265
0266     /**
0267      * @funcs: platform specific hooks
0268      */
0269     const struct intel_shared_dpll_funcs *funcs;
0270
0271     /**
0272      * @id: unique indentifier for this DPLL; should match the index in the
0273      * dev_priv->shared_dplls array
0274      */
0275     enum intel_dpll_id id;
0276
0277 #define INTEL_DPLL_ALWAYS_ON    (1 << 0)
0278     /**
0279      * @flags:
0280      *
0281      * INTEL_DPLL_ALWAYS_ON
0282      *     Inform the state checker that the DPLL is kept enabled even if
0283      *     not in use by any CRTC.
0284      */
0285     u32 flags;
0286 };
0287
0288 /**
0289  * struct intel_shared_dpll - display PLL with tracked state and users
0290  */
0291 struct intel_shared_dpll {
0292     /**
0293      * @state:
0294      *
0295      * Store the state for the pll, including its hw state
0296      * and CRTCs using it.
0297      */
0298     struct intel_shared_dpll_state state;
0299
0300     /**
0301      * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
0302      */
0303     u8 active_mask;
0304
0305     /**
0306      * @on: is the PLL actually active? Disabled during modeset
0307      */
0308     bool on;
0309
0310     /**
0311      * @info: platform specific info
0312      */
0313     const struct dpll_info *info;
0314
0315     /**
0316      * @wakeref: In some platforms a device-level runtime pm reference may
0317      * need to be grabbed to disable DC states while this DPLL is enabled
0318      */
0319     intel_wakeref_t wakeref;
0320 };
0321
0322 #define SKL_DPLL0 0
0323 #define SKL_DPLL1 1
0324 #define SKL_DPLL2 2
0325 #define SKL_DPLL3 3
0326
0327 /* shared dpll functions */
0328 struct intel_shared_dpll *
0329 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
0330                 enum intel_dpll_id id);
0331 enum intel_dpll_id
0332 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
0333              struct intel_shared_dpll *pll);
0334 void assert_shared_dpll(struct drm_i915_private *dev_priv,
0335             struct intel_shared_dpll *pll,
0336             bool state);
0337 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
0338 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
0339 int intel_compute_shared_dplls(struct intel_atomic_state *state,
0340                    struct intel_crtc *crtc,
0341                    struct intel_encoder *encoder);
0342 int intel_reserve_shared_dplls(struct intel_atomic_state *state,
0343                    struct intel_crtc *crtc,
0344                    struct intel_encoder *encoder);
0345 void intel_release_shared_dplls(struct intel_atomic_state *state,
0346                 struct intel_crtc *crtc);
0347 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
0348                   enum icl_port_dpll_id port_dpll_id);
0349 void intel_update_active_dpll(struct intel_atomic_state *state,
0350                   struct intel_crtc *crtc,
0351                   struct intel_encoder *encoder);
0352 int intel_dpll_get_freq(struct drm_i915_private *i915,
0353             const struct intel_shared_dpll *pll,
0354             const struct intel_dpll_hw_state *pll_state);
0355 bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
0356                  struct intel_shared_dpll *pll,
0357                  struct intel_dpll_hw_state *hw_state);
0358 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
0359 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
0360 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
0361 void intel_shared_dpll_init(struct drm_i915_private *dev_priv);
0362 void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
0363 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
0364 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
0365
0366 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
0367                   const struct intel_dpll_hw_state *hw_state);
0368 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
0369 bool intel_dpll_is_combophy(enum intel_dpll_id id);
0370
0371 void intel_shared_dpll_state_verify(struct intel_crtc *crtc,
0372                     struct intel_crtc_state *old_crtc_state,
0373                     struct intel_crtc_state *new_crtc_state);
0374 void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915);
0375
0376 #endif /* _INTEL_DPLL_MGR_H_ */