i915/display/intel_dpio_phy.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_DPIO_PHY_H__
0007 #define __INTEL_DPIO_PHY_H__
0008
0009 #include <linux/types.h>
0010
0011 enum dpio_channel;
0012 enum dpio_phy;
0013 enum port;
0014 struct drm_i915_private;
0015 struct intel_crtc_state;
0016 struct intel_encoder;
0017
0018 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
0019                  enum dpio_phy *phy, enum dpio_channel *ch);
0020 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
0021                    const struct intel_crtc_state *crtc_state);
0022 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
0023 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
0024 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
0025                 enum dpio_phy phy);
0026 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
0027                   enum dpio_phy phy);
0028 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
0029 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
0030                      u8 lane_lat_optim_mask);
0031 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
0032
0033 void chv_set_phy_signal_level(struct intel_encoder *encoder,
0034                   const struct intel_crtc_state *crtc_state,
0035                   u32 deemph_reg_value, u32 margin_reg_value,
0036                   bool uniq_trans_scale);
0037 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
0038                   const struct intel_crtc_state *crtc_state,
0039                   bool reset);
0040 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
0041                 const struct intel_crtc_state *crtc_state);
0042 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
0043                 const struct intel_crtc_state *crtc_state);
0044 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
0045 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
0046                   const struct intel_crtc_state *old_crtc_state);
0047
0048 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
0049                   const struct intel_crtc_state *crtc_state,
0050                   u32 demph_reg_value, u32 preemph_reg_value,
0051                   u32 uniqtranscale_reg_value, u32 tx3_demph);
0052 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
0053                 const struct intel_crtc_state *crtc_state);
0054 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
0055                 const struct intel_crtc_state *crtc_state);
0056 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
0057              const struct intel_crtc_state *old_crtc_state);
0058
0059 #endif /* __INTEL_DPIO_PHY_H__ */