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0001 /*
0002  * Copyright © 2008 Intel Corporation
0003  *             2014 Red Hat Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice (including the next
0013  * paragraph) shall be included in all copies or substantial portions of the
0014  * Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0020  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0021  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0022  * IN THE SOFTWARE.
0023  *
0024  */
0025 
0026 #include <drm/drm_atomic.h>
0027 #include <drm/drm_atomic_helper.h>
0028 #include <drm/drm_edid.h>
0029 #include <drm/drm_probe_helper.h>
0030 
0031 #include "i915_drv.h"
0032 #include "intel_atomic.h"
0033 #include "intel_audio.h"
0034 #include "intel_connector.h"
0035 #include "intel_crtc.h"
0036 #include "intel_ddi.h"
0037 #include "intel_de.h"
0038 #include "intel_display_types.h"
0039 #include "intel_dp.h"
0040 #include "intel_dp_hdcp.h"
0041 #include "intel_dp_mst.h"
0042 #include "intel_dpio_phy.h"
0043 #include "intel_hdcp.h"
0044 #include "intel_hotplug.h"
0045 #include "skl_scaler.h"
0046 
0047 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
0048                         struct intel_crtc_state *crtc_state,
0049                         struct drm_connector_state *conn_state,
0050                         struct link_config_limits *limits)
0051 {
0052     struct drm_atomic_state *state = crtc_state->uapi.state;
0053     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0054     struct intel_dp *intel_dp = &intel_mst->primary->dp;
0055     struct intel_connector *connector =
0056         to_intel_connector(conn_state->connector);
0057     struct drm_i915_private *i915 = to_i915(connector->base.dev);
0058     const struct drm_display_mode *adjusted_mode =
0059         &crtc_state->hw.adjusted_mode;
0060     bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
0061     int bpp, slots = -EINVAL;
0062 
0063     crtc_state->lane_count = limits->max_lane_count;
0064     crtc_state->port_clock = limits->max_rate;
0065 
0066     for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
0067         crtc_state->pipe_bpp = bpp;
0068 
0069         crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
0070                                crtc_state->pipe_bpp,
0071                                false);
0072 
0073         slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
0074                               connector->port,
0075                               crtc_state->pbn,
0076                               drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
0077                                            crtc_state->port_clock,
0078                                            crtc_state->lane_count));
0079         if (slots == -EDEADLK)
0080             return slots;
0081         if (slots >= 0)
0082             break;
0083     }
0084 
0085     if (slots < 0) {
0086         drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
0087                 slots);
0088         return slots;
0089     }
0090 
0091     intel_link_compute_m_n(crtc_state->pipe_bpp,
0092                    crtc_state->lane_count,
0093                    adjusted_mode->crtc_clock,
0094                    crtc_state->port_clock,
0095                    &crtc_state->dp_m_n,
0096                    constant_n, crtc_state->fec_enable);
0097     crtc_state->dp_m_n.tu = slots;
0098 
0099     return 0;
0100 }
0101 
0102 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
0103                      struct intel_crtc_state *crtc_state,
0104                      struct drm_connector_state *conn_state)
0105 {
0106     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
0107     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0108     struct intel_dp *intel_dp = &intel_mst->primary->dp;
0109     struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
0110     struct drm_dp_mst_topology_state *topology_state;
0111     u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
0112         DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
0113 
0114     topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
0115     if (IS_ERR(topology_state)) {
0116         drm_dbg_kms(&i915->drm, "slot update failed\n");
0117         return PTR_ERR(topology_state);
0118     }
0119 
0120     drm_dp_mst_update_slots(topology_state, link_coding_cap);
0121 
0122     return 0;
0123 }
0124 
0125 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
0126                        struct intel_crtc_state *pipe_config,
0127                        struct drm_connector_state *conn_state)
0128 {
0129     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0130     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0131     struct intel_dp *intel_dp = &intel_mst->primary->dp;
0132     struct intel_connector *connector =
0133         to_intel_connector(conn_state->connector);
0134     struct intel_digital_connector_state *intel_conn_state =
0135         to_intel_digital_connector_state(conn_state);
0136     const struct drm_display_mode *adjusted_mode =
0137         &pipe_config->hw.adjusted_mode;
0138     struct link_config_limits limits;
0139     int ret;
0140 
0141     if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
0142         return -EINVAL;
0143 
0144     pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
0145     pipe_config->has_pch_encoder = false;
0146 
0147     if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
0148         pipe_config->has_audio = connector->port->has_audio;
0149     else
0150         pipe_config->has_audio =
0151             intel_conn_state->force_audio == HDMI_AUDIO_ON;
0152 
0153     /*
0154      * for MST we always configure max link bw - the spec doesn't
0155      * seem to suggest we should do otherwise.
0156      */
0157     limits.min_rate =
0158     limits.max_rate = intel_dp_max_link_rate(intel_dp);
0159 
0160     limits.min_lane_count =
0161     limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
0162 
0163     limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
0164     /*
0165      * FIXME: If all the streams can't fit into the link with
0166      * their current pipe_bpp we should reduce pipe_bpp across
0167      * the board until things start to fit. Until then we
0168      * limit to <= 8bpc since that's what was hardcoded for all
0169      * MST streams previously. This hack should be removed once
0170      * we have the proper retry logic in place.
0171      */
0172     limits.max_bpp = min(pipe_config->pipe_bpp, 24);
0173 
0174     intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
0175 
0176     ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
0177                            conn_state, &limits);
0178     if (ret)
0179         return ret;
0180 
0181     ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
0182     if (ret)
0183         return ret;
0184 
0185     pipe_config->limited_color_range =
0186         intel_dp_limited_color_range(pipe_config, conn_state);
0187 
0188     if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
0189         pipe_config->lane_lat_optim_mask =
0190             bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
0191 
0192     intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
0193 
0194     return 0;
0195 }
0196 
0197 /*
0198  * Iterate over all connectors and return a mask of
0199  * all CPU transcoders streaming over the same DP link.
0200  */
0201 static unsigned int
0202 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
0203                  struct intel_dp *mst_port)
0204 {
0205     struct drm_i915_private *dev_priv = to_i915(state->base.dev);
0206     const struct intel_digital_connector_state *conn_state;
0207     struct intel_connector *connector;
0208     u8 transcoders = 0;
0209     int i;
0210 
0211     if (DISPLAY_VER(dev_priv) < 12)
0212         return 0;
0213 
0214     for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
0215         const struct intel_crtc_state *crtc_state;
0216         struct intel_crtc *crtc;
0217 
0218         if (connector->mst_port != mst_port || !conn_state->base.crtc)
0219             continue;
0220 
0221         crtc = to_intel_crtc(conn_state->base.crtc);
0222         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
0223 
0224         if (!crtc_state->hw.active)
0225             continue;
0226 
0227         transcoders |= BIT(crtc_state->cpu_transcoder);
0228     }
0229 
0230     return transcoders;
0231 }
0232 
0233 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
0234                         struct intel_crtc_state *crtc_state,
0235                         struct drm_connector_state *conn_state)
0236 {
0237     struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
0238     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0239     struct intel_dp *intel_dp = &intel_mst->primary->dp;
0240 
0241     /* lowest numbered transcoder will be designated master */
0242     crtc_state->mst_master_transcoder =
0243         ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
0244 
0245     return 0;
0246 }
0247 
0248 /*
0249  * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
0250  * that shares the same MST stream as mode changed,
0251  * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
0252  * a fastset when possible.
0253  */
0254 static int
0255 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
0256                        struct intel_atomic_state *state)
0257 {
0258     struct drm_i915_private *dev_priv = to_i915(state->base.dev);
0259     struct drm_connector_list_iter connector_list_iter;
0260     struct intel_connector *connector_iter;
0261     int ret = 0;
0262 
0263     if (DISPLAY_VER(dev_priv) < 12)
0264         return  0;
0265 
0266     if (!intel_connector_needs_modeset(state, &connector->base))
0267         return 0;
0268 
0269     drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
0270     for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
0271         struct intel_digital_connector_state *conn_iter_state;
0272         struct intel_crtc_state *crtc_state;
0273         struct intel_crtc *crtc;
0274 
0275         if (connector_iter->mst_port != connector->mst_port ||
0276             connector_iter == connector)
0277             continue;
0278 
0279         conn_iter_state = intel_atomic_get_digital_connector_state(state,
0280                                        connector_iter);
0281         if (IS_ERR(conn_iter_state)) {
0282             ret = PTR_ERR(conn_iter_state);
0283             break;
0284         }
0285 
0286         if (!conn_iter_state->base.crtc)
0287             continue;
0288 
0289         crtc = to_intel_crtc(conn_iter_state->base.crtc);
0290         crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
0291         if (IS_ERR(crtc_state)) {
0292             ret = PTR_ERR(crtc_state);
0293             break;
0294         }
0295 
0296         ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
0297         if (ret)
0298             break;
0299         crtc_state->uapi.mode_changed = true;
0300     }
0301     drm_connector_list_iter_end(&connector_list_iter);
0302 
0303     return ret;
0304 }
0305 
0306 static int
0307 intel_dp_mst_atomic_check(struct drm_connector *connector,
0308               struct drm_atomic_state *_state)
0309 {
0310     struct intel_atomic_state *state = to_intel_atomic_state(_state);
0311     struct drm_connector_state *new_conn_state =
0312         drm_atomic_get_new_connector_state(&state->base, connector);
0313     struct drm_connector_state *old_conn_state =
0314         drm_atomic_get_old_connector_state(&state->base, connector);
0315     struct intel_connector *intel_connector =
0316         to_intel_connector(connector);
0317     struct drm_crtc *new_crtc = new_conn_state->crtc;
0318     struct drm_dp_mst_topology_mgr *mgr;
0319     int ret;
0320 
0321     ret = intel_digital_connector_atomic_check(connector, &state->base);
0322     if (ret)
0323         return ret;
0324 
0325     ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state);
0326     if (ret)
0327         return ret;
0328 
0329     if (!old_conn_state->crtc)
0330         return 0;
0331 
0332     /* We only want to free VCPI if this state disables the CRTC on this
0333      * connector
0334      */
0335     if (new_crtc) {
0336         struct intel_crtc *crtc = to_intel_crtc(new_crtc);
0337         struct intel_crtc_state *crtc_state =
0338             intel_atomic_get_new_crtc_state(state, crtc);
0339 
0340         if (!crtc_state ||
0341             !drm_atomic_crtc_needs_modeset(&crtc_state->uapi) ||
0342             crtc_state->uapi.enable)
0343             return 0;
0344     }
0345 
0346     mgr = &enc_to_mst(to_intel_encoder(old_conn_state->best_encoder))->primary->dp.mst_mgr;
0347     ret = drm_dp_atomic_release_vcpi_slots(&state->base, mgr,
0348                            intel_connector->port);
0349 
0350     return ret;
0351 }
0352 
0353 static void clear_act_sent(struct intel_encoder *encoder,
0354                const struct intel_crtc_state *crtc_state)
0355 {
0356     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
0357 
0358     intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
0359                DP_TP_STATUS_ACT_SENT);
0360 }
0361 
0362 static void wait_for_act_sent(struct intel_encoder *encoder,
0363                   const struct intel_crtc_state *crtc_state)
0364 {
0365     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
0366     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0367     struct intel_dp *intel_dp = &intel_mst->primary->dp;
0368 
0369     if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
0370                   DP_TP_STATUS_ACT_SENT, 1))
0371         drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
0372 
0373     drm_dp_check_act_status(&intel_dp->mst_mgr);
0374 }
0375 
0376 static void intel_mst_disable_dp(struct intel_atomic_state *state,
0377                  struct intel_encoder *encoder,
0378                  const struct intel_crtc_state *old_crtc_state,
0379                  const struct drm_connector_state *old_conn_state)
0380 {
0381     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0382     struct intel_digital_port *dig_port = intel_mst->primary;
0383     struct intel_dp *intel_dp = &dig_port->dp;
0384     struct intel_connector *connector =
0385         to_intel_connector(old_conn_state->connector);
0386     struct drm_i915_private *i915 = to_i915(connector->base.dev);
0387     int start_slot = intel_dp_is_uhbr(old_crtc_state) ? 0 : 1;
0388     int ret;
0389 
0390     drm_dbg_kms(&i915->drm, "active links %d\n",
0391             intel_dp->active_mst_links);
0392 
0393     intel_hdcp_disable(intel_mst->connector);
0394 
0395     drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port);
0396 
0397     ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr, start_slot);
0398     if (ret) {
0399         drm_dbg_kms(&i915->drm, "failed to update payload %d\n", ret);
0400     }
0401 
0402     intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
0403 }
0404 
0405 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
0406                       struct intel_encoder *encoder,
0407                       const struct intel_crtc_state *old_crtc_state,
0408                       const struct drm_connector_state *old_conn_state)
0409 {
0410     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0411     struct intel_digital_port *dig_port = intel_mst->primary;
0412     struct intel_dp *intel_dp = &dig_port->dp;
0413     struct intel_connector *connector =
0414         to_intel_connector(old_conn_state->connector);
0415     struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0416     bool last_mst_stream;
0417 
0418     intel_dp->active_mst_links--;
0419     last_mst_stream = intel_dp->active_mst_links == 0;
0420     drm_WARN_ON(&dev_priv->drm,
0421             DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
0422             !intel_dp_mst_is_master_trans(old_crtc_state));
0423 
0424     intel_crtc_vblank_off(old_crtc_state);
0425 
0426     intel_disable_transcoder(old_crtc_state);
0427 
0428     drm_dp_update_payload_part2(&intel_dp->mst_mgr);
0429 
0430     clear_act_sent(encoder, old_crtc_state);
0431 
0432     intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
0433              TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
0434 
0435     wait_for_act_sent(encoder, old_crtc_state);
0436 
0437     drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
0438 
0439     intel_ddi_disable_transcoder_func(old_crtc_state);
0440 
0441     if (DISPLAY_VER(dev_priv) >= 9)
0442         skl_scaler_disable(old_crtc_state);
0443     else
0444         ilk_pfit_disable(old_crtc_state);
0445 
0446     /*
0447      * Power down mst path before disabling the port, otherwise we end
0448      * up getting interrupts from the sink upon detecting link loss.
0449      */
0450     drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
0451                      false);
0452 
0453     /*
0454      * BSpec 4287: disable DIP after the transcoder is disabled and before
0455      * the transcoder clock select is set to none.
0456      */
0457     if (last_mst_stream)
0458         intel_dp_set_infoframes(&dig_port->base, false,
0459                     old_crtc_state, NULL);
0460     /*
0461      * From TGL spec: "If multi-stream slave transcoder: Configure
0462      * Transcoder Clock Select to direct no clock to the transcoder"
0463      *
0464      * From older GENs spec: "Configure Transcoder Clock Select to direct
0465      * no clock to the transcoder"
0466      */
0467     if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
0468         intel_ddi_disable_pipe_clock(old_crtc_state);
0469 
0470 
0471     intel_mst->connector = NULL;
0472     if (last_mst_stream)
0473         dig_port->base.post_disable(state, &dig_port->base,
0474                           old_crtc_state, NULL);
0475 
0476     drm_dbg_kms(&dev_priv->drm, "active links %d\n",
0477             intel_dp->active_mst_links);
0478 }
0479 
0480 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
0481                     struct intel_encoder *encoder,
0482                     const struct intel_crtc_state *pipe_config,
0483                     const struct drm_connector_state *conn_state)
0484 {
0485     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0486     struct intel_digital_port *dig_port = intel_mst->primary;
0487     struct intel_dp *intel_dp = &dig_port->dp;
0488 
0489     if (intel_dp->active_mst_links == 0)
0490         dig_port->base.pre_pll_enable(state, &dig_port->base,
0491                             pipe_config, NULL);
0492 }
0493 
0494 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
0495                     struct intel_encoder *encoder,
0496                     const struct intel_crtc_state *pipe_config,
0497                     const struct drm_connector_state *conn_state)
0498 {
0499     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0500     struct intel_digital_port *dig_port = intel_mst->primary;
0501     struct intel_dp *intel_dp = &dig_port->dp;
0502     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0503     struct intel_connector *connector =
0504         to_intel_connector(conn_state->connector);
0505     int start_slot = intel_dp_is_uhbr(pipe_config) ? 0 : 1;
0506     int ret;
0507     bool first_mst_stream;
0508 
0509     /* MST encoders are bound to a crtc, not to a connector,
0510      * force the mapping here for get_hw_state.
0511      */
0512     connector->encoder = encoder;
0513     intel_mst->connector = connector;
0514     first_mst_stream = intel_dp->active_mst_links == 0;
0515     drm_WARN_ON(&dev_priv->drm,
0516             DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
0517             !intel_dp_mst_is_master_trans(pipe_config));
0518 
0519     drm_dbg_kms(&dev_priv->drm, "active links %d\n",
0520             intel_dp->active_mst_links);
0521 
0522     if (first_mst_stream)
0523         intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
0524 
0525     drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
0526 
0527     if (first_mst_stream)
0528         dig_port->base.pre_enable(state, &dig_port->base,
0529                         pipe_config, NULL);
0530 
0531     ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr,
0532                        connector->port,
0533                        pipe_config->pbn,
0534                        pipe_config->dp_m_n.tu);
0535     if (!ret)
0536         drm_err(&dev_priv->drm, "failed to allocate vcpi\n");
0537 
0538     intel_dp->active_mst_links++;
0539 
0540     ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr, start_slot);
0541 
0542     /*
0543      * Before Gen 12 this is not done as part of
0544      * dig_port->base.pre_enable() and should be done here. For
0545      * Gen 12+ the step in which this should be done is different for the
0546      * first MST stream, so it's done on the DDI for the first stream and
0547      * here for the following ones.
0548      */
0549     if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
0550         intel_ddi_enable_pipe_clock(encoder, pipe_config);
0551 
0552     intel_ddi_set_dp_msa(pipe_config, conn_state);
0553 }
0554 
0555 static void intel_mst_enable_dp(struct intel_atomic_state *state,
0556                 struct intel_encoder *encoder,
0557                 const struct intel_crtc_state *pipe_config,
0558                 const struct drm_connector_state *conn_state)
0559 {
0560     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0561     struct intel_digital_port *dig_port = intel_mst->primary;
0562     struct intel_dp *intel_dp = &dig_port->dp;
0563     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0564     enum transcoder trans = pipe_config->cpu_transcoder;
0565 
0566     drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
0567 
0568     clear_act_sent(encoder, pipe_config);
0569 
0570     if (intel_dp_is_uhbr(pipe_config)) {
0571         const struct drm_display_mode *adjusted_mode =
0572             &pipe_config->hw.adjusted_mode;
0573         u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
0574 
0575         intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
0576                    TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
0577         intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
0578                    TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
0579     }
0580 
0581     intel_ddi_enable_transcoder_func(encoder, pipe_config);
0582 
0583     intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
0584              TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
0585 
0586     drm_dbg_kms(&dev_priv->drm, "active links %d\n",
0587             intel_dp->active_mst_links);
0588 
0589     wait_for_act_sent(encoder, pipe_config);
0590 
0591     drm_dp_update_payload_part2(&intel_dp->mst_mgr);
0592 
0593     if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
0594         intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
0595                  FECSTALL_DIS_DPTSTREAM_DPTTG);
0596 
0597     intel_enable_transcoder(pipe_config);
0598 
0599     intel_crtc_vblank_on(pipe_config);
0600 
0601     intel_audio_codec_enable(encoder, pipe_config, conn_state);
0602 
0603     /* Enable hdcp if it's desired */
0604     if (conn_state->content_protection ==
0605         DRM_MODE_CONTENT_PROTECTION_DESIRED)
0606         intel_hdcp_enable(to_intel_connector(conn_state->connector),
0607                   pipe_config,
0608                   (u8)conn_state->hdcp_content_type);
0609 }
0610 
0611 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
0612                       enum pipe *pipe)
0613 {
0614     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0615     *pipe = intel_mst->pipe;
0616     if (intel_mst->connector)
0617         return true;
0618     return false;
0619 }
0620 
0621 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
0622                     struct intel_crtc_state *pipe_config)
0623 {
0624     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0625     struct intel_digital_port *dig_port = intel_mst->primary;
0626 
0627     dig_port->base.get_config(&dig_port->base, pipe_config);
0628 }
0629 
0630 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
0631                            struct intel_crtc_state *crtc_state)
0632 {
0633     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
0634     struct intel_digital_port *dig_port = intel_mst->primary;
0635 
0636     return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
0637 }
0638 
0639 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
0640 {
0641     struct intel_connector *intel_connector = to_intel_connector(connector);
0642     struct intel_dp *intel_dp = intel_connector->mst_port;
0643     struct edid *edid;
0644     int ret;
0645 
0646     if (drm_connector_is_unregistered(connector))
0647         return intel_connector_update_modes(connector, NULL);
0648 
0649     edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
0650     ret = intel_connector_update_modes(connector, edid);
0651     kfree(edid);
0652 
0653     return ret;
0654 }
0655 
0656 static int
0657 intel_dp_mst_connector_late_register(struct drm_connector *connector)
0658 {
0659     struct intel_connector *intel_connector = to_intel_connector(connector);
0660     int ret;
0661 
0662     ret = drm_dp_mst_connector_late_register(connector,
0663                          intel_connector->port);
0664     if (ret < 0)
0665         return ret;
0666 
0667     ret = intel_connector_register(connector);
0668     if (ret < 0)
0669         drm_dp_mst_connector_early_unregister(connector,
0670                               intel_connector->port);
0671 
0672     return ret;
0673 }
0674 
0675 static void
0676 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
0677 {
0678     struct intel_connector *intel_connector = to_intel_connector(connector);
0679 
0680     intel_connector_unregister(connector);
0681     drm_dp_mst_connector_early_unregister(connector,
0682                           intel_connector->port);
0683 }
0684 
0685 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
0686     .fill_modes = drm_helper_probe_single_connector_modes,
0687     .atomic_get_property = intel_digital_connector_atomic_get_property,
0688     .atomic_set_property = intel_digital_connector_atomic_set_property,
0689     .late_register = intel_dp_mst_connector_late_register,
0690     .early_unregister = intel_dp_mst_connector_early_unregister,
0691     .destroy = intel_connector_destroy,
0692     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
0693     .atomic_duplicate_state = intel_digital_connector_duplicate_state,
0694 };
0695 
0696 static int intel_dp_mst_get_modes(struct drm_connector *connector)
0697 {
0698     return intel_dp_mst_get_ddc_modes(connector);
0699 }
0700 
0701 static int
0702 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
0703                 struct drm_display_mode *mode,
0704                 struct drm_modeset_acquire_ctx *ctx,
0705                 enum drm_mode_status *status)
0706 {
0707     struct drm_i915_private *dev_priv = to_i915(connector->dev);
0708     struct intel_connector *intel_connector = to_intel_connector(connector);
0709     struct intel_dp *intel_dp = intel_connector->mst_port;
0710     struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
0711     struct drm_dp_mst_port *port = intel_connector->port;
0712     const int min_bpp = 18;
0713     int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
0714     int max_rate, mode_rate, max_lanes, max_link_clock;
0715     int ret;
0716 
0717     if (drm_connector_is_unregistered(connector)) {
0718         *status = MODE_ERROR;
0719         return 0;
0720     }
0721 
0722     if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
0723         *status = MODE_NO_DBLESCAN;
0724         return 0;
0725     }
0726 
0727     max_link_clock = intel_dp_max_link_rate(intel_dp);
0728     max_lanes = intel_dp_max_lane_count(intel_dp);
0729 
0730     max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
0731     mode_rate = intel_dp_link_required(mode->clock, min_bpp);
0732 
0733     ret = drm_modeset_lock(&mgr->base.lock, ctx);
0734     if (ret)
0735         return ret;
0736 
0737     if (mode_rate > max_rate || mode->clock > max_dotclk ||
0738         drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
0739         *status = MODE_CLOCK_HIGH;
0740         return 0;
0741     }
0742 
0743     if (mode->clock < 10000) {
0744         *status = MODE_CLOCK_LOW;
0745         return 0;
0746     }
0747 
0748     if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
0749         *status = MODE_H_ILLEGAL;
0750         return 0;
0751     }
0752 
0753     *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
0754     return 0;
0755 }
0756 
0757 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
0758                              struct drm_atomic_state *state)
0759 {
0760     struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
0761                                              connector);
0762     struct intel_connector *intel_connector = to_intel_connector(connector);
0763     struct intel_dp *intel_dp = intel_connector->mst_port;
0764     struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
0765 
0766     return &intel_dp->mst_encoders[crtc->pipe]->base.base;
0767 }
0768 
0769 static int
0770 intel_dp_mst_detect(struct drm_connector *connector,
0771             struct drm_modeset_acquire_ctx *ctx, bool force)
0772 {
0773     struct drm_i915_private *i915 = to_i915(connector->dev);
0774     struct intel_connector *intel_connector = to_intel_connector(connector);
0775     struct intel_dp *intel_dp = intel_connector->mst_port;
0776 
0777     if (!INTEL_DISPLAY_ENABLED(i915))
0778         return connector_status_disconnected;
0779 
0780     if (drm_connector_is_unregistered(connector))
0781         return connector_status_disconnected;
0782 
0783     return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
0784                       intel_connector->port);
0785 }
0786 
0787 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
0788     .get_modes = intel_dp_mst_get_modes,
0789     .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
0790     .atomic_best_encoder = intel_mst_atomic_best_encoder,
0791     .atomic_check = intel_dp_mst_atomic_check,
0792     .detect_ctx = intel_dp_mst_detect,
0793 };
0794 
0795 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
0796 {
0797     struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
0798 
0799     drm_encoder_cleanup(encoder);
0800     kfree(intel_mst);
0801 }
0802 
0803 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
0804     .destroy = intel_dp_mst_encoder_destroy,
0805 };
0806 
0807 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
0808 {
0809     if (intel_attached_encoder(connector) && connector->base.state->crtc) {
0810         enum pipe pipe;
0811         if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
0812             return false;
0813         return true;
0814     }
0815     return false;
0816 }
0817 
0818 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop)
0819 {
0820     struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
0821     struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
0822     struct drm_device *dev = dig_port->base.base.dev;
0823     struct drm_i915_private *dev_priv = to_i915(dev);
0824     struct intel_connector *intel_connector;
0825     struct drm_connector *connector;
0826     enum pipe pipe;
0827     int ret;
0828 
0829     intel_connector = intel_connector_alloc();
0830     if (!intel_connector)
0831         return NULL;
0832 
0833     intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
0834     intel_connector->mst_port = intel_dp;
0835     intel_connector->port = port;
0836     drm_dp_mst_get_port_malloc(port);
0837 
0838     connector = &intel_connector->base;
0839     ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
0840                  DRM_MODE_CONNECTOR_DisplayPort);
0841     if (ret) {
0842         drm_dp_mst_put_port_malloc(port);
0843         intel_connector_free(intel_connector);
0844         return NULL;
0845     }
0846 
0847     drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
0848 
0849     for_each_pipe(dev_priv, pipe) {
0850         struct drm_encoder *enc =
0851             &intel_dp->mst_encoders[pipe]->base.base;
0852 
0853         ret = drm_connector_attach_encoder(&intel_connector->base, enc);
0854         if (ret)
0855             goto err;
0856     }
0857 
0858     drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
0859     drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
0860 
0861     ret = drm_connector_set_path_property(connector, pathprop);
0862     if (ret)
0863         goto err;
0864 
0865     intel_attach_force_audio_property(connector);
0866     intel_attach_broadcast_rgb_property(connector);
0867 
0868     ret = intel_dp_hdcp_init(dig_port, intel_connector);
0869     if (ret)
0870         drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
0871                 connector->name, connector->base.id);
0872     /*
0873      * Reuse the prop from the SST connector because we're
0874      * not allowed to create new props after device registration.
0875      */
0876     connector->max_bpc_property =
0877         intel_dp->attached_connector->base.max_bpc_property;
0878     if (connector->max_bpc_property)
0879         drm_connector_attach_max_bpc_property(connector, 6, 12);
0880 
0881     return connector;
0882 
0883 err:
0884     drm_connector_cleanup(connector);
0885     return NULL;
0886 }
0887 
0888 static void
0889 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
0890 {
0891     struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
0892 
0893     intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
0894 }
0895 
0896 static const struct drm_dp_mst_topology_cbs mst_cbs = {
0897     .add_connector = intel_dp_add_mst_connector,
0898     .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
0899 };
0900 
0901 static struct intel_dp_mst_encoder *
0902 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
0903 {
0904     struct intel_dp_mst_encoder *intel_mst;
0905     struct intel_encoder *intel_encoder;
0906     struct drm_device *dev = dig_port->base.base.dev;
0907 
0908     intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
0909 
0910     if (!intel_mst)
0911         return NULL;
0912 
0913     intel_mst->pipe = pipe;
0914     intel_encoder = &intel_mst->base;
0915     intel_mst->primary = dig_port;
0916 
0917     drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
0918              DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
0919 
0920     intel_encoder->type = INTEL_OUTPUT_DP_MST;
0921     intel_encoder->power_domain = dig_port->base.power_domain;
0922     intel_encoder->port = dig_port->base.port;
0923     intel_encoder->cloneable = 0;
0924     /*
0925      * This is wrong, but broken userspace uses the intersection
0926      * of possible_crtcs of all the encoders of a given connector
0927      * to figure out which crtcs can drive said connector. What
0928      * should be used instead is the union of possible_crtcs.
0929      * To keep such userspace functioning we must misconfigure
0930      * this to make sure the intersection is not empty :(
0931      */
0932     intel_encoder->pipe_mask = ~0;
0933 
0934     intel_encoder->compute_config = intel_dp_mst_compute_config;
0935     intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
0936     intel_encoder->disable = intel_mst_disable_dp;
0937     intel_encoder->post_disable = intel_mst_post_disable_dp;
0938     intel_encoder->update_pipe = intel_ddi_update_pipe;
0939     intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
0940     intel_encoder->pre_enable = intel_mst_pre_enable_dp;
0941     intel_encoder->enable = intel_mst_enable_dp;
0942     intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
0943     intel_encoder->get_config = intel_dp_mst_enc_get_config;
0944     intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
0945 
0946     return intel_mst;
0947 
0948 }
0949 
0950 static bool
0951 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
0952 {
0953     struct intel_dp *intel_dp = &dig_port->dp;
0954     struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
0955     enum pipe pipe;
0956 
0957     for_each_pipe(dev_priv, pipe)
0958         intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
0959     return true;
0960 }
0961 
0962 int
0963 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
0964 {
0965     return dig_port->dp.active_mst_links;
0966 }
0967 
0968 int
0969 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
0970 {
0971     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0972     struct intel_dp *intel_dp = &dig_port->dp;
0973     enum port port = dig_port->base.port;
0974     int ret;
0975     int max_source_rate =
0976         intel_dp->source_rates[intel_dp->num_source_rates - 1];
0977 
0978     if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
0979         return 0;
0980 
0981     if (DISPLAY_VER(i915) < 12 && port == PORT_A)
0982         return 0;
0983 
0984     if (DISPLAY_VER(i915) < 11 && port == PORT_E)
0985         return 0;
0986 
0987     intel_dp->mst_mgr.cbs = &mst_cbs;
0988 
0989     /* create encoders */
0990     intel_dp_create_fake_mst_encoders(dig_port);
0991     ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
0992                        &intel_dp->aux, 16, 3,
0993                        dig_port->max_lanes,
0994                        max_source_rate,
0995                        conn_base_id);
0996     if (ret) {
0997         intel_dp->mst_mgr.cbs = NULL;
0998         return ret;
0999     }
1000 
1001     return 0;
1002 }
1003 
1004 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1005 {
1006     return intel_dp->mst_mgr.cbs;
1007 }
1008 
1009 void
1010 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1011 {
1012     struct intel_dp *intel_dp = &dig_port->dp;
1013 
1014     if (!intel_dp_mst_source_support(intel_dp))
1015         return;
1016 
1017     drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1018     /* encoders will get killed by normal cleanup */
1019 
1020     intel_dp->mst_mgr.cbs = NULL;
1021 }
1022 
1023 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1024 {
1025     return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1026 }
1027 
1028 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1029 {
1030     return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1031            crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1032 }
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