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0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright (C) 2020 Google, Inc.
0004  *
0005  * Authors:
0006  * Sean Paul <seanpaul@chromium.org>
0007  */
0008 
0009 #include <drm/display/drm_dp_helper.h>
0010 #include <drm/display/drm_dp_mst_helper.h>
0011 #include <drm/display/drm_hdcp_helper.h>
0012 #include <drm/drm_print.h>
0013 
0014 #include "intel_ddi.h"
0015 #include "intel_de.h"
0016 #include "intel_display_types.h"
0017 #include "intel_dp.h"
0018 #include "intel_dp_hdcp.h"
0019 #include "intel_hdcp.h"
0020 
0021 static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
0022 {
0023     u32 stream_enc_mask;
0024 
0025     switch (cpu_transcoder) {
0026     case TRANSCODER_A:
0027         stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
0028         break;
0029     case TRANSCODER_B:
0030         stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
0031         break;
0032     case TRANSCODER_C:
0033         stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
0034         break;
0035     case TRANSCODER_D:
0036         stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
0037         break;
0038     default:
0039         stream_enc_mask = 0;
0040     }
0041 
0042     return stream_enc_mask;
0043 }
0044 
0045 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
0046 {
0047     long ret;
0048 
0049 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
0050     ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
0051                            msecs_to_jiffies(timeout));
0052 
0053     if (!ret)
0054         DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
0055 }
0056 
0057 static
0058 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
0059                 u8 *an)
0060 {
0061     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0062     u8 aksv[DRM_HDCP_KSV_LEN] = {};
0063     ssize_t dpcd_ret;
0064 
0065     /* Output An first, that's easy */
0066     dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
0067                      an, DRM_HDCP_AN_LEN);
0068     if (dpcd_ret != DRM_HDCP_AN_LEN) {
0069         drm_dbg_kms(&i915->drm,
0070                 "Failed to write An over DP/AUX (%zd)\n",
0071                 dpcd_ret);
0072         return dpcd_ret >= 0 ? -EIO : dpcd_ret;
0073     }
0074 
0075     /*
0076      * Since Aksv is Oh-So-Secret, we can't access it in software. So we
0077      * send an empty buffer of the correct length through the DP helpers. On
0078      * the other side, in the transfer hook, we'll generate a flag based on
0079      * the destination address which will tickle the hardware to output the
0080      * Aksv on our behalf after the header is sent.
0081      */
0082     dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
0083                      aksv, DRM_HDCP_KSV_LEN);
0084     if (dpcd_ret != DRM_HDCP_KSV_LEN) {
0085         drm_dbg_kms(&i915->drm,
0086                 "Failed to write Aksv over DP/AUX (%zd)\n",
0087                 dpcd_ret);
0088         return dpcd_ret >= 0 ? -EIO : dpcd_ret;
0089     }
0090     return 0;
0091 }
0092 
0093 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
0094                    u8 *bksv)
0095 {
0096     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0097     ssize_t ret;
0098 
0099     ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
0100                    DRM_HDCP_KSV_LEN);
0101     if (ret != DRM_HDCP_KSV_LEN) {
0102         drm_dbg_kms(&i915->drm,
0103                 "Read Bksv from DP/AUX failed (%zd)\n", ret);
0104         return ret >= 0 ? -EIO : ret;
0105     }
0106     return 0;
0107 }
0108 
0109 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
0110                       u8 *bstatus)
0111 {
0112     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0113     ssize_t ret;
0114 
0115     /*
0116      * For some reason the HDMI and DP HDCP specs call this register
0117      * definition by different names. In the HDMI spec, it's called BSTATUS,
0118      * but in DP it's called BINFO.
0119      */
0120     ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
0121                    bstatus, DRM_HDCP_BSTATUS_LEN);
0122     if (ret != DRM_HDCP_BSTATUS_LEN) {
0123         drm_dbg_kms(&i915->drm,
0124                 "Read bstatus from DP/AUX failed (%zd)\n", ret);
0125         return ret >= 0 ? -EIO : ret;
0126     }
0127     return 0;
0128 }
0129 
0130 static
0131 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
0132                  u8 *bcaps)
0133 {
0134     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0135     ssize_t ret;
0136 
0137     ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
0138                    bcaps, 1);
0139     if (ret != 1) {
0140         drm_dbg_kms(&i915->drm,
0141                 "Read bcaps from DP/AUX failed (%zd)\n", ret);
0142         return ret >= 0 ? -EIO : ret;
0143     }
0144 
0145     return 0;
0146 }
0147 
0148 static
0149 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
0150                    bool *repeater_present)
0151 {
0152     ssize_t ret;
0153     u8 bcaps;
0154 
0155     ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
0156     if (ret)
0157         return ret;
0158 
0159     *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
0160     return 0;
0161 }
0162 
0163 static
0164 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
0165                 u8 *ri_prime)
0166 {
0167     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0168     ssize_t ret;
0169 
0170     ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
0171                    ri_prime, DRM_HDCP_RI_LEN);
0172     if (ret != DRM_HDCP_RI_LEN) {
0173         drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
0174                 ret);
0175         return ret >= 0 ? -EIO : ret;
0176     }
0177     return 0;
0178 }
0179 
0180 static
0181 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
0182                  bool *ksv_ready)
0183 {
0184     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0185     ssize_t ret;
0186     u8 bstatus;
0187 
0188     ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
0189                    &bstatus, 1);
0190     if (ret != 1) {
0191         drm_dbg_kms(&i915->drm,
0192                 "Read bstatus from DP/AUX failed (%zd)\n", ret);
0193         return ret >= 0 ? -EIO : ret;
0194     }
0195     *ksv_ready = bstatus & DP_BSTATUS_READY;
0196     return 0;
0197 }
0198 
0199 static
0200 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
0201                 int num_downstream, u8 *ksv_fifo)
0202 {
0203     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0204     ssize_t ret;
0205     int i;
0206 
0207     /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
0208     for (i = 0; i < num_downstream; i += 3) {
0209         size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
0210         ret = drm_dp_dpcd_read(&dig_port->dp.aux,
0211                        DP_AUX_HDCP_KSV_FIFO,
0212                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
0213                        len);
0214         if (ret != len) {
0215             drm_dbg_kms(&i915->drm,
0216                     "Read ksv[%d] from DP/AUX failed (%zd)\n",
0217                     i, ret);
0218             return ret >= 0 ? -EIO : ret;
0219         }
0220     }
0221     return 0;
0222 }
0223 
0224 static
0225 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
0226                     int i, u32 *part)
0227 {
0228     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0229     ssize_t ret;
0230 
0231     if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
0232         return -EINVAL;
0233 
0234     ret = drm_dp_dpcd_read(&dig_port->dp.aux,
0235                    DP_AUX_HDCP_V_PRIME(i), part,
0236                    DRM_HDCP_V_PRIME_PART_LEN);
0237     if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
0238         drm_dbg_kms(&i915->drm,
0239                 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
0240         return ret >= 0 ? -EIO : ret;
0241     }
0242     return 0;
0243 }
0244 
0245 static
0246 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
0247                     enum transcoder cpu_transcoder,
0248                     bool enable)
0249 {
0250     /* Not used for single stream DisplayPort setups */
0251     return 0;
0252 }
0253 
0254 static
0255 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
0256                   struct intel_connector *connector)
0257 {
0258     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0259     ssize_t ret;
0260     u8 bstatus;
0261 
0262     ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
0263                    &bstatus, 1);
0264     if (ret != 1) {
0265         drm_dbg_kms(&i915->drm,
0266                 "Read bstatus from DP/AUX failed (%zd)\n", ret);
0267         return false;
0268     }
0269 
0270     return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
0271 }
0272 
0273 static
0274 int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
0275               bool *hdcp_capable)
0276 {
0277     ssize_t ret;
0278     u8 bcaps;
0279 
0280     ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
0281     if (ret)
0282         return ret;
0283 
0284     *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
0285     return 0;
0286 }
0287 
0288 struct hdcp2_dp_errata_stream_type {
0289     u8  msg_id;
0290     u8  stream_type;
0291 } __packed;
0292 
0293 struct hdcp2_dp_msg_data {
0294     u8 msg_id;
0295     u32 offset;
0296     bool msg_detectable;
0297     u32 timeout;
0298     u32 timeout2; /* Added for non_paired situation */
0299     /* Timeout to read entire msg */
0300     u32 msg_read_timeout;
0301 };
0302 
0303 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
0304     { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
0305     { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
0306       false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
0307     { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
0308       false, 0, 0, 0 },
0309     { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
0310       false, 0, 0, 0 },
0311     { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
0312       true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
0313       HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS},
0314     { HDCP_2_2_AKE_SEND_PAIRING_INFO,
0315       DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
0316       HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS },
0317     { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
0318     { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
0319       false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
0320     { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
0321       0, 0, 0 },
0322     { HDCP_2_2_REP_SEND_RECVID_LIST,
0323       DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
0324       HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 },
0325     { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
0326       0, 0, 0 },
0327     { HDCP_2_2_REP_STREAM_MANAGE,
0328       DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
0329       0, 0, 0},
0330     { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
0331       false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
0332 /* local define to shovel this through the write_2_2 interface */
0333 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
0334     { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
0335       DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
0336       0, 0 },
0337 };
0338 
0339 static int
0340 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
0341                   u8 *rx_status)
0342 {
0343     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0344     ssize_t ret;
0345 
0346     ret = drm_dp_dpcd_read(&dig_port->dp.aux,
0347                    DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
0348                    HDCP_2_2_DP_RXSTATUS_LEN);
0349     if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
0350         drm_dbg_kms(&i915->drm,
0351                 "Read bstatus from DP/AUX failed (%zd)\n", ret);
0352         return ret >= 0 ? -EIO : ret;
0353     }
0354 
0355     return 0;
0356 }
0357 
0358 static
0359 int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
0360                   u8 msg_id, bool *msg_ready)
0361 {
0362     u8 rx_status;
0363     int ret;
0364 
0365     *msg_ready = false;
0366     ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
0367     if (ret < 0)
0368         return ret;
0369 
0370     switch (msg_id) {
0371     case HDCP_2_2_AKE_SEND_HPRIME:
0372         if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
0373             *msg_ready = true;
0374         break;
0375     case HDCP_2_2_AKE_SEND_PAIRING_INFO:
0376         if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
0377             *msg_ready = true;
0378         break;
0379     case HDCP_2_2_REP_SEND_RECVID_LIST:
0380         if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
0381             *msg_ready = true;
0382         break;
0383     default:
0384         DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
0385         return -EINVAL;
0386     }
0387 
0388     return 0;
0389 }
0390 
0391 static ssize_t
0392 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
0393                 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
0394 {
0395     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0396     struct intel_dp *dp = &dig_port->dp;
0397     struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
0398     u8 msg_id = hdcp2_msg_data->msg_id;
0399     int ret, timeout;
0400     bool msg_ready = false;
0401 
0402     if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
0403         timeout = hdcp2_msg_data->timeout2;
0404     else
0405         timeout = hdcp2_msg_data->timeout;
0406 
0407     /*
0408      * There is no way to detect the CERT, LPRIME and STREAM_READY
0409      * availability. So Wait for timeout and read the msg.
0410      */
0411     if (!hdcp2_msg_data->msg_detectable) {
0412         mdelay(timeout);
0413         ret = 0;
0414     } else {
0415         /*
0416          * As we want to check the msg availability at timeout, Ignoring
0417          * the timeout at wait for CP_IRQ.
0418          */
0419         intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
0420         ret = hdcp2_detect_msg_availability(dig_port,
0421                             msg_id, &msg_ready);
0422         if (!msg_ready)
0423             ret = -ETIMEDOUT;
0424     }
0425 
0426     if (ret)
0427         drm_dbg_kms(&i915->drm,
0428                 "msg_id %d, ret %d, timeout(mSec): %d\n",
0429                 hdcp2_msg_data->msg_id, ret, timeout);
0430 
0431     return ret;
0432 }
0433 
0434 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
0435 {
0436     int i;
0437 
0438     for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
0439         if (hdcp2_dp_msg_data[i].msg_id == msg_id)
0440             return &hdcp2_dp_msg_data[i];
0441 
0442     return NULL;
0443 }
0444 
0445 static
0446 int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
0447                  void *buf, size_t size)
0448 {
0449     unsigned int offset;
0450     u8 *byte = buf;
0451     ssize_t ret, bytes_to_write, len;
0452     const struct hdcp2_dp_msg_data *hdcp2_msg_data;
0453 
0454     hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
0455     if (!hdcp2_msg_data)
0456         return -EINVAL;
0457 
0458     offset = hdcp2_msg_data->offset;
0459 
0460     /* No msg_id in DP HDCP2.2 msgs */
0461     bytes_to_write = size - 1;
0462     byte++;
0463 
0464     while (bytes_to_write) {
0465         len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
0466                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
0467 
0468         ret = drm_dp_dpcd_write(&dig_port->dp.aux,
0469                     offset, (void *)byte, len);
0470         if (ret < 0)
0471             return ret;
0472 
0473         bytes_to_write -= ret;
0474         byte += ret;
0475         offset += ret;
0476     }
0477 
0478     return size;
0479 }
0480 
0481 static
0482 ssize_t get_receiver_id_list_rx_info(struct intel_digital_port *dig_port, u32 *dev_cnt, u8 *byte)
0483 {
0484     ssize_t ret;
0485     u8 *rx_info = byte;
0486 
0487     ret = drm_dp_dpcd_read(&dig_port->dp.aux,
0488                    DP_HDCP_2_2_REG_RXINFO_OFFSET,
0489                    (void *)rx_info, HDCP_2_2_RXINFO_LEN);
0490     if (ret != HDCP_2_2_RXINFO_LEN)
0491         return ret >= 0 ? -EIO : ret;
0492 
0493     *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
0494            HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
0495 
0496     if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
0497         *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
0498 
0499     return ret;
0500 }
0501 
0502 static
0503 int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
0504                 u8 msg_id, void *buf, size_t size)
0505 {
0506     struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
0507     struct intel_dp *dp = &dig_port->dp;
0508     struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
0509     unsigned int offset;
0510     u8 *byte = buf;
0511     ssize_t ret, bytes_to_recv, len;
0512     const struct hdcp2_dp_msg_data *hdcp2_msg_data;
0513     ktime_t msg_end = ktime_set(0, 0);
0514     bool msg_expired;
0515     u32 dev_cnt;
0516 
0517     hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
0518     if (!hdcp2_msg_data)
0519         return -EINVAL;
0520     offset = hdcp2_msg_data->offset;
0521 
0522     ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
0523     if (ret < 0)
0524         return ret;
0525 
0526     hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
0527 
0528     /* DP adaptation msgs has no msg_id */
0529     byte++;
0530 
0531     if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
0532         ret = get_receiver_id_list_rx_info(dig_port, &dev_cnt, byte);
0533         if (ret < 0)
0534             return ret;
0535 
0536         byte += ret;
0537         size = sizeof(struct hdcp2_rep_send_receiverid_list) -
0538         HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN +
0539         (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
0540         offset += HDCP_2_2_RXINFO_LEN;
0541     }
0542 
0543     bytes_to_recv = size - 1;
0544 
0545     while (bytes_to_recv) {
0546         len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
0547               DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
0548 
0549         /* Entire msg read timeout since initiate of msg read */
0550         if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0)
0551             msg_end = ktime_add_ms(ktime_get_raw(),
0552                            hdcp2_msg_data->msg_read_timeout);
0553 
0554         ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
0555                        (void *)byte, len);
0556         if (ret < 0) {
0557             drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
0558                     msg_id, ret);
0559             return ret;
0560         }
0561 
0562         bytes_to_recv -= ret;
0563         byte += ret;
0564         offset += ret;
0565     }
0566 
0567     if (hdcp2_msg_data->msg_read_timeout > 0) {
0568         msg_expired = ktime_after(ktime_get_raw(), msg_end);
0569         if (msg_expired) {
0570             drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
0571                     msg_id, hdcp2_msg_data->msg_read_timeout);
0572             return -ETIMEDOUT;
0573         }
0574     }
0575 
0576     byte = buf;
0577     *byte = msg_id;
0578 
0579     return size;
0580 }
0581 
0582 static
0583 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
0584                       bool is_repeater, u8 content_type)
0585 {
0586     int ret;
0587     struct hdcp2_dp_errata_stream_type stream_type_msg;
0588 
0589     if (is_repeater)
0590         return 0;
0591 
0592     /*
0593      * Errata for DP: As Stream type is used for encryption, Receiver
0594      * should be communicated with stream type for the decryption of the
0595      * content.
0596      * Repeater will be communicated with stream type as a part of it's
0597      * auth later in time.
0598      */
0599     stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
0600     stream_type_msg.stream_type = content_type;
0601 
0602     ret =  intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
0603                     sizeof(stream_type_msg));
0604 
0605     return ret < 0 ? ret : 0;
0606 
0607 }
0608 
0609 static
0610 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
0611                   struct intel_connector *connector)
0612 {
0613     u8 rx_status;
0614     int ret;
0615 
0616     ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
0617     if (ret)
0618         return ret;
0619 
0620     if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
0621         ret = HDCP_REAUTH_REQUEST;
0622     else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
0623         ret = HDCP_LINK_INTEGRITY_FAILURE;
0624     else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
0625         ret = HDCP_TOPOLOGY_CHANGE;
0626 
0627     return ret;
0628 }
0629 
0630 static
0631 int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
0632                bool *capable)
0633 {
0634     u8 rx_caps[3];
0635     int ret;
0636 
0637     *capable = false;
0638     ret = drm_dp_dpcd_read(&dig_port->dp.aux,
0639                    DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
0640                    rx_caps, HDCP_2_2_RXCAPS_LEN);
0641     if (ret != HDCP_2_2_RXCAPS_LEN)
0642         return ret >= 0 ? -EIO : ret;
0643 
0644     if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
0645         HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
0646         *capable = true;
0647 
0648     return 0;
0649 }
0650 
0651 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
0652     .write_an_aksv = intel_dp_hdcp_write_an_aksv,
0653     .read_bksv = intel_dp_hdcp_read_bksv,
0654     .read_bstatus = intel_dp_hdcp_read_bstatus,
0655     .repeater_present = intel_dp_hdcp_repeater_present,
0656     .read_ri_prime = intel_dp_hdcp_read_ri_prime,
0657     .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
0658     .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
0659     .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
0660     .toggle_signalling = intel_dp_hdcp_toggle_signalling,
0661     .check_link = intel_dp_hdcp_check_link,
0662     .hdcp_capable = intel_dp_hdcp_capable,
0663     .write_2_2_msg = intel_dp_hdcp2_write_msg,
0664     .read_2_2_msg = intel_dp_hdcp2_read_msg,
0665     .config_stream_type = intel_dp_hdcp2_config_stream_type,
0666     .check_2_2_link = intel_dp_hdcp2_check_link,
0667     .hdcp_2_2_capable = intel_dp_hdcp2_capable,
0668     .protocol = HDCP_PROTOCOL_DP,
0669 };
0670 
0671 static int
0672 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
0673                        bool enable)
0674 {
0675     struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
0676     struct drm_i915_private *i915 = to_i915(connector->base.dev);
0677     struct intel_hdcp *hdcp = &connector->hdcp;
0678     int ret;
0679 
0680     ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
0681                      hdcp->stream_transcoder, enable,
0682                      TRANS_DDI_HDCP_SELECT);
0683     if (ret)
0684         drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
0685             enable ? "Enable" : "Disable", ret);
0686     return ret;
0687 }
0688 
0689 static int
0690 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
0691                     bool enable)
0692 {
0693     struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
0694     struct drm_i915_private *i915 = to_i915(connector->base.dev);
0695     struct intel_hdcp *hdcp = &connector->hdcp;
0696     enum port port = dig_port->base.port;
0697     enum transcoder cpu_transcoder = hdcp->stream_transcoder;
0698     u32 stream_enc_status;
0699     int ret;
0700 
0701     ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
0702     if (ret)
0703         return ret;
0704 
0705     stream_enc_status =  transcoder_to_stream_enc_status(cpu_transcoder);
0706     if (!stream_enc_status)
0707         return -EINVAL;
0708 
0709     /* Wait for encryption confirmation */
0710     if (intel_de_wait_for_register(i915,
0711                        HDCP_STATUS(i915, cpu_transcoder, port),
0712                        stream_enc_status,
0713                        enable ? stream_enc_status : 0,
0714                        HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
0715         drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
0716             transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
0717         return -ETIMEDOUT;
0718     }
0719 
0720     return 0;
0721 }
0722 
0723 static int
0724 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
0725                      bool enable)
0726 {
0727     struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
0728     struct drm_i915_private *i915 = to_i915(connector->base.dev);
0729     struct hdcp_port_data *data = &dig_port->hdcp_port_data;
0730     struct intel_hdcp *hdcp = &connector->hdcp;
0731     enum transcoder cpu_transcoder = hdcp->stream_transcoder;
0732     enum pipe pipe = (enum pipe)cpu_transcoder;
0733     enum port port = dig_port->base.port;
0734     int ret;
0735 
0736     drm_WARN_ON(&i915->drm, enable &&
0737             !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
0738             & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
0739 
0740     ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
0741     if (ret)
0742         return ret;
0743 
0744     /* Wait for encryption confirmation */
0745     if (intel_de_wait_for_register(i915,
0746                        HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
0747                        STREAM_ENCRYPTION_STATUS,
0748                        enable ? STREAM_ENCRYPTION_STATUS : 0,
0749                        HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
0750         drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
0751             transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
0752         return -ETIMEDOUT;
0753     }
0754 
0755     return 0;
0756 }
0757 
0758 static
0759 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
0760                   struct intel_connector *connector)
0761 {
0762     struct intel_hdcp *hdcp = &connector->hdcp;
0763     int ret;
0764 
0765     /*
0766      * We do need to do the Link Check only for the connector involved with
0767      * HDCP port authentication and encryption.
0768      * We can re-use the hdcp->is_repeater flag to know that the connector
0769      * involved with HDCP port authentication and encryption.
0770      */
0771     if (hdcp->is_repeater) {
0772         ret = intel_dp_hdcp2_check_link(dig_port, connector);
0773         if (ret)
0774             return ret;
0775     }
0776 
0777     return 0;
0778 }
0779 
0780 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
0781     .write_an_aksv = intel_dp_hdcp_write_an_aksv,
0782     .read_bksv = intel_dp_hdcp_read_bksv,
0783     .read_bstatus = intel_dp_hdcp_read_bstatus,
0784     .repeater_present = intel_dp_hdcp_repeater_present,
0785     .read_ri_prime = intel_dp_hdcp_read_ri_prime,
0786     .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
0787     .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
0788     .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
0789     .toggle_signalling = intel_dp_hdcp_toggle_signalling,
0790     .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
0791     .check_link = intel_dp_hdcp_check_link,
0792     .hdcp_capable = intel_dp_hdcp_capable,
0793     .write_2_2_msg = intel_dp_hdcp2_write_msg,
0794     .read_2_2_msg = intel_dp_hdcp2_read_msg,
0795     .config_stream_type = intel_dp_hdcp2_config_stream_type,
0796     .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
0797     .check_2_2_link = intel_dp_mst_hdcp2_check_link,
0798     .hdcp_2_2_capable = intel_dp_hdcp2_capable,
0799     .protocol = HDCP_PROTOCOL_DP,
0800 };
0801 
0802 int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
0803                struct intel_connector *intel_connector)
0804 {
0805     struct drm_device *dev = intel_connector->base.dev;
0806     struct drm_i915_private *dev_priv = to_i915(dev);
0807     struct intel_encoder *intel_encoder = &dig_port->base;
0808     enum port port = intel_encoder->port;
0809     struct intel_dp *intel_dp = &dig_port->dp;
0810 
0811     if (!is_hdcp_supported(dev_priv, port))
0812         return 0;
0813 
0814     if (intel_connector->mst_port)
0815         return intel_hdcp_init(intel_connector, dig_port,
0816                        &intel_dp_mst_hdcp_shim);
0817     else if (!intel_dp_is_edp(intel_dp))
0818         return intel_hdcp_init(intel_connector, dig_port,
0819                        &intel_dp_hdcp_shim);
0820 
0821     return 0;
0822 }
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