i915/display/intel_dmc_regs.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_DMC_REGS_H__
0007 #define __INTEL_DMC_REGS_H__
0008
0009 #include "i915_reg_defs.h"
0010
0011 #define DMC_PROGRAM(addr, i)    _MMIO((addr) + (i) * 4)
0012 #define DMC_SSP_BASE_ADDR_GEN9  0x00002FC0
0013
0014 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A   0x5f000
0015 #define _TGL_PIPEDMC_REG_MMIO_BASE_A    0x92000
0016
0017 #define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) \
0018     ((DISPLAY_VER(i915) >= 13 ? _ADLP_PIPEDMC_REG_MMIO_BASE_A : \
0019                     _TGL_PIPEDMC_REG_MMIO_BASE_A) + \
0020      0x400 * ((dmc_id) - 1))
0021
0022 #define __DMC_REG_MMIO_BASE     0x8f000
0023
0024 #define _DMC_REG_MMIO_BASE(i915, dmc_id) \
0025     ((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \
0026                    __PIPEDMC_REG_MMIO_BASE(i915, dmc_id))
0027
0028 #define _DMC_REG(i915, dmc_id, reg) \
0029     ((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id))
0030
0031 #define _DMC_EVT_HTP_0          0x8f004
0032
0033 #define DMC_EVT_HTP(i915, dmc_id, handler) \
0034     _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))
0035
0036 #define _DMC_EVT_CTL_0          0x8f034
0037
0038 #define DMC_EVT_CTL(i915, dmc_id, handler) \
0039     _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))
0040
0041 #define DMC_EVT_CTL_ENABLE      REG_BIT(31)
0042 #define DMC_EVT_CTL_RECURRING       REG_BIT(30)
0043 #define DMC_EVT_CTL_TYPE_MASK       REG_GENMASK(17, 16)
0044 #define DMC_EVT_CTL_TYPE_LEVEL_0    0
0045 #define DMC_EVT_CTL_TYPE_LEVEL_1    1
0046 #define DMC_EVT_CTL_TYPE_EDGE_1_0   2
0047 #define DMC_EVT_CTL_TYPE_EDGE_0_1   3
0048
0049 #define DMC_EVT_CTL_EVENT_ID_MASK   REG_GENMASK(15, 8)
0050 #define DMC_EVT_CTL_EVENT_ID_FALSE  0x01
0051 /* An event handler scheduled to run at a 1 kHz frequency. */
0052 #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC   0xbf
0053
0054 #define DMC_HTP_ADDR_SKL    0x00500034
0055 #define DMC_SSP_BASE        _MMIO(0x8F074)
0056 #define DMC_HTP_SKL     _MMIO(0x8F004)
0057 #define DMC_LAST_WRITE      _MMIO(0x8F034)
0058 #define DMC_LAST_WRITE_VALUE    0xc003b400
0059 #define DMC_MMIO_START_RANGE    0x80000
0060 #define DMC_MMIO_END_RANGE     0x8FFFF
0061 #define DMC_V1_MMIO_START_RANGE     0x80000
0062 #define TGL_MAIN_MMIO_START     0x8F000
0063 #define TGL_MAIN_MMIO_END       0x8FFFF
0064 #define _TGL_PIPEA_MMIO_START       0x92000
0065 #define _TGL_PIPEA_MMIO_END     0x93FFF
0066 #define _TGL_PIPEB_MMIO_START       0x96000
0067 #define _TGL_PIPEB_MMIO_END     0x97FFF
0068 #define ADLP_PIPE_MMIO_START        0x5F000
0069 #define ADLP_PIPE_MMIO_END      0x5FFFF
0070
0071 #define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
0072                           _TGL_PIPEB_MMIO_START)
0073
0074 #define TGL_PIPE_MMIO_END(dmc_id)   _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\
0075                           _TGL_PIPEB_MMIO_END)
0076
0077 #define SKL_DMC_DC3_DC5_COUNT   _MMIO(0x80030)
0078 #define SKL_DMC_DC5_DC6_COUNT   _MMIO(0x8002C)
0079 #define BXT_DMC_DC3_DC5_COUNT   _MMIO(0x80038)
0080 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
0081 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
0082 #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
0083
0084 #define TGL_DMC_DEBUG3      _MMIO(0x101090)
0085 #define DG1_DMC_DEBUG3      _MMIO(0x13415c)
0086
0087 #endif /* __INTEL_DMC_REGS_H__ */