i915/display/intel_dmc.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_DMC_H__
0007 #define __INTEL_DMC_H__
0008
0009 #include "i915_reg_defs.h"
0010 #include "intel_wakeref.h"
0011 #include <linux/workqueue.h>
0012
0013 struct drm_i915_error_state_buf;
0014 struct drm_i915_private;
0015
0016 enum {
0017     DMC_FW_MAIN = 0,
0018     DMC_FW_PIPEA,
0019     DMC_FW_PIPEB,
0020     DMC_FW_PIPEC,
0021     DMC_FW_PIPED,
0022     DMC_FW_MAX
0023 };
0024
0025 struct intel_dmc {
0026     struct work_struct work;
0027     const char *fw_path;
0028     u32 required_version;
0029     u32 max_fw_size; /* bytes */
0030     u32 version;
0031     struct dmc_fw_info {
0032         u32 mmio_count;
0033         i915_reg_t mmioaddr[20];
0034         u32 mmiodata[20];
0035         u32 dmc_offset;
0036         u32 start_mmioaddr;
0037         u32 dmc_fw_size; /*dwords */
0038         u32 *payload;
0039         bool present;
0040     } dmc_info[DMC_FW_MAX];
0041
0042     u32 dc_state;
0043     u32 target_dc_state;
0044     u32 allowed_dc_mask;
0045     intel_wakeref_t wakeref;
0046 };
0047
0048 void intel_dmc_ucode_init(struct drm_i915_private *i915);
0049 void intel_dmc_load_program(struct drm_i915_private *i915);
0050 void intel_dmc_ucode_fini(struct drm_i915_private *i915);
0051 void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
0052 void intel_dmc_ucode_resume(struct drm_i915_private *i915);
0053 bool intel_dmc_has_payload(struct drm_i915_private *i915);
0054 void intel_dmc_debugfs_register(struct drm_i915_private *i915);
0055 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
0056                  struct drm_i915_private *i915);
0057
0058 void assert_dmc_loaded(struct drm_i915_private *i915);
0059
0060 #endif /* __INTEL_DMC_H__ */