i915/display/intel_display_power_well.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005 #ifndef __INTEL_DISPLAY_POWER_WELL_H__
0006 #define __INTEL_DISPLAY_POWER_WELL_H__
0007
0008 #include <linux/types.h>
0009
0010 #include "intel_display.h"
0011 #include "intel_display_power.h"
0012
0013 struct drm_i915_private;
0014 struct i915_power_well;
0015
0016 #define for_each_power_well(__dev_priv, __power_well)               \
0017     for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
0018          (__power_well) - (__dev_priv)->power_domains.power_wells < \
0019         (__dev_priv)->power_domains.power_well_count;       \
0020          (__power_well)++)
0021
0022 #define for_each_power_well_reverse(__dev_priv, __power_well)           \
0023     for ((__power_well) = (__dev_priv)->power_domains.power_wells +     \
0024                   (__dev_priv)->power_domains.power_well_count - 1; \
0025          (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
0026          (__power_well)--)
0027
0028 /*
0029  * i915_power_well_id:
0030  *
0031  * IDs used to look up power wells. Power wells accessed directly bypassing
0032  * the power domains framework must be assigned a unique ID. The rest of power
0033  * wells must be assigned DISP_PW_ID_NONE.
0034  */
0035 enum i915_power_well_id {
0036     DISP_PW_ID_NONE = 0,        /* must be kept zero */
0037
0038     VLV_DISP_PW_DISP2D,
0039     BXT_DISP_PW_DPIO_CMN_A,
0040     VLV_DISP_PW_DPIO_CMN_BC,
0041     GLK_DISP_PW_DPIO_CMN_C,
0042     CHV_DISP_PW_DPIO_CMN_D,
0043     HSW_DISP_PW_GLOBAL,
0044     SKL_DISP_PW_MISC_IO,
0045     SKL_DISP_PW_1,
0046     SKL_DISP_PW_2,
0047     ICL_DISP_PW_3,
0048     SKL_DISP_DC_OFF,
0049     TGL_DISP_PW_TC_COLD_OFF,
0050 };
0051
0052 struct i915_power_well_instance {
0053     const char *name;
0054     const struct i915_power_domain_list {
0055         const enum intel_display_power_domain *list;
0056         u8 count;
0057     } *domain_list;
0058
0059     /* unique identifier for this power well */
0060     enum i915_power_well_id id;
0061     /*
0062      * Arbitraty data associated with this power well. Platform and power
0063      * well specific.
0064      */
0065     union {
0066         struct {
0067             /*
0068              * request/status flag index in the PUNIT power well
0069              * control/status registers.
0070              */
0071             u8 idx;
0072         } vlv;
0073         struct {
0074             enum dpio_phy phy;
0075         } bxt;
0076         struct {
0077             /*
0078              * request/status flag index in the power well
0079              * constrol/status registers.
0080              */
0081             u8 idx;
0082         } hsw;
0083     };
0084 };
0085
0086 struct i915_power_well_desc {
0087     const struct i915_power_well_ops *ops;
0088     const struct i915_power_well_instance_list {
0089         const struct i915_power_well_instance *list;
0090         u8 count;
0091     } *instances;
0092
0093     /* Mask of pipes whose IRQ logic is backed by the pw */
0094     u16 irq_pipe_mask:4;
0095     u16 always_on:1;
0096     /*
0097      * Instead of waiting for the status bit to ack enables,
0098      * just wait a specific amount of time and then consider
0099      * the well enabled.
0100      */
0101     u16 fixed_enable_delay:1;
0102     /* The pw is backing the VGA functionality */
0103     u16 has_vga:1;
0104     u16 has_fuses:1;
0105     /*
0106      * The pw is for an ICL+ TypeC PHY port in
0107      * Thunderbolt mode.
0108      */
0109     u16 is_tc_tbt:1;
0110 };
0111
0112 struct i915_power_well {
0113     const struct i915_power_well_desc *desc;
0114     struct intel_power_domain_mask domains;
0115     /* power well enable/disable usage count */
0116     int count;
0117     /* cached hw enabled state */
0118     bool hw_enabled;
0119     /* index into desc->instances->list */
0120     u8 instance_idx;
0121 };
0122
0123 struct i915_power_well *lookup_power_well(struct drm_i915_private *i915,
0124                       enum i915_power_well_id id);
0125
0126 void intel_power_well_enable(struct drm_i915_private *i915,
0127                  struct i915_power_well *power_well);
0128 void intel_power_well_disable(struct drm_i915_private *i915,
0129                   struct i915_power_well *power_well);
0130 void intel_power_well_sync_hw(struct drm_i915_private *i915,
0131                   struct i915_power_well *power_well);
0132 void intel_power_well_get(struct drm_i915_private *i915,
0133               struct i915_power_well *power_well);
0134 void intel_power_well_put(struct drm_i915_private *i915,
0135               struct i915_power_well *power_well);
0136 bool intel_power_well_is_enabled(struct drm_i915_private *i915,
0137                  struct i915_power_well *power_well);
0138 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well);
0139 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
0140                      enum i915_power_well_id power_well_id);
0141 bool intel_power_well_is_always_on(struct i915_power_well *power_well);
0142 const char *intel_power_well_name(struct i915_power_well *power_well);
0143 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well);
0144 int intel_power_well_refcount(struct i915_power_well *power_well);
0145
0146 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
0147                  bool override, unsigned int mask);
0148 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
0149               enum dpio_channel ch, bool override);
0150
0151 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
0152 void skl_enable_dc6(struct drm_i915_private *dev_priv);
0153 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
0154 void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state);
0155 void gen9_disable_dc_states(struct drm_i915_private *dev_priv);
0156 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
0157 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
0158
0159 extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
0160 extern const struct i915_power_well_ops chv_pipe_power_well_ops;
0161 extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
0162 extern const struct i915_power_well_ops i830_pipes_power_well_ops;
0163 extern const struct i915_power_well_ops hsw_power_well_ops;
0164 extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
0165 extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
0166 extern const struct i915_power_well_ops vlv_display_power_well_ops;
0167 extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
0168 extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
0169 extern const struct i915_power_well_ops icl_aux_power_well_ops;
0170 extern const struct i915_power_well_ops icl_ddi_power_well_ops;
0171 extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
0172
0173 #endif