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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005 
0006 #include "i915_drv.h"
0007 #include "i915_irq.h"
0008 #include "intel_combo_phy.h"
0009 #include "intel_combo_phy_regs.h"
0010 #include "intel_crt.h"
0011 #include "intel_de.h"
0012 #include "intel_display_power_well.h"
0013 #include "intel_display_types.h"
0014 #include "intel_dmc.h"
0015 #include "intel_dpio_phy.h"
0016 #include "intel_dpll.h"
0017 #include "intel_hotplug.h"
0018 #include "intel_pcode.h"
0019 #include "intel_pm.h"
0020 #include "intel_pps.h"
0021 #include "intel_tc.h"
0022 #include "intel_vga.h"
0023 #include "vlv_sideband.h"
0024 #include "vlv_sideband_reg.h"
0025 
0026 struct i915_power_well_regs {
0027     i915_reg_t bios;
0028     i915_reg_t driver;
0029     i915_reg_t kvmr;
0030     i915_reg_t debug;
0031 };
0032 
0033 struct i915_power_well_ops {
0034     const struct i915_power_well_regs *regs;
0035     /*
0036      * Synchronize the well's hw state to match the current sw state, for
0037      * example enable/disable it based on the current refcount. Called
0038      * during driver init and resume time, possibly after first calling
0039      * the enable/disable handlers.
0040      */
0041     void (*sync_hw)(struct drm_i915_private *i915,
0042             struct i915_power_well *power_well);
0043     /*
0044      * Enable the well and resources that depend on it (for example
0045      * interrupts located on the well). Called after the 0->1 refcount
0046      * transition.
0047      */
0048     void (*enable)(struct drm_i915_private *i915,
0049                struct i915_power_well *power_well);
0050     /*
0051      * Disable the well and resources that depend on it. Called after
0052      * the 1->0 refcount transition.
0053      */
0054     void (*disable)(struct drm_i915_private *i915,
0055             struct i915_power_well *power_well);
0056     /* Returns the hw enabled state. */
0057     bool (*is_enabled)(struct drm_i915_private *i915,
0058                struct i915_power_well *power_well);
0059 };
0060 
0061 static const struct i915_power_well_instance *
0062 i915_power_well_instance(const struct i915_power_well *power_well)
0063 {
0064     return &power_well->desc->instances->list[power_well->instance_idx];
0065 }
0066 
0067 struct i915_power_well *
0068 lookup_power_well(struct drm_i915_private *i915,
0069           enum i915_power_well_id power_well_id)
0070 {
0071     struct i915_power_well *power_well;
0072 
0073     for_each_power_well(i915, power_well)
0074         if (i915_power_well_instance(power_well)->id == power_well_id)
0075             return power_well;
0076 
0077     /*
0078      * It's not feasible to add error checking code to the callers since
0079      * this condition really shouldn't happen and it doesn't even make sense
0080      * to abort things like display initialization sequences. Just return
0081      * the first power well and hope the WARN gets reported so we can fix
0082      * our driver.
0083      */
0084     drm_WARN(&i915->drm, 1,
0085          "Power well %d not defined for this platform\n",
0086          power_well_id);
0087     return &i915->power_domains.power_wells[0];
0088 }
0089 
0090 void intel_power_well_enable(struct drm_i915_private *i915,
0091                  struct i915_power_well *power_well)
0092 {
0093     drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well));
0094     power_well->desc->ops->enable(i915, power_well);
0095     power_well->hw_enabled = true;
0096 }
0097 
0098 void intel_power_well_disable(struct drm_i915_private *i915,
0099                   struct i915_power_well *power_well)
0100 {
0101     drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well));
0102     power_well->hw_enabled = false;
0103     power_well->desc->ops->disable(i915, power_well);
0104 }
0105 
0106 void intel_power_well_sync_hw(struct drm_i915_private *i915,
0107                   struct i915_power_well *power_well)
0108 {
0109     power_well->desc->ops->sync_hw(i915, power_well);
0110     power_well->hw_enabled =
0111         power_well->desc->ops->is_enabled(i915, power_well);
0112 }
0113 
0114 void intel_power_well_get(struct drm_i915_private *i915,
0115               struct i915_power_well *power_well)
0116 {
0117     if (!power_well->count++)
0118         intel_power_well_enable(i915, power_well);
0119 }
0120 
0121 void intel_power_well_put(struct drm_i915_private *i915,
0122               struct i915_power_well *power_well)
0123 {
0124     drm_WARN(&i915->drm, !power_well->count,
0125          "Use count on power well %s is already zero",
0126          i915_power_well_instance(power_well)->name);
0127 
0128     if (!--power_well->count)
0129         intel_power_well_disable(i915, power_well);
0130 }
0131 
0132 bool intel_power_well_is_enabled(struct drm_i915_private *i915,
0133                  struct i915_power_well *power_well)
0134 {
0135     return power_well->desc->ops->is_enabled(i915, power_well);
0136 }
0137 
0138 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well)
0139 {
0140     return power_well->hw_enabled;
0141 }
0142 
0143 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
0144                      enum i915_power_well_id power_well_id)
0145 {
0146     struct i915_power_well *power_well;
0147 
0148     power_well = lookup_power_well(dev_priv, power_well_id);
0149 
0150     return intel_power_well_is_enabled(dev_priv, power_well);
0151 }
0152 
0153 bool intel_power_well_is_always_on(struct i915_power_well *power_well)
0154 {
0155     return power_well->desc->always_on;
0156 }
0157 
0158 const char *intel_power_well_name(struct i915_power_well *power_well)
0159 {
0160     return i915_power_well_instance(power_well)->name;
0161 }
0162 
0163 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well)
0164 {
0165     return &power_well->domains;
0166 }
0167 
0168 int intel_power_well_refcount(struct i915_power_well *power_well)
0169 {
0170     return power_well->count;
0171 }
0172 
0173 /*
0174  * Starting with Haswell, we have a "Power Down Well" that can be turned off
0175  * when not needed anymore. We have 4 registers that can request the power well
0176  * to be enabled, and it will only be disabled if none of the registers is
0177  * requesting it to be enabled.
0178  */
0179 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
0180                        u8 irq_pipe_mask, bool has_vga)
0181 {
0182     if (has_vga)
0183         intel_vga_reset_io_mem(dev_priv);
0184 
0185     if (irq_pipe_mask)
0186         gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
0187 }
0188 
0189 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
0190                        u8 irq_pipe_mask)
0191 {
0192     if (irq_pipe_mask)
0193         gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
0194 }
0195 
0196 #define ICL_AUX_PW_TO_CH(pw_idx)    \
0197     ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
0198 
0199 #define ICL_TBT_AUX_PW_TO_CH(pw_idx)    \
0200     ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
0201 
0202 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
0203 {
0204     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0205 
0206     return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
0207                          ICL_AUX_PW_TO_CH(pw_idx);
0208 }
0209 
0210 static struct intel_digital_port *
0211 aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
0212                enum aux_ch aux_ch)
0213 {
0214     struct intel_digital_port *dig_port = NULL;
0215     struct intel_encoder *encoder;
0216 
0217     for_each_intel_encoder(&dev_priv->drm, encoder) {
0218         /* We'll check the MST primary port */
0219         if (encoder->type == INTEL_OUTPUT_DP_MST)
0220             continue;
0221 
0222         dig_port = enc_to_dig_port(encoder);
0223         if (!dig_port)
0224             continue;
0225 
0226         if (dig_port->aux_ch != aux_ch) {
0227             dig_port = NULL;
0228             continue;
0229         }
0230 
0231         break;
0232     }
0233 
0234     return dig_port;
0235 }
0236 
0237 static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
0238                   const struct i915_power_well *power_well)
0239 {
0240     enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
0241     struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
0242 
0243     return intel_port_to_phy(i915, dig_port->base.port);
0244 }
0245 
0246 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
0247                        struct i915_power_well *power_well,
0248                        bool timeout_expected)
0249 {
0250     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0251     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0252 
0253     /*
0254      * For some power wells we're not supposed to watch the status bit for
0255      * an ack, but rather just wait a fixed amount of time and then
0256      * proceed.  This is only used on DG2.
0257      */
0258     if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) {
0259         usleep_range(600, 1200);
0260         return;
0261     }
0262 
0263     /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
0264     if (intel_de_wait_for_set(dev_priv, regs->driver,
0265                   HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
0266         drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
0267                 intel_power_well_name(power_well));
0268 
0269         drm_WARN_ON(&dev_priv->drm, !timeout_expected);
0270 
0271     }
0272 }
0273 
0274 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
0275                      const struct i915_power_well_regs *regs,
0276                      int pw_idx)
0277 {
0278     u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
0279     u32 ret;
0280 
0281     ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
0282     ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
0283     if (regs->kvmr.reg)
0284         ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
0285     ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
0286 
0287     return ret;
0288 }
0289 
0290 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
0291                         struct i915_power_well *power_well)
0292 {
0293     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0294     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0295     bool disabled;
0296     u32 reqs;
0297 
0298     /*
0299      * Bspec doesn't require waiting for PWs to get disabled, but still do
0300      * this for paranoia. The known cases where a PW will be forced on:
0301      * - a KVMR request on any power well via the KVMR request register
0302      * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
0303      *   DEBUG request registers
0304      * Skip the wait in case any of the request bits are set and print a
0305      * diagnostic message.
0306      */
0307     wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
0308                    HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
0309          (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
0310     if (disabled)
0311         return;
0312 
0313     drm_dbg_kms(&dev_priv->drm,
0314             "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
0315             intel_power_well_name(power_well),
0316             !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
0317 }
0318 
0319 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
0320                        enum skl_power_gate pg)
0321 {
0322     /* Timeout 5us for PG#0, for other PGs 1us */
0323     drm_WARN_ON(&dev_priv->drm,
0324             intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
0325                       SKL_FUSE_PG_DIST_STATUS(pg), 1));
0326 }
0327 
0328 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
0329                   struct i915_power_well *power_well)
0330 {
0331     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0332     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0333     u32 val;
0334 
0335     if (power_well->desc->has_fuses) {
0336         enum skl_power_gate pg;
0337 
0338         pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
0339                          SKL_PW_CTL_IDX_TO_PG(pw_idx);
0340 
0341         /* Wa_16013190616:adlp */
0342         if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
0343             intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
0344 
0345         /*
0346          * For PW1 we have to wait both for the PW0/PG0 fuse state
0347          * before enabling the power well and PW1/PG1's own fuse
0348          * state after the enabling. For all other power wells with
0349          * fuses we only have to wait for that PW/PG's fuse state
0350          * after the enabling.
0351          */
0352         if (pg == SKL_PG1)
0353             gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
0354     }
0355 
0356     val = intel_de_read(dev_priv, regs->driver);
0357     intel_de_write(dev_priv, regs->driver,
0358                val | HSW_PWR_WELL_CTL_REQ(pw_idx));
0359 
0360     hsw_wait_for_power_well_enable(dev_priv, power_well, false);
0361 
0362     if (power_well->desc->has_fuses) {
0363         enum skl_power_gate pg;
0364 
0365         pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
0366                          SKL_PW_CTL_IDX_TO_PG(pw_idx);
0367         gen9_wait_for_power_well_fuses(dev_priv, pg);
0368     }
0369 
0370     hsw_power_well_post_enable(dev_priv,
0371                    power_well->desc->irq_pipe_mask,
0372                    power_well->desc->has_vga);
0373 }
0374 
0375 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
0376                    struct i915_power_well *power_well)
0377 {
0378     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0379     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0380     u32 val;
0381 
0382     hsw_power_well_pre_disable(dev_priv,
0383                    power_well->desc->irq_pipe_mask);
0384 
0385     val = intel_de_read(dev_priv, regs->driver);
0386     intel_de_write(dev_priv, regs->driver,
0387                val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
0388     hsw_wait_for_power_well_disable(dev_priv, power_well);
0389 }
0390 
0391 static void
0392 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
0393                     struct i915_power_well *power_well)
0394 {
0395     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0396     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0397     enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
0398     u32 val;
0399 
0400     drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
0401 
0402     val = intel_de_read(dev_priv, regs->driver);
0403     intel_de_write(dev_priv, regs->driver,
0404                val | HSW_PWR_WELL_CTL_REQ(pw_idx));
0405 
0406     if (DISPLAY_VER(dev_priv) < 12) {
0407         val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
0408         intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
0409                    val | ICL_LANE_ENABLE_AUX);
0410     }
0411 
0412     hsw_wait_for_power_well_enable(dev_priv, power_well, false);
0413 
0414     /* Display WA #1178: icl */
0415     if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
0416         !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
0417         val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx));
0418         val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
0419         intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val);
0420     }
0421 }
0422 
0423 static void
0424 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
0425                      struct i915_power_well *power_well)
0426 {
0427     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0428     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0429     enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
0430     u32 val;
0431 
0432     drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
0433 
0434     val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
0435     intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
0436                val & ~ICL_LANE_ENABLE_AUX);
0437 
0438     val = intel_de_read(dev_priv, regs->driver);
0439     intel_de_write(dev_priv, regs->driver,
0440                val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
0441 
0442     hsw_wait_for_power_well_disable(dev_priv, power_well);
0443 }
0444 
0445 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
0446 
0447 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
0448                     struct i915_power_well *power_well,
0449                     struct intel_digital_port *dig_port)
0450 {
0451     if (drm_WARN_ON(&dev_priv->drm, !dig_port))
0452         return;
0453 
0454     if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
0455         return;
0456 
0457     drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
0458 }
0459 
0460 #else
0461 
0462 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
0463                     struct i915_power_well *power_well,
0464                     struct intel_digital_port *dig_port)
0465 {
0466 }
0467 
0468 #endif
0469 
0470 #define TGL_AUX_PW_TO_TC_PORT(pw_idx)   ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
0471 
0472 static void icl_tc_cold_exit(struct drm_i915_private *i915)
0473 {
0474     int ret, tries = 0;
0475 
0476     while (1) {
0477         ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,
0478                           250, 1);
0479         if (ret != -EAGAIN || ++tries == 3)
0480             break;
0481         msleep(1);
0482     }
0483 
0484     /* Spec states that TC cold exit can take up to 1ms to complete */
0485     if (!ret)
0486         msleep(1);
0487 
0488     /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */
0489     drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
0490             "succeeded");
0491 }
0492 
0493 static void
0494 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
0495                  struct i915_power_well *power_well)
0496 {
0497     enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
0498     struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
0499     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0500     bool is_tbt = power_well->desc->is_tc_tbt;
0501     bool timeout_expected;
0502     u32 val;
0503 
0504     icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
0505 
0506     val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
0507     val &= ~DP_AUX_CH_CTL_TBT_IO;
0508     if (is_tbt)
0509         val |= DP_AUX_CH_CTL_TBT_IO;
0510     intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
0511 
0512     val = intel_de_read(dev_priv, regs->driver);
0513     intel_de_write(dev_priv, regs->driver,
0514                val | HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx));
0515 
0516     /*
0517      * An AUX timeout is expected if the TBT DP tunnel is down,
0518      * or need to enable AUX on a legacy TypeC port as part of the TC-cold
0519      * exit sequence.
0520      */
0521     timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
0522     if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
0523         icl_tc_cold_exit(dev_priv);
0524 
0525     hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
0526 
0527     if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
0528         enum tc_port tc_port;
0529 
0530         tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
0531         intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
0532                    HIP_INDEX_VAL(tc_port, 0x2));
0533 
0534         if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port),
0535                       DKL_CMN_UC_DW27_UC_HEALTH, 1))
0536             drm_warn(&dev_priv->drm,
0537                  "Timeout waiting TC uC health\n");
0538     }
0539 }
0540 
0541 static void
0542 icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
0543               struct i915_power_well *power_well)
0544 {
0545     enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
0546 
0547     if (intel_phy_is_tc(dev_priv, phy))
0548         return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
0549     else if (IS_ICELAKE(dev_priv))
0550         return icl_combo_phy_aux_power_well_enable(dev_priv,
0551                                power_well);
0552     else
0553         return hsw_power_well_enable(dev_priv, power_well);
0554 }
0555 
0556 static void
0557 icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
0558                struct i915_power_well *power_well)
0559 {
0560     enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
0561 
0562     if (intel_phy_is_tc(dev_priv, phy))
0563         return hsw_power_well_disable(dev_priv, power_well);
0564     else if (IS_ICELAKE(dev_priv))
0565         return icl_combo_phy_aux_power_well_disable(dev_priv,
0566                                 power_well);
0567     else
0568         return hsw_power_well_disable(dev_priv, power_well);
0569 }
0570 
0571 /*
0572  * We should only use the power well if we explicitly asked the hardware to
0573  * enable it, so check if it's enabled and also check if we've requested it to
0574  * be enabled.
0575  */
0576 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
0577                    struct i915_power_well *power_well)
0578 {
0579     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0580     enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
0581     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0582     u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
0583            HSW_PWR_WELL_CTL_STATE(pw_idx);
0584     u32 val;
0585 
0586     val = intel_de_read(dev_priv, regs->driver);
0587 
0588     /*
0589      * On GEN9 big core due to a DMC bug the driver's request bits for PW1
0590      * and the MISC_IO PW will be not restored, so check instead for the
0591      * BIOS's own request bits, which are forced-on for these power wells
0592      * when exiting DC5/6.
0593      */
0594     if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
0595         (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
0596         val |= intel_de_read(dev_priv, regs->bios);
0597 
0598     return (val & mask) == mask;
0599 }
0600 
0601 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
0602 {
0603     drm_WARN_ONCE(&dev_priv->drm,
0604               (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
0605               "DC9 already programmed to be enabled.\n");
0606     drm_WARN_ONCE(&dev_priv->drm,
0607               intel_de_read(dev_priv, DC_STATE_EN) &
0608               DC_STATE_EN_UPTO_DC5,
0609               "DC5 still not disabled to enable DC9.\n");
0610     drm_WARN_ONCE(&dev_priv->drm,
0611               intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
0612               HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
0613               "Power well 2 on.\n");
0614     drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
0615               "Interrupts not disabled yet.\n");
0616 
0617      /*
0618       * TODO: check for the following to verify the conditions to enter DC9
0619       * state are satisfied:
0620       * 1] Check relevant display engine registers to verify if mode set
0621       * disable sequence was followed.
0622       * 2] Check if display uninitialize sequence is initialized.
0623       */
0624 }
0625 
0626 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
0627 {
0628     drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
0629               "Interrupts not disabled yet.\n");
0630     drm_WARN_ONCE(&dev_priv->drm,
0631               intel_de_read(dev_priv, DC_STATE_EN) &
0632               DC_STATE_EN_UPTO_DC5,
0633               "DC5 still not disabled.\n");
0634 
0635      /*
0636       * TODO: check for the following to verify DC9 state was indeed
0637       * entered before programming to disable it:
0638       * 1] Check relevant display engine registers to verify if mode
0639       *  set disable sequence was followed.
0640       * 2] Check if display uninitialize sequence is initialized.
0641       */
0642 }
0643 
0644 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
0645                 u32 state)
0646 {
0647     int rewrites = 0;
0648     int rereads = 0;
0649     u32 v;
0650 
0651     intel_de_write(dev_priv, DC_STATE_EN, state);
0652 
0653     /* It has been observed that disabling the dc6 state sometimes
0654      * doesn't stick and dmc keeps returning old value. Make sure
0655      * the write really sticks enough times and also force rewrite until
0656      * we are confident that state is exactly what we want.
0657      */
0658     do  {
0659         v = intel_de_read(dev_priv, DC_STATE_EN);
0660 
0661         if (v != state) {
0662             intel_de_write(dev_priv, DC_STATE_EN, state);
0663             rewrites++;
0664             rereads = 0;
0665         } else if (rereads++ > 5) {
0666             break;
0667         }
0668 
0669     } while (rewrites < 100);
0670 
0671     if (v != state)
0672         drm_err(&dev_priv->drm,
0673             "Writing dc state to 0x%x failed, now 0x%x\n",
0674             state, v);
0675 
0676     /* Most of the times we need one retry, avoid spam */
0677     if (rewrites > 1)
0678         drm_dbg_kms(&dev_priv->drm,
0679                 "Rewrote dc state to 0x%x %d times\n",
0680                 state, rewrites);
0681 }
0682 
0683 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
0684 {
0685     u32 mask;
0686 
0687     mask = DC_STATE_EN_UPTO_DC5;
0688 
0689     if (DISPLAY_VER(dev_priv) >= 12)
0690         mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
0691                       | DC_STATE_EN_DC9;
0692     else if (DISPLAY_VER(dev_priv) == 11)
0693         mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
0694     else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
0695         mask |= DC_STATE_EN_DC9;
0696     else
0697         mask |= DC_STATE_EN_UPTO_DC6;
0698 
0699     return mask;
0700 }
0701 
0702 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
0703 {
0704     u32 val;
0705 
0706     if (!HAS_DISPLAY(dev_priv))
0707         return;
0708 
0709     val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv);
0710 
0711     drm_dbg_kms(&dev_priv->drm,
0712             "Resetting DC state tracking from %02x to %02x\n",
0713             dev_priv->dmc.dc_state, val);
0714     dev_priv->dmc.dc_state = val;
0715 }
0716 
0717 /**
0718  * gen9_set_dc_state - set target display C power state
0719  * @dev_priv: i915 device instance
0720  * @state: target DC power state
0721  * - DC_STATE_DISABLE
0722  * - DC_STATE_EN_UPTO_DC5
0723  * - DC_STATE_EN_UPTO_DC6
0724  * - DC_STATE_EN_DC9
0725  *
0726  * Signal to DMC firmware/HW the target DC power state passed in @state.
0727  * DMC/HW can turn off individual display clocks and power rails when entering
0728  * a deeper DC power state (higher in number) and turns these back when exiting
0729  * that state to a shallower power state (lower in number). The HW will decide
0730  * when to actually enter a given state on an on-demand basis, for instance
0731  * depending on the active state of display pipes. The state of display
0732  * registers backed by affected power rails are saved/restored as needed.
0733  *
0734  * Based on the above enabling a deeper DC power state is asynchronous wrt.
0735  * enabling it. Disabling a deeper power state is synchronous: for instance
0736  * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
0737  * back on and register state is restored. This is guaranteed by the MMIO write
0738  * to DC_STATE_EN blocking until the state is restored.
0739  */
0740 void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
0741 {
0742     u32 val;
0743     u32 mask;
0744 
0745     if (!HAS_DISPLAY(dev_priv))
0746         return;
0747 
0748     if (drm_WARN_ON_ONCE(&dev_priv->drm,
0749                  state & ~dev_priv->dmc.allowed_dc_mask))
0750         state &= dev_priv->dmc.allowed_dc_mask;
0751 
0752     val = intel_de_read(dev_priv, DC_STATE_EN);
0753     mask = gen9_dc_mask(dev_priv);
0754     drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",
0755             val & mask, state);
0756 
0757     /* Check if DMC is ignoring our DC state requests */
0758     if ((val & mask) != dev_priv->dmc.dc_state)
0759         drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
0760             dev_priv->dmc.dc_state, val & mask);
0761 
0762     val &= ~mask;
0763     val |= state;
0764 
0765     gen9_write_dc_state(dev_priv, val);
0766 
0767     dev_priv->dmc.dc_state = val & mask;
0768 }
0769 
0770 static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
0771 {
0772     drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
0773     gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
0774 }
0775 
0776 static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
0777 {
0778     u32 val;
0779 
0780     drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
0781     val = intel_de_read(dev_priv, DC_STATE_EN);
0782     val &= ~DC_STATE_DC3CO_STATUS;
0783     intel_de_write(dev_priv, DC_STATE_EN, val);
0784     gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
0785     /*
0786      * Delay of 200us DC3CO Exit time B.Spec 49196
0787      */
0788     usleep_range(200, 210);
0789 }
0790 
0791 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
0792 {
0793     enum i915_power_well_id high_pg;
0794 
0795     /* Power wells at this level and above must be disabled for DC5 entry */
0796     if (DISPLAY_VER(dev_priv) == 12)
0797         high_pg = ICL_DISP_PW_3;
0798     else
0799         high_pg = SKL_DISP_PW_2;
0800 
0801     drm_WARN_ONCE(&dev_priv->drm,
0802               intel_display_power_well_is_enabled(dev_priv, high_pg),
0803               "Power wells above platform's DC5 limit still enabled.\n");
0804 
0805     drm_WARN_ONCE(&dev_priv->drm,
0806               (intel_de_read(dev_priv, DC_STATE_EN) &
0807                DC_STATE_EN_UPTO_DC5),
0808               "DC5 already programmed to be enabled.\n");
0809     assert_rpm_wakelock_held(&dev_priv->runtime_pm);
0810 
0811     assert_dmc_loaded(dev_priv);
0812 }
0813 
0814 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
0815 {
0816     assert_can_enable_dc5(dev_priv);
0817 
0818     drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
0819 
0820     /* Wa Display #1183: skl,kbl,cfl */
0821     if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
0822         intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
0823                    intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
0824 
0825     gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
0826 }
0827 
0828 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
0829 {
0830     drm_WARN_ONCE(&dev_priv->drm,
0831               intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
0832               "Backlight is not disabled.\n");
0833     drm_WARN_ONCE(&dev_priv->drm,
0834               (intel_de_read(dev_priv, DC_STATE_EN) &
0835                DC_STATE_EN_UPTO_DC6),
0836               "DC6 already programmed to be enabled.\n");
0837 
0838     assert_dmc_loaded(dev_priv);
0839 }
0840 
0841 void skl_enable_dc6(struct drm_i915_private *dev_priv)
0842 {
0843     assert_can_enable_dc6(dev_priv);
0844 
0845     drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
0846 
0847     /* Wa Display #1183: skl,kbl,cfl */
0848     if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
0849         intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
0850                    intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
0851 
0852     gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
0853 }
0854 
0855 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
0856 {
0857     assert_can_enable_dc9(dev_priv);
0858 
0859     drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
0860     /*
0861      * Power sequencer reset is not needed on
0862      * platforms with South Display Engine on PCH,
0863      * because PPS registers are always on.
0864      */
0865     if (!HAS_PCH_SPLIT(dev_priv))
0866         intel_pps_reset_all(dev_priv);
0867     gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
0868 }
0869 
0870 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
0871 {
0872     assert_can_disable_dc9(dev_priv);
0873 
0874     drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
0875 
0876     gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
0877 
0878     intel_pps_unlock_regs_wa(dev_priv);
0879 }
0880 
0881 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
0882                    struct i915_power_well *power_well)
0883 {
0884     const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
0885     int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
0886     u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
0887     u32 bios_req = intel_de_read(dev_priv, regs->bios);
0888 
0889     /* Take over the request bit if set by BIOS. */
0890     if (bios_req & mask) {
0891         u32 drv_req = intel_de_read(dev_priv, regs->driver);
0892 
0893         if (!(drv_req & mask))
0894             intel_de_write(dev_priv, regs->driver, drv_req | mask);
0895         intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
0896     }
0897 }
0898 
0899 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
0900                        struct i915_power_well *power_well)
0901 {
0902     bxt_ddi_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
0903 }
0904 
0905 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
0906                         struct i915_power_well *power_well)
0907 {
0908     bxt_ddi_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
0909 }
0910 
0911 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
0912                         struct i915_power_well *power_well)
0913 {
0914     return bxt_ddi_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
0915 }
0916 
0917 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
0918 {
0919     struct i915_power_well *power_well;
0920 
0921     power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
0922     if (intel_power_well_refcount(power_well) > 0)
0923         bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
0924 
0925     power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
0926     if (intel_power_well_refcount(power_well) > 0)
0927         bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
0928 
0929     if (IS_GEMINILAKE(dev_priv)) {
0930         power_well = lookup_power_well(dev_priv,
0931                            GLK_DISP_PW_DPIO_CMN_C);
0932         if (intel_power_well_refcount(power_well) > 0)
0933             bxt_ddi_phy_verify_state(dev_priv,
0934                          i915_power_well_instance(power_well)->bxt.phy);
0935     }
0936 }
0937 
0938 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
0939                        struct i915_power_well *power_well)
0940 {
0941     return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
0942         (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
0943 }
0944 
0945 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
0946 {
0947     u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
0948     u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
0949 
0950     drm_WARN(&dev_priv->drm,
0951          hw_enabled_dbuf_slices != enabled_dbuf_slices,
0952          "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
0953          hw_enabled_dbuf_slices,
0954          enabled_dbuf_slices);
0955 }
0956 
0957 void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
0958 {
0959     struct intel_cdclk_config cdclk_config = {};
0960 
0961     if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
0962         tgl_disable_dc3co(dev_priv);
0963         return;
0964     }
0965 
0966     gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
0967 
0968     if (!HAS_DISPLAY(dev_priv))
0969         return;
0970 
0971     intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
0972     /* Can't read out voltage_level so can't use intel_cdclk_changed() */
0973     drm_WARN_ON(&dev_priv->drm,
0974             intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
0975                           &cdclk_config));
0976 
0977     gen9_assert_dbuf_enabled(dev_priv);
0978 
0979     if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
0980         bxt_verify_ddi_phy_power_wells(dev_priv);
0981 
0982     if (DISPLAY_VER(dev_priv) >= 11)
0983         /*
0984          * DMC retains HW context only for port A, the other combo
0985          * PHY's HW context for port B is lost after DC transitions,
0986          * so we need to restore it manually.
0987          */
0988         intel_combo_phy_init(dev_priv);
0989 }
0990 
0991 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
0992                       struct i915_power_well *power_well)
0993 {
0994     gen9_disable_dc_states(dev_priv);
0995 }
0996 
0997 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
0998                        struct i915_power_well *power_well)
0999 {
1000     if (!intel_dmc_has_payload(dev_priv))
1001         return;
1002 
1003     switch (dev_priv->dmc.target_dc_state) {
1004     case DC_STATE_EN_DC3CO:
1005         tgl_enable_dc3co(dev_priv);
1006         break;
1007     case DC_STATE_EN_UPTO_DC6:
1008         skl_enable_dc6(dev_priv);
1009         break;
1010     case DC_STATE_EN_UPTO_DC5:
1011         gen9_enable_dc5(dev_priv);
1012         break;
1013     }
1014 }
1015 
1016 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
1017                      struct i915_power_well *power_well)
1018 {
1019 }
1020 
1021 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
1022                        struct i915_power_well *power_well)
1023 {
1024 }
1025 
1026 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
1027                          struct i915_power_well *power_well)
1028 {
1029     return true;
1030 }
1031 
1032 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
1033                      struct i915_power_well *power_well)
1034 {
1035     if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
1036         i830_enable_pipe(dev_priv, PIPE_A);
1037     if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
1038         i830_enable_pipe(dev_priv, PIPE_B);
1039 }
1040 
1041 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
1042                       struct i915_power_well *power_well)
1043 {
1044     i830_disable_pipe(dev_priv, PIPE_B);
1045     i830_disable_pipe(dev_priv, PIPE_A);
1046 }
1047 
1048 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
1049                       struct i915_power_well *power_well)
1050 {
1051     return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
1052         intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1053 }
1054 
1055 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
1056                       struct i915_power_well *power_well)
1057 {
1058     if (intel_power_well_refcount(power_well) > 0)
1059         i830_pipes_power_well_enable(dev_priv, power_well);
1060     else
1061         i830_pipes_power_well_disable(dev_priv, power_well);
1062 }
1063 
1064 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
1065                    struct i915_power_well *power_well, bool enable)
1066 {
1067     int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
1068     u32 mask;
1069     u32 state;
1070     u32 ctrl;
1071 
1072     mask = PUNIT_PWRGT_MASK(pw_idx);
1073     state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
1074              PUNIT_PWRGT_PWR_GATE(pw_idx);
1075 
1076     vlv_punit_get(dev_priv);
1077 
1078 #define COND \
1079     ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
1080 
1081     if (COND)
1082         goto out;
1083 
1084     ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
1085     ctrl &= ~mask;
1086     ctrl |= state;
1087     vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
1088 
1089     if (wait_for(COND, 100))
1090         drm_err(&dev_priv->drm,
1091             "timeout setting power well state %08x (%08x)\n",
1092             state,
1093             vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1094 
1095 #undef COND
1096 
1097 out:
1098     vlv_punit_put(dev_priv);
1099 }
1100 
1101 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1102                   struct i915_power_well *power_well)
1103 {
1104     vlv_set_power_well(dev_priv, power_well, true);
1105 }
1106 
1107 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1108                    struct i915_power_well *power_well)
1109 {
1110     vlv_set_power_well(dev_priv, power_well, false);
1111 }
1112 
1113 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1114                    struct i915_power_well *power_well)
1115 {
1116     int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
1117     bool enabled = false;
1118     u32 mask;
1119     u32 state;
1120     u32 ctrl;
1121 
1122     mask = PUNIT_PWRGT_MASK(pw_idx);
1123     ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
1124 
1125     vlv_punit_get(dev_priv);
1126 
1127     state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1128     /*
1129      * We only ever set the power-on and power-gate states, anything
1130      * else is unexpected.
1131      */
1132     drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
1133             state != PUNIT_PWRGT_PWR_GATE(pw_idx));
1134     if (state == ctrl)
1135         enabled = true;
1136 
1137     /*
1138      * A transient state at this point would mean some unexpected party
1139      * is poking at the power controls too.
1140      */
1141     ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1142     drm_WARN_ON(&dev_priv->drm, ctrl != state);
1143 
1144     vlv_punit_put(dev_priv);
1145 
1146     return enabled;
1147 }
1148 
1149 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1150 {
1151     u32 val;
1152 
1153     /*
1154      * On driver load, a pipe may be active and driving a DSI display.
1155      * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1156      * (and never recovering) in this case. intel_dsi_post_disable() will
1157      * clear it when we turn off the display.
1158      */
1159     val = intel_de_read(dev_priv, DSPCLK_GATE_D);
1160     val &= DPOUNIT_CLOCK_GATE_DISABLE;
1161     val |= VRHUNIT_CLOCK_GATE_DISABLE;
1162     intel_de_write(dev_priv, DSPCLK_GATE_D, val);
1163 
1164     /*
1165      * Disable trickle feed and enable pnd deadline calculation
1166      */
1167     intel_de_write(dev_priv, MI_ARB_VLV,
1168                MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1169     intel_de_write(dev_priv, CBR1_VLV, 0);
1170 
1171     drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
1172     intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
1173                DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
1174                      1000));
1175 }
1176 
1177 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1178 {
1179     struct intel_encoder *encoder;
1180     enum pipe pipe;
1181 
1182     /*
1183      * Enable the CRI clock source so we can get at the
1184      * display and the reference clock for VGA
1185      * hotplug / manual detection. Supposedly DSI also
1186      * needs the ref clock up and running.
1187      *
1188      * CHV DPLL B/C have some issues if VGA mode is enabled.
1189      */
1190     for_each_pipe(dev_priv, pipe) {
1191         u32 val = intel_de_read(dev_priv, DPLL(pipe));
1192 
1193         val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1194         if (pipe != PIPE_A)
1195             val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1196 
1197         intel_de_write(dev_priv, DPLL(pipe), val);
1198     }
1199 
1200     vlv_init_display_clock_gating(dev_priv);
1201 
1202     spin_lock_irq(&dev_priv->irq_lock);
1203     valleyview_enable_display_irqs(dev_priv);
1204     spin_unlock_irq(&dev_priv->irq_lock);
1205 
1206     /*
1207      * During driver initialization/resume we can avoid restoring the
1208      * part of the HW/SW state that will be inited anyway explicitly.
1209      */
1210     if (dev_priv->power_domains.initializing)
1211         return;
1212 
1213     intel_hpd_init(dev_priv);
1214     intel_hpd_poll_disable(dev_priv);
1215 
1216     /* Re-enable the ADPA, if we have one */
1217     for_each_intel_encoder(&dev_priv->drm, encoder) {
1218         if (encoder->type == INTEL_OUTPUT_ANALOG)
1219             intel_crt_reset(&encoder->base);
1220     }
1221 
1222     intel_vga_redisable_power_on(dev_priv);
1223 
1224     intel_pps_unlock_regs_wa(dev_priv);
1225 }
1226 
1227 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1228 {
1229     spin_lock_irq(&dev_priv->irq_lock);
1230     valleyview_disable_display_irqs(dev_priv);
1231     spin_unlock_irq(&dev_priv->irq_lock);
1232 
1233     /* make sure we're done processing display irqs */
1234     intel_synchronize_irq(dev_priv);
1235 
1236     intel_pps_reset_all(dev_priv);
1237 
1238     /* Prevent us from re-enabling polling on accident in late suspend */
1239     if (!dev_priv->drm.dev->power.is_suspended)
1240         intel_hpd_poll_enable(dev_priv);
1241 }
1242 
1243 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1244                       struct i915_power_well *power_well)
1245 {
1246     vlv_set_power_well(dev_priv, power_well, true);
1247 
1248     vlv_display_power_well_init(dev_priv);
1249 }
1250 
1251 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1252                        struct i915_power_well *power_well)
1253 {
1254     vlv_display_power_well_deinit(dev_priv);
1255 
1256     vlv_set_power_well(dev_priv, power_well, false);
1257 }
1258 
1259 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1260                        struct i915_power_well *power_well)
1261 {
1262     /* since ref/cri clock was enabled */
1263     udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1264 
1265     vlv_set_power_well(dev_priv, power_well, true);
1266 
1267     /*
1268      * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1269      *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1270      *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1271      *   b. The other bits such as sfr settings / modesel may all
1272      *  be set to 0.
1273      *
1274      * This should only be done on init and resume from S3 with
1275      * both PLLs disabled, or we risk losing DPIO and PLL
1276      * synchronization.
1277      */
1278     intel_de_write(dev_priv, DPIO_CTL,
1279                intel_de_read(dev_priv, DPIO_CTL) | DPIO_CMNRST);
1280 }
1281 
1282 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1283                         struct i915_power_well *power_well)
1284 {
1285     enum pipe pipe;
1286 
1287     for_each_pipe(dev_priv, pipe)
1288         assert_pll_disabled(dev_priv, pipe);
1289 
1290     /* Assert common reset */
1291     intel_de_write(dev_priv, DPIO_CTL,
1292                intel_de_read(dev_priv, DPIO_CTL) & ~DPIO_CMNRST);
1293 
1294     vlv_set_power_well(dev_priv, power_well, false);
1295 }
1296 
1297 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1298 
1299 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1300 {
1301     struct i915_power_well *cmn_bc =
1302         lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1303     struct i915_power_well *cmn_d =
1304         lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1305     u32 phy_control = dev_priv->chv_phy_control;
1306     u32 phy_status = 0;
1307     u32 phy_status_mask = 0xffffffff;
1308 
1309     /*
1310      * The BIOS can leave the PHY is some weird state
1311      * where it doesn't fully power down some parts.
1312      * Disable the asserts until the PHY has been fully
1313      * reset (ie. the power well has been disabled at
1314      * least once).
1315      */
1316     if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1317         phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1318                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1319                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1320                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1321                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1322                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1323 
1324     if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1325         phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1326                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1327                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1328 
1329     if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
1330         phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1331 
1332         /* this assumes override is only used to enable lanes */
1333         if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1334             phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1335 
1336         if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1337             phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1338 
1339         /* CL1 is on whenever anything is on in either channel */
1340         if (BITS_SET(phy_control,
1341                  PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1342                  PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1343             phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1344 
1345         /*
1346          * The DPLLB check accounts for the pipe B + port A usage
1347          * with CL2 powered up but all the lanes in the second channel
1348          * powered down.
1349          */
1350         if (BITS_SET(phy_control,
1351                  PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1352             (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1353             phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1354 
1355         if (BITS_SET(phy_control,
1356                  PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1357             phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1358         if (BITS_SET(phy_control,
1359                  PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1360             phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1361 
1362         if (BITS_SET(phy_control,
1363                  PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1364             phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1365         if (BITS_SET(phy_control,
1366                  PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1367             phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1368     }
1369 
1370     if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
1371         phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1372 
1373         /* this assumes override is only used to enable lanes */
1374         if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1375             phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1376 
1377         if (BITS_SET(phy_control,
1378                  PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1379             phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1380 
1381         if (BITS_SET(phy_control,
1382                  PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1383             phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1384         if (BITS_SET(phy_control,
1385                  PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1386             phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1387     }
1388 
1389     phy_status &= phy_status_mask;
1390 
1391     /*
1392      * The PHY may be busy with some initial calibration and whatnot,
1393      * so the power state can take a while to actually change.
1394      */
1395     if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,
1396                        phy_status_mask, phy_status, 10))
1397         drm_err(&dev_priv->drm,
1398             "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1399             intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
1400             phy_status, dev_priv->chv_phy_control);
1401 }
1402 
1403 #undef BITS_SET
1404 
1405 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1406                        struct i915_power_well *power_well)
1407 {
1408     enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1409     enum dpio_phy phy;
1410     enum pipe pipe;
1411     u32 tmp;
1412 
1413     drm_WARN_ON_ONCE(&dev_priv->drm,
1414              id != VLV_DISP_PW_DPIO_CMN_BC &&
1415              id != CHV_DISP_PW_DPIO_CMN_D);
1416 
1417     if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1418         pipe = PIPE_A;
1419         phy = DPIO_PHY0;
1420     } else {
1421         pipe = PIPE_C;
1422         phy = DPIO_PHY1;
1423     }
1424 
1425     /* since ref/cri clock was enabled */
1426     udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1427     vlv_set_power_well(dev_priv, power_well, true);
1428 
1429     /* Poll for phypwrgood signal */
1430     if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
1431                   PHY_POWERGOOD(phy), 1))
1432         drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
1433             phy);
1434 
1435     vlv_dpio_get(dev_priv);
1436 
1437     /* Enable dynamic power down */
1438     tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1439     tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1440         DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1441     vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1442 
1443     if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1444         tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1445         tmp |= DPIO_DYNPWRDOWNEN_CH1;
1446         vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1447     } else {
1448         /*
1449          * Force the non-existing CL2 off. BXT does this
1450          * too, so maybe it saves some power even though
1451          * CL2 doesn't exist?
1452          */
1453         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1454         tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1455         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1456     }
1457 
1458     vlv_dpio_put(dev_priv);
1459 
1460     dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1461     intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1462                dev_priv->chv_phy_control);
1463 
1464     drm_dbg_kms(&dev_priv->drm,
1465             "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1466             phy, dev_priv->chv_phy_control);
1467 
1468     assert_chv_phy_status(dev_priv);
1469 }
1470 
1471 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1472                         struct i915_power_well *power_well)
1473 {
1474     enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1475     enum dpio_phy phy;
1476 
1477     drm_WARN_ON_ONCE(&dev_priv->drm,
1478              id != VLV_DISP_PW_DPIO_CMN_BC &&
1479              id != CHV_DISP_PW_DPIO_CMN_D);
1480 
1481     if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1482         phy = DPIO_PHY0;
1483         assert_pll_disabled(dev_priv, PIPE_A);
1484         assert_pll_disabled(dev_priv, PIPE_B);
1485     } else {
1486         phy = DPIO_PHY1;
1487         assert_pll_disabled(dev_priv, PIPE_C);
1488     }
1489 
1490     dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1491     intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1492                dev_priv->chv_phy_control);
1493 
1494     vlv_set_power_well(dev_priv, power_well, false);
1495 
1496     drm_dbg_kms(&dev_priv->drm,
1497             "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1498             phy, dev_priv->chv_phy_control);
1499 
1500     /* PHY is fully reset now, so we can enable the PHY state asserts */
1501     dev_priv->chv_phy_assert[phy] = true;
1502 
1503     assert_chv_phy_status(dev_priv);
1504 }
1505 
1506 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1507                      enum dpio_channel ch, bool override, unsigned int mask)
1508 {
1509     enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1510     u32 reg, val, expected, actual;
1511 
1512     /*
1513      * The BIOS can leave the PHY is some weird state
1514      * where it doesn't fully power down some parts.
1515      * Disable the asserts until the PHY has been fully
1516      * reset (ie. the power well has been disabled at
1517      * least once).
1518      */
1519     if (!dev_priv->chv_phy_assert[phy])
1520         return;
1521 
1522     if (ch == DPIO_CH0)
1523         reg = _CHV_CMN_DW0_CH0;
1524     else
1525         reg = _CHV_CMN_DW6_CH1;
1526 
1527     vlv_dpio_get(dev_priv);
1528     val = vlv_dpio_read(dev_priv, pipe, reg);
1529     vlv_dpio_put(dev_priv);
1530 
1531     /*
1532      * This assumes !override is only used when the port is disabled.
1533      * All lanes should power down even without the override when
1534      * the port is disabled.
1535      */
1536     if (!override || mask == 0xf) {
1537         expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1538         /*
1539          * If CH1 common lane is not active anymore
1540          * (eg. for pipe B DPLL) the entire channel will
1541          * shut down, which causes the common lane registers
1542          * to read as 0. That means we can't actually check
1543          * the lane power down status bits, but as the entire
1544          * register reads as 0 it's a good indication that the
1545          * channel is indeed entirely powered down.
1546          */
1547         if (ch == DPIO_CH1 && val == 0)
1548             expected = 0;
1549     } else if (mask != 0x0) {
1550         expected = DPIO_ANYDL_POWERDOWN;
1551     } else {
1552         expected = 0;
1553     }
1554 
1555     if (ch == DPIO_CH0)
1556         actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1557     else
1558         actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1559     actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1560 
1561     drm_WARN(&dev_priv->drm, actual != expected,
1562          "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1563          !!(actual & DPIO_ALLDL_POWERDOWN),
1564          !!(actual & DPIO_ANYDL_POWERDOWN),
1565          !!(expected & DPIO_ALLDL_POWERDOWN),
1566          !!(expected & DPIO_ANYDL_POWERDOWN),
1567          reg, val);
1568 }
1569 
1570 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1571               enum dpio_channel ch, bool override)
1572 {
1573     struct i915_power_domains *power_domains = &dev_priv->power_domains;
1574     bool was_override;
1575 
1576     mutex_lock(&power_domains->lock);
1577 
1578     was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1579 
1580     if (override == was_override)
1581         goto out;
1582 
1583     if (override)
1584         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1585     else
1586         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1587 
1588     intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1589                dev_priv->chv_phy_control);
1590 
1591     drm_dbg_kms(&dev_priv->drm,
1592             "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1593             phy, ch, dev_priv->chv_phy_control);
1594 
1595     assert_chv_phy_status(dev_priv);
1596 
1597 out:
1598     mutex_unlock(&power_domains->lock);
1599 
1600     return was_override;
1601 }
1602 
1603 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1604                  bool override, unsigned int mask)
1605 {
1606     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1607     struct i915_power_domains *power_domains = &dev_priv->power_domains;
1608     enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
1609     enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
1610 
1611     mutex_lock(&power_domains->lock);
1612 
1613     dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1614     dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1615 
1616     if (override)
1617         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1618     else
1619         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1620 
1621     intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1622                dev_priv->chv_phy_control);
1623 
1624     drm_dbg_kms(&dev_priv->drm,
1625             "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1626             phy, ch, mask, dev_priv->chv_phy_control);
1627 
1628     assert_chv_phy_status(dev_priv);
1629 
1630     assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1631 
1632     mutex_unlock(&power_domains->lock);
1633 }
1634 
1635 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1636                     struct i915_power_well *power_well)
1637 {
1638     enum pipe pipe = PIPE_A;
1639     bool enabled;
1640     u32 state, ctrl;
1641 
1642     vlv_punit_get(dev_priv);
1643 
1644     state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
1645     /*
1646      * We only ever set the power-on and power-gate states, anything
1647      * else is unexpected.
1648      */
1649     drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
1650             state != DP_SSS_PWR_GATE(pipe));
1651     enabled = state == DP_SSS_PWR_ON(pipe);
1652 
1653     /*
1654      * A transient state at this point would mean some unexpected party
1655      * is poking at the power controls too.
1656      */
1657     ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
1658     drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
1659 
1660     vlv_punit_put(dev_priv);
1661 
1662     return enabled;
1663 }
1664 
1665 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1666                     struct i915_power_well *power_well,
1667                     bool enable)
1668 {
1669     enum pipe pipe = PIPE_A;
1670     u32 state;
1671     u32 ctrl;
1672 
1673     state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1674 
1675     vlv_punit_get(dev_priv);
1676 
1677 #define COND \
1678     ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
1679 
1680     if (COND)
1681         goto out;
1682 
1683     ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
1684     ctrl &= ~DP_SSC_MASK(pipe);
1685     ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1686     vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
1687 
1688     if (wait_for(COND, 100))
1689         drm_err(&dev_priv->drm,
1690             "timeout setting power well state %08x (%08x)\n",
1691             state,
1692             vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
1693 
1694 #undef COND
1695 
1696 out:
1697     vlv_punit_put(dev_priv);
1698 }
1699 
1700 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1701                     struct i915_power_well *power_well)
1702 {
1703     intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1704                dev_priv->chv_phy_control);
1705 }
1706 
1707 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1708                        struct i915_power_well *power_well)
1709 {
1710     chv_set_pipe_power_well(dev_priv, power_well, true);
1711 
1712     vlv_display_power_well_init(dev_priv);
1713 }
1714 
1715 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1716                     struct i915_power_well *power_well)
1717 {
1718     vlv_display_power_well_deinit(dev_priv);
1719 
1720     chv_set_pipe_power_well(dev_priv, power_well, false);
1721 }
1722 
1723 static void
1724 tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
1725 {
1726     u8 tries = 0;
1727     int ret;
1728 
1729     while (1) {
1730         u32 low_val;
1731         u32 high_val = 0;
1732 
1733         if (block)
1734             low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
1735         else
1736             low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;
1737 
1738         /*
1739          * Spec states that we should timeout the request after 200us
1740          * but the function below will timeout after 500us
1741          */
1742         ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val);
1743         if (ret == 0) {
1744             if (block &&
1745                 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
1746                 ret = -EIO;
1747             else
1748                 break;
1749         }
1750 
1751         if (++tries == 3)
1752             break;
1753 
1754         msleep(1);
1755     }
1756 
1757     if (ret)
1758         drm_err(&i915->drm, "TC cold %sblock failed\n",
1759             block ? "" : "un");
1760     else
1761         drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
1762                 block ? "" : "un");
1763 }
1764 
1765 static void
1766 tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
1767                   struct i915_power_well *power_well)
1768 {
1769     tgl_tc_cold_request(i915, true);
1770 }
1771 
1772 static void
1773 tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
1774                    struct i915_power_well *power_well)
1775 {
1776     tgl_tc_cold_request(i915, false);
1777 }
1778 
1779 static void
1780 tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
1781                    struct i915_power_well *power_well)
1782 {
1783     if (intel_power_well_refcount(power_well) > 0)
1784         tgl_tc_cold_off_power_well_enable(i915, power_well);
1785     else
1786         tgl_tc_cold_off_power_well_disable(i915, power_well);
1787 }
1788 
1789 static bool
1790 tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
1791                       struct i915_power_well *power_well)
1792 {
1793     /*
1794      * Not the correctly implementation but there is no way to just read it
1795      * from PCODE, so returning count to avoid state mismatch errors
1796      */
1797     return intel_power_well_refcount(power_well);
1798 }
1799 
1800 
1801 const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1802     .sync_hw = i9xx_power_well_sync_hw_noop,
1803     .enable = i9xx_always_on_power_well_noop,
1804     .disable = i9xx_always_on_power_well_noop,
1805     .is_enabled = i9xx_always_on_power_well_enabled,
1806 };
1807 
1808 const struct i915_power_well_ops chv_pipe_power_well_ops = {
1809     .sync_hw = chv_pipe_power_well_sync_hw,
1810     .enable = chv_pipe_power_well_enable,
1811     .disable = chv_pipe_power_well_disable,
1812     .is_enabled = chv_pipe_power_well_enabled,
1813 };
1814 
1815 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1816     .sync_hw = i9xx_power_well_sync_hw_noop,
1817     .enable = chv_dpio_cmn_power_well_enable,
1818     .disable = chv_dpio_cmn_power_well_disable,
1819     .is_enabled = vlv_power_well_enabled,
1820 };
1821 
1822 const struct i915_power_well_ops i830_pipes_power_well_ops = {
1823     .sync_hw = i830_pipes_power_well_sync_hw,
1824     .enable = i830_pipes_power_well_enable,
1825     .disable = i830_pipes_power_well_disable,
1826     .is_enabled = i830_pipes_power_well_enabled,
1827 };
1828 
1829 static const struct i915_power_well_regs hsw_power_well_regs = {
1830     .bios   = HSW_PWR_WELL_CTL1,
1831     .driver = HSW_PWR_WELL_CTL2,
1832     .kvmr   = HSW_PWR_WELL_CTL3,
1833     .debug  = HSW_PWR_WELL_CTL4,
1834 };
1835 
1836 const struct i915_power_well_ops hsw_power_well_ops = {
1837     .regs = &hsw_power_well_regs,
1838     .sync_hw = hsw_power_well_sync_hw,
1839     .enable = hsw_power_well_enable,
1840     .disable = hsw_power_well_disable,
1841     .is_enabled = hsw_power_well_enabled,
1842 };
1843 
1844 const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1845     .sync_hw = i9xx_power_well_sync_hw_noop,
1846     .enable = gen9_dc_off_power_well_enable,
1847     .disable = gen9_dc_off_power_well_disable,
1848     .is_enabled = gen9_dc_off_power_well_enabled,
1849 };
1850 
1851 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1852     .sync_hw = i9xx_power_well_sync_hw_noop,
1853     .enable = bxt_dpio_cmn_power_well_enable,
1854     .disable = bxt_dpio_cmn_power_well_disable,
1855     .is_enabled = bxt_dpio_cmn_power_well_enabled,
1856 };
1857 
1858 const struct i915_power_well_ops vlv_display_power_well_ops = {
1859     .sync_hw = i9xx_power_well_sync_hw_noop,
1860     .enable = vlv_display_power_well_enable,
1861     .disable = vlv_display_power_well_disable,
1862     .is_enabled = vlv_power_well_enabled,
1863 };
1864 
1865 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1866     .sync_hw = i9xx_power_well_sync_hw_noop,
1867     .enable = vlv_dpio_cmn_power_well_enable,
1868     .disable = vlv_dpio_cmn_power_well_disable,
1869     .is_enabled = vlv_power_well_enabled,
1870 };
1871 
1872 const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1873     .sync_hw = i9xx_power_well_sync_hw_noop,
1874     .enable = vlv_power_well_enable,
1875     .disable = vlv_power_well_disable,
1876     .is_enabled = vlv_power_well_enabled,
1877 };
1878 
1879 static const struct i915_power_well_regs icl_aux_power_well_regs = {
1880     .bios   = ICL_PWR_WELL_CTL_AUX1,
1881     .driver = ICL_PWR_WELL_CTL_AUX2,
1882     .debug  = ICL_PWR_WELL_CTL_AUX4,
1883 };
1884 
1885 const struct i915_power_well_ops icl_aux_power_well_ops = {
1886     .regs = &icl_aux_power_well_regs,
1887     .sync_hw = hsw_power_well_sync_hw,
1888     .enable = icl_aux_power_well_enable,
1889     .disable = icl_aux_power_well_disable,
1890     .is_enabled = hsw_power_well_enabled,
1891 };
1892 
1893 static const struct i915_power_well_regs icl_ddi_power_well_regs = {
1894     .bios   = ICL_PWR_WELL_CTL_DDI1,
1895     .driver = ICL_PWR_WELL_CTL_DDI2,
1896     .debug  = ICL_PWR_WELL_CTL_DDI4,
1897 };
1898 
1899 const struct i915_power_well_ops icl_ddi_power_well_ops = {
1900     .regs = &icl_ddi_power_well_regs,
1901     .sync_hw = hsw_power_well_sync_hw,
1902     .enable = hsw_power_well_enable,
1903     .disable = hsw_power_well_disable,
1904     .is_enabled = hsw_power_well_enabled,
1905 };
1906 
1907 const struct i915_power_well_ops tgl_tc_cold_off_ops = {
1908     .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
1909     .enable = tgl_tc_cold_off_power_well_enable,
1910     .disable = tgl_tc_cold_off_power_well_disable,
1911     .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
1912 };
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