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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005 
0006 #include "i915_drv.h"
0007 #include "i915_reg.h"
0008 
0009 #include "vlv_sideband_reg.h"
0010 
0011 #include "intel_display_power_map.h"
0012 #include "intel_display_power_well.h"
0013 
0014 #define __LIST_INLINE_ELEMS(__elem_type, ...) \
0015     ((__elem_type[]) { __VA_ARGS__ })
0016 
0017 #define __LIST(__elems) { \
0018     .list = __elems, \
0019     .count = ARRAY_SIZE(__elems), \
0020 }
0021 
0022 #define I915_PW_DOMAINS(...) \
0023     (const struct i915_power_domain_list) \
0024         __LIST(__LIST_INLINE_ELEMS(const enum intel_display_power_domain, __VA_ARGS__))
0025 
0026 #define I915_DECL_PW_DOMAINS(__name, ...) \
0027     static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__)
0028 
0029 /* Zero-length list assigns all power domains, a NULL list assigns none. */
0030 #define I915_PW_DOMAINS_NONE    NULL
0031 #define I915_PW_DOMAINS_ALL /* zero-length list */
0032 
0033 #define I915_PW_INSTANCES(...) \
0034     (const struct i915_power_well_instance_list) \
0035         __LIST(__LIST_INLINE_ELEMS(const struct i915_power_well_instance, __VA_ARGS__))
0036 
0037 #define I915_PW(_name, _domain_list, ...) \
0038     { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
0039 
0040 
0041 struct i915_power_well_desc_list {
0042     const struct i915_power_well_desc *list;
0043     u8 count;
0044 };
0045 
0046 #define I915_PW_DESCRIPTORS(x) __LIST(x)
0047 
0048 
0049 I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
0050 
0051 static const struct i915_power_well_desc i9xx_power_wells_always_on[] = {
0052     {
0053         .instances = &I915_PW_INSTANCES(
0054             I915_PW("always-on", &i9xx_pwdoms_always_on),
0055         ),
0056         .ops = &i9xx_always_on_power_well_ops,
0057         .always_on = true,
0058     },
0059 };
0060 
0061 static const struct i915_power_well_desc_list i9xx_power_wells[] = {
0062     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0063 };
0064 
0065 I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
0066     POWER_DOMAIN_PIPE_A,
0067     POWER_DOMAIN_PIPE_B,
0068     POWER_DOMAIN_PIPE_PANEL_FITTER_A,
0069     POWER_DOMAIN_PIPE_PANEL_FITTER_B,
0070     POWER_DOMAIN_TRANSCODER_A,
0071     POWER_DOMAIN_TRANSCODER_B,
0072     POWER_DOMAIN_INIT);
0073 
0074 static const struct i915_power_well_desc i830_power_wells_main[] = {
0075     {
0076         .instances = &I915_PW_INSTANCES(
0077             I915_PW("pipes", &i830_pwdoms_pipes),
0078         ),
0079         .ops = &i830_pipes_power_well_ops,
0080     },
0081 };
0082 
0083 static const struct i915_power_well_desc_list i830_power_wells[] = {
0084     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0085     I915_PW_DESCRIPTORS(i830_power_wells_main),
0086 };
0087 
0088 I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
0089     POWER_DOMAIN_PIPE_B,
0090     POWER_DOMAIN_PIPE_C,
0091     POWER_DOMAIN_PIPE_PANEL_FITTER_A,
0092     POWER_DOMAIN_PIPE_PANEL_FITTER_B,
0093     POWER_DOMAIN_PIPE_PANEL_FITTER_C,
0094     POWER_DOMAIN_TRANSCODER_A,
0095     POWER_DOMAIN_TRANSCODER_B,
0096     POWER_DOMAIN_TRANSCODER_C,
0097     POWER_DOMAIN_PORT_DDI_LANES_B,
0098     POWER_DOMAIN_PORT_DDI_LANES_C,
0099     POWER_DOMAIN_PORT_DDI_LANES_D,
0100     POWER_DOMAIN_PORT_CRT, /* DDI E */
0101     POWER_DOMAIN_VGA,
0102     POWER_DOMAIN_AUDIO_MMIO,
0103     POWER_DOMAIN_AUDIO_PLAYBACK,
0104     POWER_DOMAIN_INIT);
0105 
0106 static const struct i915_power_well_desc hsw_power_wells_main[] = {
0107     {
0108         .instances = &I915_PW_INSTANCES(
0109             I915_PW("display", &hsw_pwdoms_display,
0110                 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
0111                 .id = HSW_DISP_PW_GLOBAL),
0112         ),
0113         .ops = &hsw_power_well_ops,
0114         .has_vga = true,
0115     },
0116 };
0117 
0118 static const struct i915_power_well_desc_list hsw_power_wells[] = {
0119     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0120     I915_PW_DESCRIPTORS(hsw_power_wells_main),
0121 };
0122 
0123 I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
0124     POWER_DOMAIN_PIPE_B,
0125     POWER_DOMAIN_PIPE_C,
0126     POWER_DOMAIN_PIPE_PANEL_FITTER_B,
0127     POWER_DOMAIN_PIPE_PANEL_FITTER_C,
0128     POWER_DOMAIN_TRANSCODER_A,
0129     POWER_DOMAIN_TRANSCODER_B,
0130     POWER_DOMAIN_TRANSCODER_C,
0131     POWER_DOMAIN_PORT_DDI_LANES_B,
0132     POWER_DOMAIN_PORT_DDI_LANES_C,
0133     POWER_DOMAIN_PORT_DDI_LANES_D,
0134     POWER_DOMAIN_PORT_CRT, /* DDI E */
0135     POWER_DOMAIN_VGA,
0136     POWER_DOMAIN_AUDIO_MMIO,
0137     POWER_DOMAIN_AUDIO_PLAYBACK,
0138     POWER_DOMAIN_INIT);
0139 
0140 static const struct i915_power_well_desc bdw_power_wells_main[] = {
0141     {
0142         .instances = &I915_PW_INSTANCES(
0143             I915_PW("display", &bdw_pwdoms_display,
0144                 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
0145                 .id = HSW_DISP_PW_GLOBAL),
0146         ),
0147         .ops = &hsw_power_well_ops,
0148         .has_vga = true,
0149         .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
0150     },
0151 };
0152 
0153 static const struct i915_power_well_desc_list bdw_power_wells[] = {
0154     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0155     I915_PW_DESCRIPTORS(bdw_power_wells_main),
0156 };
0157 
0158 I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
0159     POWER_DOMAIN_DISPLAY_CORE,
0160     POWER_DOMAIN_PIPE_A,
0161     POWER_DOMAIN_PIPE_B,
0162     POWER_DOMAIN_PIPE_PANEL_FITTER_A,
0163     POWER_DOMAIN_PIPE_PANEL_FITTER_B,
0164     POWER_DOMAIN_TRANSCODER_A,
0165     POWER_DOMAIN_TRANSCODER_B,
0166     POWER_DOMAIN_PORT_DDI_LANES_B,
0167     POWER_DOMAIN_PORT_DDI_LANES_C,
0168     POWER_DOMAIN_PORT_DSI,
0169     POWER_DOMAIN_PORT_CRT,
0170     POWER_DOMAIN_VGA,
0171     POWER_DOMAIN_AUDIO_MMIO,
0172     POWER_DOMAIN_AUDIO_PLAYBACK,
0173     POWER_DOMAIN_AUX_B,
0174     POWER_DOMAIN_AUX_C,
0175     POWER_DOMAIN_GMBUS,
0176     POWER_DOMAIN_INIT);
0177 
0178 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
0179     POWER_DOMAIN_PORT_DDI_LANES_B,
0180     POWER_DOMAIN_PORT_DDI_LANES_C,
0181     POWER_DOMAIN_PORT_CRT,
0182     POWER_DOMAIN_AUX_B,
0183     POWER_DOMAIN_AUX_C,
0184     POWER_DOMAIN_INIT);
0185 
0186 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
0187     POWER_DOMAIN_PORT_DDI_LANES_B,
0188     POWER_DOMAIN_PORT_DDI_LANES_C,
0189     POWER_DOMAIN_AUX_B,
0190     POWER_DOMAIN_AUX_C,
0191     POWER_DOMAIN_INIT);
0192 
0193 static const struct i915_power_well_desc vlv_power_wells_main[] = {
0194     {
0195         .instances = &I915_PW_INSTANCES(
0196             I915_PW("display", &vlv_pwdoms_display,
0197                 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
0198                 .id = VLV_DISP_PW_DISP2D),
0199         ),
0200         .ops = &vlv_display_power_well_ops,
0201     }, {
0202         .instances = &I915_PW_INSTANCES(
0203             I915_PW("dpio-tx-b-01", &vlv_pwdoms_dpio_tx_bc_lanes,
0204                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
0205             I915_PW("dpio-tx-b-23", &vlv_pwdoms_dpio_tx_bc_lanes,
0206                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
0207             I915_PW("dpio-tx-c-01", &vlv_pwdoms_dpio_tx_bc_lanes,
0208                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
0209             I915_PW("dpio-tx-c-23", &vlv_pwdoms_dpio_tx_bc_lanes,
0210                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
0211         ),
0212         .ops = &vlv_dpio_power_well_ops,
0213     }, {
0214         .instances = &I915_PW_INSTANCES(
0215             I915_PW("dpio-common", &vlv_pwdoms_dpio_cmn_bc,
0216                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
0217                 .id = VLV_DISP_PW_DPIO_CMN_BC),
0218         ),
0219         .ops = &vlv_dpio_cmn_power_well_ops,
0220     },
0221 };
0222 
0223 static const struct i915_power_well_desc_list vlv_power_wells[] = {
0224     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0225     I915_PW_DESCRIPTORS(vlv_power_wells_main),
0226 };
0227 
0228 I915_DECL_PW_DOMAINS(chv_pwdoms_display,
0229     POWER_DOMAIN_DISPLAY_CORE,
0230     POWER_DOMAIN_PIPE_A,
0231     POWER_DOMAIN_PIPE_B,
0232     POWER_DOMAIN_PIPE_C,
0233     POWER_DOMAIN_PIPE_PANEL_FITTER_A,
0234     POWER_DOMAIN_PIPE_PANEL_FITTER_B,
0235     POWER_DOMAIN_PIPE_PANEL_FITTER_C,
0236     POWER_DOMAIN_TRANSCODER_A,
0237     POWER_DOMAIN_TRANSCODER_B,
0238     POWER_DOMAIN_TRANSCODER_C,
0239     POWER_DOMAIN_PORT_DDI_LANES_B,
0240     POWER_DOMAIN_PORT_DDI_LANES_C,
0241     POWER_DOMAIN_PORT_DDI_LANES_D,
0242     POWER_DOMAIN_PORT_DSI,
0243     POWER_DOMAIN_VGA,
0244     POWER_DOMAIN_AUDIO_MMIO,
0245     POWER_DOMAIN_AUDIO_PLAYBACK,
0246     POWER_DOMAIN_AUX_B,
0247     POWER_DOMAIN_AUX_C,
0248     POWER_DOMAIN_AUX_D,
0249     POWER_DOMAIN_GMBUS,
0250     POWER_DOMAIN_INIT);
0251 
0252 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
0253     POWER_DOMAIN_PORT_DDI_LANES_B,
0254     POWER_DOMAIN_PORT_DDI_LANES_C,
0255     POWER_DOMAIN_AUX_B,
0256     POWER_DOMAIN_AUX_C,
0257     POWER_DOMAIN_INIT);
0258 
0259 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
0260     POWER_DOMAIN_PORT_DDI_LANES_D,
0261     POWER_DOMAIN_AUX_D,
0262     POWER_DOMAIN_INIT);
0263 
0264 static const struct i915_power_well_desc chv_power_wells_main[] = {
0265     {
0266         /*
0267          * Pipe A power well is the new disp2d well. Pipe B and C
0268          * power wells don't actually exist. Pipe A power well is
0269          * required for any pipe to work.
0270          */
0271         .instances = &I915_PW_INSTANCES(
0272             I915_PW("display", &chv_pwdoms_display),
0273         ),
0274         .ops = &chv_pipe_power_well_ops,
0275     }, {
0276         .instances = &I915_PW_INSTANCES(
0277             I915_PW("dpio-common-bc", &chv_pwdoms_dpio_cmn_bc,
0278                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
0279                 .id = VLV_DISP_PW_DPIO_CMN_BC),
0280             I915_PW("dpio-common-d", &chv_pwdoms_dpio_cmn_d,
0281                 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
0282                 .id = CHV_DISP_PW_DPIO_CMN_D),
0283         ),
0284         .ops = &chv_dpio_cmn_power_well_ops,
0285     },
0286 };
0287 
0288 static const struct i915_power_well_desc_list chv_power_wells[] = {
0289     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0290     I915_PW_DESCRIPTORS(chv_power_wells_main),
0291 };
0292 
0293 #define SKL_PW_2_POWER_DOMAINS \
0294     POWER_DOMAIN_PIPE_B, \
0295     POWER_DOMAIN_PIPE_C, \
0296     POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
0297     POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
0298     POWER_DOMAIN_TRANSCODER_A, \
0299     POWER_DOMAIN_TRANSCODER_B, \
0300     POWER_DOMAIN_TRANSCODER_C, \
0301     POWER_DOMAIN_PORT_DDI_LANES_B, \
0302     POWER_DOMAIN_PORT_DDI_LANES_C, \
0303     POWER_DOMAIN_PORT_DDI_LANES_D, \
0304     POWER_DOMAIN_PORT_DDI_LANES_E, \
0305     POWER_DOMAIN_VGA, \
0306     POWER_DOMAIN_AUDIO_MMIO, \
0307     POWER_DOMAIN_AUDIO_PLAYBACK, \
0308     POWER_DOMAIN_AUX_B, \
0309     POWER_DOMAIN_AUX_C, \
0310     POWER_DOMAIN_AUX_D
0311 
0312 I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
0313     SKL_PW_2_POWER_DOMAINS,
0314     POWER_DOMAIN_INIT);
0315 
0316 I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
0317     SKL_PW_2_POWER_DOMAINS,
0318     POWER_DOMAIN_AUX_A,
0319     POWER_DOMAIN_MODESET,
0320     POWER_DOMAIN_GT_IRQ,
0321     POWER_DOMAIN_INIT);
0322 
0323 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
0324     POWER_DOMAIN_PORT_DDI_IO_A,
0325     POWER_DOMAIN_PORT_DDI_IO_E,
0326     POWER_DOMAIN_INIT);
0327 
0328 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
0329     POWER_DOMAIN_PORT_DDI_IO_B,
0330     POWER_DOMAIN_INIT);
0331 
0332 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
0333     POWER_DOMAIN_PORT_DDI_IO_C,
0334     POWER_DOMAIN_INIT);
0335 
0336 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
0337     POWER_DOMAIN_PORT_DDI_IO_D,
0338     POWER_DOMAIN_INIT);
0339 
0340 static const struct i915_power_well_desc skl_power_wells_pw_1[] = {
0341     {
0342         /* Handled by the DMC firmware */
0343         .instances = &I915_PW_INSTANCES(
0344             I915_PW("PW_1", I915_PW_DOMAINS_NONE,
0345                 .hsw.idx = SKL_PW_CTL_IDX_PW_1,
0346                 .id = SKL_DISP_PW_1),
0347         ),
0348         .ops = &hsw_power_well_ops,
0349         .always_on = true,
0350         .has_fuses = true,
0351     },
0352 };
0353 
0354 static const struct i915_power_well_desc skl_power_wells_main[] = {
0355     {
0356         /* Handled by the DMC firmware */
0357         .instances = &I915_PW_INSTANCES(
0358             I915_PW("MISC_IO", I915_PW_DOMAINS_NONE,
0359                 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
0360                 .id = SKL_DISP_PW_MISC_IO),
0361         ),
0362         .ops = &hsw_power_well_ops,
0363         .always_on = true,
0364     }, {
0365         .instances = &I915_PW_INSTANCES(
0366             I915_PW("DC_off", &skl_pwdoms_dc_off,
0367                 .id = SKL_DISP_DC_OFF),
0368         ),
0369         .ops = &gen9_dc_off_power_well_ops,
0370     }, {
0371         .instances = &I915_PW_INSTANCES(
0372             I915_PW("PW_2", &skl_pwdoms_pw_2,
0373                 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
0374                 .id = SKL_DISP_PW_2),
0375         ),
0376         .ops = &hsw_power_well_ops,
0377         .has_vga = true,
0378         .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
0379         .has_fuses = true,
0380     }, {
0381         .instances = &I915_PW_INSTANCES(
0382             I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E),
0383             I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
0384             I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
0385             I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D),
0386         ),
0387         .ops = &hsw_power_well_ops,
0388     },
0389 };
0390 
0391 static const struct i915_power_well_desc_list skl_power_wells[] = {
0392     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0393     I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
0394     I915_PW_DESCRIPTORS(skl_power_wells_main),
0395 };
0396 
0397 #define BXT_PW_2_POWER_DOMAINS \
0398     POWER_DOMAIN_PIPE_B, \
0399     POWER_DOMAIN_PIPE_C, \
0400     POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
0401     POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
0402     POWER_DOMAIN_TRANSCODER_A, \
0403     POWER_DOMAIN_TRANSCODER_B, \
0404     POWER_DOMAIN_TRANSCODER_C, \
0405     POWER_DOMAIN_PORT_DDI_LANES_B, \
0406     POWER_DOMAIN_PORT_DDI_LANES_C, \
0407     POWER_DOMAIN_VGA, \
0408     POWER_DOMAIN_AUDIO_MMIO, \
0409     POWER_DOMAIN_AUDIO_PLAYBACK, \
0410     POWER_DOMAIN_AUX_B, \
0411     POWER_DOMAIN_AUX_C
0412 
0413 I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
0414     BXT_PW_2_POWER_DOMAINS,
0415     POWER_DOMAIN_INIT);
0416 
0417 I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
0418     BXT_PW_2_POWER_DOMAINS,
0419     POWER_DOMAIN_AUX_A,
0420     POWER_DOMAIN_GMBUS,
0421     POWER_DOMAIN_MODESET,
0422     POWER_DOMAIN_GT_IRQ,
0423     POWER_DOMAIN_INIT);
0424 
0425 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
0426     POWER_DOMAIN_PORT_DDI_LANES_A,
0427     POWER_DOMAIN_AUX_A,
0428     POWER_DOMAIN_INIT);
0429 
0430 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
0431     POWER_DOMAIN_PORT_DDI_LANES_B,
0432     POWER_DOMAIN_PORT_DDI_LANES_C,
0433     POWER_DOMAIN_AUX_B,
0434     POWER_DOMAIN_AUX_C,
0435     POWER_DOMAIN_INIT);
0436 
0437 static const struct i915_power_well_desc bxt_power_wells_main[] = {
0438     {
0439         .instances = &I915_PW_INSTANCES(
0440             I915_PW("DC_off", &bxt_pwdoms_dc_off,
0441                 .id = SKL_DISP_DC_OFF),
0442         ),
0443         .ops = &gen9_dc_off_power_well_ops,
0444     }, {
0445         .instances = &I915_PW_INSTANCES(
0446             I915_PW("PW_2", &bxt_pwdoms_pw_2,
0447                 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
0448                 .id = SKL_DISP_PW_2),
0449         ),
0450         .ops = &hsw_power_well_ops,
0451         .has_vga = true,
0452         .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
0453         .has_fuses = true,
0454     }, {
0455         .instances = &I915_PW_INSTANCES(
0456             I915_PW("dpio-common-a", &bxt_pwdoms_dpio_cmn_a,
0457                 .bxt.phy = DPIO_PHY1,
0458                 .id = BXT_DISP_PW_DPIO_CMN_A),
0459             I915_PW("dpio-common-bc", &bxt_pwdoms_dpio_cmn_bc,
0460                 .bxt.phy = DPIO_PHY0,
0461                 .id = VLV_DISP_PW_DPIO_CMN_BC),
0462         ),
0463         .ops = &bxt_dpio_cmn_power_well_ops,
0464     },
0465 };
0466 
0467 static const struct i915_power_well_desc_list bxt_power_wells[] = {
0468     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0469     I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
0470     I915_PW_DESCRIPTORS(bxt_power_wells_main),
0471 };
0472 
0473 #define GLK_PW_2_POWER_DOMAINS \
0474     POWER_DOMAIN_PIPE_B, \
0475     POWER_DOMAIN_PIPE_C, \
0476     POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
0477     POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
0478     POWER_DOMAIN_TRANSCODER_A, \
0479     POWER_DOMAIN_TRANSCODER_B, \
0480     POWER_DOMAIN_TRANSCODER_C, \
0481     POWER_DOMAIN_PORT_DDI_LANES_B, \
0482     POWER_DOMAIN_PORT_DDI_LANES_C, \
0483     POWER_DOMAIN_VGA, \
0484     POWER_DOMAIN_AUDIO_MMIO, \
0485     POWER_DOMAIN_AUDIO_PLAYBACK, \
0486     POWER_DOMAIN_AUX_B, \
0487     POWER_DOMAIN_AUX_C
0488 
0489 I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
0490     GLK_PW_2_POWER_DOMAINS,
0491     POWER_DOMAIN_INIT);
0492 
0493 I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
0494     GLK_PW_2_POWER_DOMAINS,
0495     POWER_DOMAIN_AUX_A,
0496     POWER_DOMAIN_GMBUS,
0497     POWER_DOMAIN_MODESET,
0498     POWER_DOMAIN_GT_IRQ,
0499     POWER_DOMAIN_INIT);
0500 
0501 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a,   POWER_DOMAIN_PORT_DDI_IO_A);
0502 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b,   POWER_DOMAIN_PORT_DDI_IO_B);
0503 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c,   POWER_DOMAIN_PORT_DDI_IO_C);
0504 
0505 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
0506     POWER_DOMAIN_PORT_DDI_LANES_A,
0507     POWER_DOMAIN_AUX_A,
0508     POWER_DOMAIN_INIT);
0509 
0510 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
0511     POWER_DOMAIN_PORT_DDI_LANES_B,
0512     POWER_DOMAIN_AUX_B,
0513     POWER_DOMAIN_INIT);
0514 
0515 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
0516     POWER_DOMAIN_PORT_DDI_LANES_C,
0517     POWER_DOMAIN_AUX_C,
0518     POWER_DOMAIN_INIT);
0519 
0520 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
0521     POWER_DOMAIN_AUX_A,
0522     POWER_DOMAIN_AUX_IO_A,
0523     POWER_DOMAIN_INIT);
0524 
0525 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
0526     POWER_DOMAIN_AUX_B,
0527     POWER_DOMAIN_INIT);
0528 
0529 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
0530     POWER_DOMAIN_AUX_C,
0531     POWER_DOMAIN_INIT);
0532 
0533 static const struct i915_power_well_desc glk_power_wells_main[] = {
0534     {
0535         .instances = &I915_PW_INSTANCES(
0536             I915_PW("DC_off", &glk_pwdoms_dc_off,
0537                 .id = SKL_DISP_DC_OFF),
0538         ),
0539         .ops = &gen9_dc_off_power_well_ops,
0540     }, {
0541         .instances = &I915_PW_INSTANCES(
0542             I915_PW("PW_2", &glk_pwdoms_pw_2,
0543                 .hsw.idx = SKL_PW_CTL_IDX_PW_2,
0544                 .id = SKL_DISP_PW_2),
0545         ),
0546         .ops = &hsw_power_well_ops,
0547         .has_vga = true,
0548         .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
0549         .has_fuses = true,
0550     }, {
0551         .instances = &I915_PW_INSTANCES(
0552             I915_PW("dpio-common-a", &glk_pwdoms_dpio_cmn_a,
0553                 .bxt.phy = DPIO_PHY1,
0554                 .id = BXT_DISP_PW_DPIO_CMN_A),
0555             I915_PW("dpio-common-b", &glk_pwdoms_dpio_cmn_b,
0556                 .bxt.phy = DPIO_PHY0,
0557                 .id = VLV_DISP_PW_DPIO_CMN_BC),
0558             I915_PW("dpio-common-c", &glk_pwdoms_dpio_cmn_c,
0559                 .bxt.phy = DPIO_PHY2,
0560                 .id = GLK_DISP_PW_DPIO_CMN_C),
0561         ),
0562         .ops = &bxt_dpio_cmn_power_well_ops,
0563     }, {
0564         .instances = &I915_PW_INSTANCES(
0565             I915_PW("AUX_A", &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A),
0566             I915_PW("AUX_B", &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B),
0567             I915_PW("AUX_C", &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C),
0568             I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A),
0569             I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
0570             I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
0571         ),
0572         .ops = &hsw_power_well_ops,
0573     },
0574 };
0575 
0576 static const struct i915_power_well_desc_list glk_power_wells[] = {
0577     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0578     I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
0579     I915_PW_DESCRIPTORS(glk_power_wells_main),
0580 };
0581 
0582 /*
0583  * ICL PW_0/PG_0 domains (HW/DMC control):
0584  * - PCI
0585  * - clocks except port PLL
0586  * - central power except FBC
0587  * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
0588  * ICL PW_1/PG_1 domains (HW/DMC control):
0589  * - DBUF function
0590  * - PIPE_A and its planes, except VGA
0591  * - transcoder EDP + PSR
0592  * - transcoder DSI
0593  * - DDI_A
0594  * - FBC
0595  */
0596 #define ICL_PW_4_POWER_DOMAINS \
0597     POWER_DOMAIN_PIPE_C, \
0598     POWER_DOMAIN_PIPE_PANEL_FITTER_C
0599 
0600 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
0601     ICL_PW_4_POWER_DOMAINS,
0602     POWER_DOMAIN_INIT);
0603     /* VDSC/joining */
0604 
0605 #define ICL_PW_3_POWER_DOMAINS \
0606     ICL_PW_4_POWER_DOMAINS, \
0607     POWER_DOMAIN_PIPE_B, \
0608     POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
0609     POWER_DOMAIN_TRANSCODER_A, \
0610     POWER_DOMAIN_TRANSCODER_B, \
0611     POWER_DOMAIN_TRANSCODER_C, \
0612     POWER_DOMAIN_PORT_DDI_LANES_B, \
0613     POWER_DOMAIN_PORT_DDI_LANES_C, \
0614     POWER_DOMAIN_PORT_DDI_LANES_D, \
0615     POWER_DOMAIN_PORT_DDI_LANES_E, \
0616     POWER_DOMAIN_PORT_DDI_LANES_F, \
0617     POWER_DOMAIN_VGA, \
0618     POWER_DOMAIN_AUDIO_MMIO, \
0619     POWER_DOMAIN_AUDIO_PLAYBACK, \
0620     POWER_DOMAIN_AUX_B, \
0621     POWER_DOMAIN_AUX_C, \
0622     POWER_DOMAIN_AUX_D, \
0623     POWER_DOMAIN_AUX_E, \
0624     POWER_DOMAIN_AUX_F, \
0625     POWER_DOMAIN_AUX_TBT1, \
0626     POWER_DOMAIN_AUX_TBT2, \
0627     POWER_DOMAIN_AUX_TBT3, \
0628     POWER_DOMAIN_AUX_TBT4
0629 
0630 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
0631     ICL_PW_3_POWER_DOMAINS,
0632     POWER_DOMAIN_INIT);
0633     /*
0634      * - transcoder WD
0635      * - KVMR (HW control)
0636      */
0637 
0638 #define ICL_PW_2_POWER_DOMAINS \
0639     ICL_PW_3_POWER_DOMAINS, \
0640     POWER_DOMAIN_TRANSCODER_VDSC_PW2
0641 
0642 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
0643     ICL_PW_2_POWER_DOMAINS,
0644     POWER_DOMAIN_INIT);
0645     /*
0646      * - KVMR (HW control)
0647      */
0648 
0649 I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
0650     ICL_PW_2_POWER_DOMAINS,
0651     POWER_DOMAIN_AUX_A,
0652     POWER_DOMAIN_MODESET,
0653     POWER_DOMAIN_DC_OFF,
0654     POWER_DOMAIN_INIT);
0655 
0656 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d,   POWER_DOMAIN_PORT_DDI_IO_D);
0657 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e,   POWER_DOMAIN_PORT_DDI_IO_E);
0658 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,   POWER_DOMAIN_PORT_DDI_IO_F);
0659 
0660 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
0661     POWER_DOMAIN_AUX_A,
0662     POWER_DOMAIN_AUX_IO_A);
0663 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,      POWER_DOMAIN_AUX_B);
0664 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,      POWER_DOMAIN_AUX_C);
0665 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,      POWER_DOMAIN_AUX_D);
0666 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,      POWER_DOMAIN_AUX_E);
0667 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,      POWER_DOMAIN_AUX_F);
0668 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,   POWER_DOMAIN_AUX_TBT1);
0669 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,   POWER_DOMAIN_AUX_TBT2);
0670 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,   POWER_DOMAIN_AUX_TBT3);
0671 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4,   POWER_DOMAIN_AUX_TBT4);
0672 
0673 static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
0674     {
0675         /* Handled by the DMC firmware */
0676         .instances = &I915_PW_INSTANCES(
0677             I915_PW("PW_1", I915_PW_DOMAINS_NONE,
0678                 .hsw.idx = ICL_PW_CTL_IDX_PW_1,
0679                 .id = SKL_DISP_PW_1),
0680         ),
0681         .ops = &hsw_power_well_ops,
0682         .always_on = true,
0683         .has_fuses = true,
0684     },
0685 };
0686 
0687 static const struct i915_power_well_desc icl_power_wells_main[] = {
0688     {
0689         .instances = &I915_PW_INSTANCES(
0690             I915_PW("DC_off", &icl_pwdoms_dc_off,
0691                 .id = SKL_DISP_DC_OFF),
0692         ),
0693         .ops = &gen9_dc_off_power_well_ops,
0694     }, {
0695         .instances = &I915_PW_INSTANCES(
0696             I915_PW("PW_2", &icl_pwdoms_pw_2,
0697                 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
0698                 .id = SKL_DISP_PW_2),
0699         ),
0700         .ops = &hsw_power_well_ops,
0701         .has_fuses = true,
0702     }, {
0703         .instances = &I915_PW_INSTANCES(
0704             I915_PW("PW_3", &icl_pwdoms_pw_3,
0705                 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
0706                 .id = ICL_DISP_PW_3),
0707         ),
0708         .ops = &hsw_power_well_ops,
0709         .has_vga = true,
0710         .irq_pipe_mask = BIT(PIPE_B),
0711         .has_fuses = true,
0712     }, {
0713         .instances = &I915_PW_INSTANCES(
0714             I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
0715             I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
0716             I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
0717             I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D),
0718             I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E),
0719             I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F),
0720         ),
0721         .ops = &icl_ddi_power_well_ops,
0722     }, {
0723         .instances = &I915_PW_INSTANCES(
0724             I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
0725             I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
0726             I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
0727             I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D),
0728             I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E),
0729             I915_PW("AUX_F", &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F),
0730         ),
0731         .ops = &icl_aux_power_well_ops,
0732     }, {
0733         .instances = &I915_PW_INSTANCES(
0734             I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1),
0735             I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2),
0736             I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3),
0737             I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4),
0738         ),
0739         .ops = &icl_aux_power_well_ops,
0740         .is_tc_tbt = true,
0741     }, {
0742         .instances = &I915_PW_INSTANCES(
0743             I915_PW("PW_4", &icl_pwdoms_pw_4,
0744                 .hsw.idx = ICL_PW_CTL_IDX_PW_4),
0745         ),
0746         .ops = &hsw_power_well_ops,
0747         .irq_pipe_mask = BIT(PIPE_C),
0748         .has_fuses = true,
0749     },
0750 };
0751 
0752 static const struct i915_power_well_desc_list icl_power_wells[] = {
0753     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0754     I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
0755     I915_PW_DESCRIPTORS(icl_power_wells_main),
0756 };
0757 
0758 #define TGL_PW_5_POWER_DOMAINS \
0759     POWER_DOMAIN_PIPE_D, \
0760     POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
0761     POWER_DOMAIN_TRANSCODER_D
0762 
0763 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
0764     TGL_PW_5_POWER_DOMAINS,
0765     POWER_DOMAIN_INIT);
0766 
0767 #define TGL_PW_4_POWER_DOMAINS \
0768     TGL_PW_5_POWER_DOMAINS, \
0769     POWER_DOMAIN_PIPE_C, \
0770     POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
0771     POWER_DOMAIN_TRANSCODER_C
0772 
0773 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
0774     TGL_PW_4_POWER_DOMAINS,
0775     POWER_DOMAIN_INIT);
0776 
0777 #define TGL_PW_3_POWER_DOMAINS \
0778     TGL_PW_4_POWER_DOMAINS, \
0779     POWER_DOMAIN_PIPE_B, \
0780     POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
0781     POWER_DOMAIN_TRANSCODER_B, \
0782     POWER_DOMAIN_PORT_DDI_LANES_TC1, \
0783     POWER_DOMAIN_PORT_DDI_LANES_TC2, \
0784     POWER_DOMAIN_PORT_DDI_LANES_TC3, \
0785     POWER_DOMAIN_PORT_DDI_LANES_TC4, \
0786     POWER_DOMAIN_PORT_DDI_LANES_TC5, \
0787     POWER_DOMAIN_PORT_DDI_LANES_TC6, \
0788     POWER_DOMAIN_VGA, \
0789     POWER_DOMAIN_AUDIO_MMIO, \
0790     POWER_DOMAIN_AUDIO_PLAYBACK, \
0791     POWER_DOMAIN_AUX_USBC1, \
0792     POWER_DOMAIN_AUX_USBC2, \
0793     POWER_DOMAIN_AUX_USBC3, \
0794     POWER_DOMAIN_AUX_USBC4, \
0795     POWER_DOMAIN_AUX_USBC5, \
0796     POWER_DOMAIN_AUX_USBC6, \
0797     POWER_DOMAIN_AUX_TBT1, \
0798     POWER_DOMAIN_AUX_TBT2, \
0799     POWER_DOMAIN_AUX_TBT3, \
0800     POWER_DOMAIN_AUX_TBT4, \
0801     POWER_DOMAIN_AUX_TBT5, \
0802     POWER_DOMAIN_AUX_TBT6
0803 
0804 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
0805     TGL_PW_3_POWER_DOMAINS,
0806     POWER_DOMAIN_INIT);
0807 
0808 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
0809     TGL_PW_3_POWER_DOMAINS,
0810     POWER_DOMAIN_TRANSCODER_VDSC_PW2,
0811     POWER_DOMAIN_INIT);
0812 
0813 I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
0814     TGL_PW_3_POWER_DOMAINS,
0815     POWER_DOMAIN_AUX_A,
0816     POWER_DOMAIN_AUX_B,
0817     POWER_DOMAIN_AUX_C,
0818     POWER_DOMAIN_MODESET,
0819     POWER_DOMAIN_INIT);
0820 
0821 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
0822 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
0823 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
0824 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
0825 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5);
0826 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6);
0827 
0828 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1,  POWER_DOMAIN_AUX_USBC1);
0829 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2,  POWER_DOMAIN_AUX_USBC2);
0830 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3,  POWER_DOMAIN_AUX_USBC3);
0831 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4,  POWER_DOMAIN_AUX_USBC4);
0832 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5,  POWER_DOMAIN_AUX_USBC5);
0833 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6,  POWER_DOMAIN_AUX_USBC6);
0834 
0835 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5,   POWER_DOMAIN_AUX_TBT5);
0836 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6,   POWER_DOMAIN_AUX_TBT6);
0837 
0838 I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
0839     POWER_DOMAIN_AUX_USBC1,
0840     POWER_DOMAIN_AUX_USBC2,
0841     POWER_DOMAIN_AUX_USBC3,
0842     POWER_DOMAIN_AUX_USBC4,
0843     POWER_DOMAIN_AUX_USBC5,
0844     POWER_DOMAIN_AUX_USBC6,
0845     POWER_DOMAIN_AUX_TBT1,
0846     POWER_DOMAIN_AUX_TBT2,
0847     POWER_DOMAIN_AUX_TBT3,
0848     POWER_DOMAIN_AUX_TBT4,
0849     POWER_DOMAIN_AUX_TBT5,
0850     POWER_DOMAIN_AUX_TBT6,
0851     POWER_DOMAIN_TC_COLD_OFF);
0852 
0853 static const struct i915_power_well_desc tgl_power_wells_main[] = {
0854     {
0855         .instances = &I915_PW_INSTANCES(
0856             I915_PW("DC_off", &tgl_pwdoms_dc_off,
0857                 .id = SKL_DISP_DC_OFF),
0858         ),
0859         .ops = &gen9_dc_off_power_well_ops,
0860     }, {
0861         .instances = &I915_PW_INSTANCES(
0862             I915_PW("PW_2", &tgl_pwdoms_pw_2,
0863                 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
0864                 .id = SKL_DISP_PW_2),
0865         ),
0866         .ops = &hsw_power_well_ops,
0867         .has_fuses = true,
0868     }, {
0869         .instances = &I915_PW_INSTANCES(
0870             I915_PW("PW_3", &tgl_pwdoms_pw_3,
0871                 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
0872                 .id = ICL_DISP_PW_3),
0873         ),
0874         .ops = &hsw_power_well_ops,
0875         .has_vga = true,
0876         .irq_pipe_mask = BIT(PIPE_B),
0877         .has_fuses = true,
0878     }, {
0879         .instances = &I915_PW_INSTANCES(
0880             I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
0881             I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
0882             I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
0883             I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
0884             I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
0885             I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
0886             I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
0887             I915_PW("DDI_IO_TC5", &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5),
0888             I915_PW("DDI_IO_TC6", &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6),
0889         ),
0890         .ops = &icl_ddi_power_well_ops,
0891     }, {
0892         .instances = &I915_PW_INSTANCES(
0893             I915_PW("PW_4", &tgl_pwdoms_pw_4,
0894                 .hsw.idx = ICL_PW_CTL_IDX_PW_4),
0895         ),
0896         .ops = &hsw_power_well_ops,
0897         .has_fuses = true,
0898         .irq_pipe_mask = BIT(PIPE_C),
0899     }, {
0900         .instances = &I915_PW_INSTANCES(
0901             I915_PW("PW_5", &tgl_pwdoms_pw_5,
0902                 .hsw.idx = TGL_PW_CTL_IDX_PW_5),
0903         ),
0904         .ops = &hsw_power_well_ops,
0905         .has_fuses = true,
0906         .irq_pipe_mask = BIT(PIPE_D),
0907     },
0908 };
0909 
0910 static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = {
0911     {
0912         .instances = &I915_PW_INSTANCES(
0913             I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off,
0914                 .id = TGL_DISP_PW_TC_COLD_OFF),
0915         ),
0916         .ops = &tgl_tc_cold_off_ops,
0917     },
0918 };
0919 
0920 static const struct i915_power_well_desc tgl_power_wells_aux[] = {
0921     {
0922         .instances = &I915_PW_INSTANCES(
0923             I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
0924             I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
0925             I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
0926             I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
0927             I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
0928             I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
0929             I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
0930             I915_PW("AUX_USBC5", &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5),
0931             I915_PW("AUX_USBC6", &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6),
0932         ),
0933         .ops = &icl_aux_power_well_ops,
0934     }, {
0935         .instances = &I915_PW_INSTANCES(
0936             I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
0937             I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
0938             I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
0939             I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
0940             I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5),
0941             I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6),
0942         ),
0943         .ops = &icl_aux_power_well_ops,
0944         .is_tc_tbt = true,
0945     },
0946 };
0947 
0948 static const struct i915_power_well_desc_list tgl_power_wells[] = {
0949     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0950     I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
0951     I915_PW_DESCRIPTORS(tgl_power_wells_main),
0952     I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off),
0953     I915_PW_DESCRIPTORS(tgl_power_wells_aux),
0954 };
0955 
0956 static const struct i915_power_well_desc_list adls_power_wells[] = {
0957     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
0958     I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
0959     I915_PW_DESCRIPTORS(tgl_power_wells_main),
0960     I915_PW_DESCRIPTORS(tgl_power_wells_aux),
0961 };
0962 
0963 #define RKL_PW_4_POWER_DOMAINS \
0964     POWER_DOMAIN_PIPE_C, \
0965     POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
0966     POWER_DOMAIN_TRANSCODER_C
0967 
0968 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
0969     RKL_PW_4_POWER_DOMAINS,
0970     POWER_DOMAIN_INIT);
0971 
0972 #define RKL_PW_3_POWER_DOMAINS \
0973     RKL_PW_4_POWER_DOMAINS, \
0974     POWER_DOMAIN_PIPE_B, \
0975     POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
0976     POWER_DOMAIN_TRANSCODER_B, \
0977     POWER_DOMAIN_PORT_DDI_LANES_TC1, \
0978     POWER_DOMAIN_PORT_DDI_LANES_TC2, \
0979     POWER_DOMAIN_VGA, \
0980     POWER_DOMAIN_AUDIO_MMIO, \
0981     POWER_DOMAIN_AUDIO_PLAYBACK, \
0982     POWER_DOMAIN_AUX_USBC1, \
0983     POWER_DOMAIN_AUX_USBC2
0984 
0985 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
0986     RKL_PW_3_POWER_DOMAINS,
0987     POWER_DOMAIN_INIT);
0988 
0989 /*
0990  * There is no PW_2/PG_2 on RKL.
0991  *
0992  * RKL PW_1/PG_1 domains (under HW/DMC control):
0993  * - DBUF function (note: registers are in PW0)
0994  * - PIPE_A and its planes and VDSC/joining, except VGA
0995  * - transcoder A
0996  * - DDI_A and DDI_B
0997  * - FBC
0998  *
0999  * RKL PW_0/PG_0 domains (under HW/DMC control):
1000  * - PCI
1001  * - clocks except port PLL
1002  * - shared functions:
1003  *     * interrupts except pipe interrupts
1004  *     * MBus except PIPE_MBUS_DBOX_CTL
1005  *     * DBUF registers
1006  * - central power except FBC
1007  * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
1008  */
1009 
1010 I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
1011     RKL_PW_3_POWER_DOMAINS,
1012     POWER_DOMAIN_AUX_A,
1013     POWER_DOMAIN_AUX_B,
1014     POWER_DOMAIN_MODESET,
1015     POWER_DOMAIN_INIT);
1016 
1017 static const struct i915_power_well_desc rkl_power_wells_main[] = {
1018     {
1019         .instances = &I915_PW_INSTANCES(
1020             I915_PW("DC_off", &rkl_pwdoms_dc_off,
1021                 .id = SKL_DISP_DC_OFF),
1022         ),
1023         .ops = &gen9_dc_off_power_well_ops,
1024     }, {
1025         .instances = &I915_PW_INSTANCES(
1026             I915_PW("PW_3", &rkl_pwdoms_pw_3,
1027                 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
1028                 .id = ICL_DISP_PW_3),
1029         ),
1030         .ops = &hsw_power_well_ops,
1031         .irq_pipe_mask = BIT(PIPE_B),
1032         .has_vga = true,
1033         .has_fuses = true,
1034     }, {
1035         .instances = &I915_PW_INSTANCES(
1036             I915_PW("PW_4", &rkl_pwdoms_pw_4,
1037                 .hsw.idx = ICL_PW_CTL_IDX_PW_4),
1038         ),
1039         .ops = &hsw_power_well_ops,
1040         .has_fuses = true,
1041         .irq_pipe_mask = BIT(PIPE_C),
1042     },
1043 };
1044 
1045 static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = {
1046     {
1047         .instances = &I915_PW_INSTANCES(
1048             I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
1049             I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
1050             I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
1051             I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
1052         ),
1053         .ops = &icl_ddi_power_well_ops,
1054     }, {
1055         .instances = &I915_PW_INSTANCES(
1056             I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
1057             I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
1058             I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
1059             I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
1060         ),
1061         .ops = &icl_aux_power_well_ops,
1062     },
1063 };
1064 
1065 static const struct i915_power_well_desc_list rkl_power_wells[] = {
1066     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1067     I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1068     I915_PW_DESCRIPTORS(rkl_power_wells_main),
1069     I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
1070 };
1071 
1072 /*
1073  * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
1074  */
1075 #define DG1_PW_3_POWER_DOMAINS \
1076     TGL_PW_4_POWER_DOMAINS, \
1077     POWER_DOMAIN_PIPE_B, \
1078     POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
1079     POWER_DOMAIN_TRANSCODER_B, \
1080     POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1081     POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1082     POWER_DOMAIN_VGA, \
1083     POWER_DOMAIN_AUDIO_PLAYBACK, \
1084     POWER_DOMAIN_AUX_USBC1, \
1085     POWER_DOMAIN_AUX_USBC2
1086 
1087 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
1088     DG1_PW_3_POWER_DOMAINS,
1089     POWER_DOMAIN_INIT);
1090 
1091 I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
1092     DG1_PW_3_POWER_DOMAINS,
1093     POWER_DOMAIN_AUDIO_MMIO,
1094     POWER_DOMAIN_AUX_A,
1095     POWER_DOMAIN_AUX_B,
1096     POWER_DOMAIN_MODESET,
1097     POWER_DOMAIN_INIT);
1098 
1099 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
1100     DG1_PW_3_POWER_DOMAINS,
1101     POWER_DOMAIN_TRANSCODER_VDSC_PW2,
1102     POWER_DOMAIN_INIT);
1103 
1104 static const struct i915_power_well_desc dg1_power_wells_main[] = {
1105     {
1106         .instances = &I915_PW_INSTANCES(
1107             I915_PW("DC_off", &dg1_pwdoms_dc_off,
1108                 .id = SKL_DISP_DC_OFF),
1109         ),
1110         .ops = &gen9_dc_off_power_well_ops,
1111     }, {
1112         .instances = &I915_PW_INSTANCES(
1113             I915_PW("PW_2", &dg1_pwdoms_pw_2,
1114                 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
1115                 .id = SKL_DISP_PW_2),
1116         ),
1117         .ops = &hsw_power_well_ops,
1118         .has_fuses = true,
1119     }, {
1120         .instances = &I915_PW_INSTANCES(
1121             I915_PW("PW_3", &dg1_pwdoms_pw_3,
1122                 .hsw.idx = ICL_PW_CTL_IDX_PW_3,
1123                 .id = ICL_DISP_PW_3),
1124         ),
1125         .ops = &hsw_power_well_ops,
1126         .irq_pipe_mask = BIT(PIPE_B),
1127         .has_vga = true,
1128         .has_fuses = true,
1129     }, {
1130         .instances = &I915_PW_INSTANCES(
1131             I915_PW("PW_4", &tgl_pwdoms_pw_4,
1132                 .hsw.idx = ICL_PW_CTL_IDX_PW_4),
1133         ),
1134         .ops = &hsw_power_well_ops,
1135         .has_fuses = true,
1136         .irq_pipe_mask = BIT(PIPE_C),
1137     }, {
1138         .instances = &I915_PW_INSTANCES(
1139             I915_PW("PW_5", &tgl_pwdoms_pw_5,
1140                 .hsw.idx = TGL_PW_CTL_IDX_PW_5),
1141         ),
1142         .ops = &hsw_power_well_ops,
1143         .has_fuses = true,
1144         .irq_pipe_mask = BIT(PIPE_D),
1145     },
1146 };
1147 
1148 static const struct i915_power_well_desc_list dg1_power_wells[] = {
1149     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1150     I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1151     I915_PW_DESCRIPTORS(dg1_power_wells_main),
1152     I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
1153 };
1154 
1155 /*
1156  * XE_LPD Power Domains
1157  *
1158  * Previous platforms required that PG(n-1) be enabled before PG(n).  That
1159  * dependency chain turns into a dependency tree on XE_LPD:
1160  *
1161  *       PG0
1162  *        |
1163  *     --PG1--
1164  *    /       \
1165  *  PGA     --PG2--
1166  *         /   |   \
1167  *       PGB  PGC  PGD
1168  *
1169  * Power wells must be enabled from top to bottom and disabled from bottom
1170  * to top.  This allows pipes to be power gated independently.
1171  */
1172 
1173 #define XELPD_PW_D_POWER_DOMAINS \
1174     POWER_DOMAIN_PIPE_D, \
1175     POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
1176     POWER_DOMAIN_TRANSCODER_D
1177 
1178 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
1179     XELPD_PW_D_POWER_DOMAINS,
1180     POWER_DOMAIN_INIT);
1181 
1182 #define XELPD_PW_C_POWER_DOMAINS \
1183     POWER_DOMAIN_PIPE_C, \
1184     POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
1185     POWER_DOMAIN_TRANSCODER_C
1186 
1187 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
1188     XELPD_PW_C_POWER_DOMAINS,
1189     POWER_DOMAIN_INIT);
1190 
1191 #define XELPD_PW_B_POWER_DOMAINS \
1192     POWER_DOMAIN_PIPE_B, \
1193     POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
1194     POWER_DOMAIN_TRANSCODER_B
1195 
1196 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
1197     XELPD_PW_B_POWER_DOMAINS,
1198     POWER_DOMAIN_INIT);
1199 
1200 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
1201     POWER_DOMAIN_PIPE_A,
1202     POWER_DOMAIN_PIPE_PANEL_FITTER_A,
1203     POWER_DOMAIN_INIT);
1204 
1205 #define XELPD_PW_2_POWER_DOMAINS \
1206     XELPD_PW_B_POWER_DOMAINS, \
1207     XELPD_PW_C_POWER_DOMAINS, \
1208     XELPD_PW_D_POWER_DOMAINS, \
1209     POWER_DOMAIN_PORT_DDI_LANES_C, \
1210     POWER_DOMAIN_PORT_DDI_LANES_D, \
1211     POWER_DOMAIN_PORT_DDI_LANES_E, \
1212     POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1213     POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1214     POWER_DOMAIN_PORT_DDI_LANES_TC3, \
1215     POWER_DOMAIN_PORT_DDI_LANES_TC4, \
1216     POWER_DOMAIN_VGA, \
1217     POWER_DOMAIN_AUDIO_PLAYBACK, \
1218     POWER_DOMAIN_AUX_C, \
1219     POWER_DOMAIN_AUX_D, \
1220     POWER_DOMAIN_AUX_E, \
1221     POWER_DOMAIN_AUX_USBC1, \
1222     POWER_DOMAIN_AUX_USBC2, \
1223     POWER_DOMAIN_AUX_USBC3, \
1224     POWER_DOMAIN_AUX_USBC4, \
1225     POWER_DOMAIN_AUX_TBT1, \
1226     POWER_DOMAIN_AUX_TBT2, \
1227     POWER_DOMAIN_AUX_TBT3, \
1228     POWER_DOMAIN_AUX_TBT4
1229 
1230 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
1231     XELPD_PW_2_POWER_DOMAINS,
1232     POWER_DOMAIN_INIT);
1233 
1234 /*
1235  * XELPD PW_1/PG_1 domains (under HW/DMC control):
1236  *  - DBUF function (registers are in PW0)
1237  *  - Transcoder A
1238  *  - DDI_A and DDI_B
1239  *
1240  * XELPD PW_0/PW_1 domains (under HW/DMC control):
1241  *  - PCI
1242  *  - Clocks except port PLL
1243  *  - Shared functions:
1244  *     * interrupts except pipe interrupts
1245  *     * MBus except PIPE_MBUS_DBOX_CTL
1246  *     * DBUF registers
1247  *  - Central power except FBC
1248  *  - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
1249  */
1250 
1251 I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
1252     XELPD_PW_2_POWER_DOMAINS,
1253     POWER_DOMAIN_PORT_DSI,
1254     POWER_DOMAIN_AUDIO_MMIO,
1255     POWER_DOMAIN_AUX_A,
1256     POWER_DOMAIN_AUX_B,
1257     POWER_DOMAIN_MODESET,
1258     POWER_DOMAIN_INIT);
1259 
1260 static const struct i915_power_well_desc xelpd_power_wells_main[] = {
1261     {
1262         .instances = &I915_PW_INSTANCES(
1263             I915_PW("DC_off", &xelpd_pwdoms_dc_off,
1264                 .id = SKL_DISP_DC_OFF),
1265         ),
1266         .ops = &gen9_dc_off_power_well_ops,
1267     }, {
1268         .instances = &I915_PW_INSTANCES(
1269             I915_PW("PW_2", &xelpd_pwdoms_pw_2,
1270                 .hsw.idx = ICL_PW_CTL_IDX_PW_2,
1271                 .id = SKL_DISP_PW_2),
1272         ),
1273         .ops = &hsw_power_well_ops,
1274         .has_vga = true,
1275         .has_fuses = true,
1276     }, {
1277         .instances = &I915_PW_INSTANCES(
1278             I915_PW("PW_A", &xelpd_pwdoms_pw_a,
1279                 .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
1280         ),
1281         .ops = &hsw_power_well_ops,
1282         .irq_pipe_mask = BIT(PIPE_A),
1283         .has_fuses = true,
1284     }, {
1285         .instances = &I915_PW_INSTANCES(
1286             I915_PW("PW_B", &xelpd_pwdoms_pw_b,
1287                 .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
1288         ),
1289         .ops = &hsw_power_well_ops,
1290         .irq_pipe_mask = BIT(PIPE_B),
1291         .has_fuses = true,
1292     }, {
1293         .instances = &I915_PW_INSTANCES(
1294             I915_PW("PW_C", &xelpd_pwdoms_pw_c,
1295                 .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
1296         ),
1297         .ops = &hsw_power_well_ops,
1298         .irq_pipe_mask = BIT(PIPE_C),
1299         .has_fuses = true,
1300     }, {
1301         .instances = &I915_PW_INSTANCES(
1302             I915_PW("PW_D", &xelpd_pwdoms_pw_d,
1303                 .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
1304         ),
1305         .ops = &hsw_power_well_ops,
1306         .irq_pipe_mask = BIT(PIPE_D),
1307         .has_fuses = true,
1308     }, {
1309         .instances = &I915_PW_INSTANCES(
1310             I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
1311             I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
1312             I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
1313             I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
1314             I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
1315             I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
1316             I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
1317             I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
1318             I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
1319         ),
1320         .ops = &icl_ddi_power_well_ops,
1321     }, {
1322         .instances = &I915_PW_INSTANCES(
1323             I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
1324             I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
1325             I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
1326             I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
1327             I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
1328             I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
1329             I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
1330             I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
1331             I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
1332         ),
1333         .ops = &icl_aux_power_well_ops,
1334         .fixed_enable_delay = true,
1335     }, {
1336         .instances = &I915_PW_INSTANCES(
1337             I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
1338             I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
1339             I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
1340             I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
1341         ),
1342         .ops = &icl_aux_power_well_ops,
1343         .is_tc_tbt = true,
1344     },
1345 };
1346 
1347 static const struct i915_power_well_desc_list xelpd_power_wells[] = {
1348     I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1349     I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1350     I915_PW_DESCRIPTORS(xelpd_power_wells_main),
1351 };
1352 
1353 static void init_power_well_domains(const struct i915_power_well_instance *inst,
1354                     struct i915_power_well *power_well)
1355 {
1356     int j;
1357 
1358     if (!inst->domain_list)
1359         return;
1360 
1361     if (inst->domain_list->count == 0) {
1362         bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
1363 
1364         return;
1365     }
1366 
1367     for (j = 0; j < inst->domain_list->count; j++)
1368         set_bit(inst->domain_list->list[j], power_well->domains.bits);
1369 }
1370 
1371 #define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \
1372     for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \
1373         for ((_inst) = (_desc)->instances->list; \
1374              (_inst) - (_desc)->instances->list < (_desc)->instances->count; \
1375              (_inst)++)
1376 
1377 #define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \
1378     for ((_descs) = (_desc_list); \
1379          (_descs) - (_desc_list) < (_desc_count); \
1380          (_descs)++) \
1381         for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \
1382                               (_desc), (_inst))
1383 
1384 static int
1385 __set_power_wells(struct i915_power_domains *power_domains,
1386           const struct i915_power_well_desc_list *power_well_descs,
1387           int power_well_descs_sz)
1388 {
1389     struct drm_i915_private *i915 = container_of(power_domains,
1390                              struct drm_i915_private,
1391                              power_domains);
1392     u64 power_well_ids = 0;
1393     const struct i915_power_well_desc_list *desc_list;
1394     const struct i915_power_well_desc *desc;
1395     const struct i915_power_well_instance *inst;
1396     int power_well_count = 0;
1397     int plt_idx = 0;
1398 
1399     for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
1400         power_well_count++;
1401 
1402     power_domains->power_well_count = power_well_count;
1403     power_domains->power_wells =
1404                 kcalloc(power_well_count,
1405                     sizeof(*power_domains->power_wells),
1406                     GFP_KERNEL);
1407     if (!power_domains->power_wells)
1408         return -ENOMEM;
1409 
1410     for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {
1411         struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
1412         enum i915_power_well_id id = inst->id;
1413 
1414         pw->desc = desc;
1415         drm_WARN_ON(&i915->drm,
1416                 overflows_type(inst - desc->instances->list, pw->instance_idx));
1417         pw->instance_idx = inst - desc->instances->list;
1418 
1419         init_power_well_domains(inst, pw);
1420 
1421         plt_idx++;
1422 
1423         if (id == DISP_PW_ID_NONE)
1424             continue;
1425 
1426         drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
1427         drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
1428         power_well_ids |= BIT_ULL(id);
1429     }
1430 
1431     return 0;
1432 }
1433 
1434 #define set_power_wells(power_domains, __power_well_descs) \
1435     __set_power_wells(power_domains, __power_well_descs, \
1436               ARRAY_SIZE(__power_well_descs))
1437 
1438 /**
1439  * intel_display_power_map_init - initialize power domain -> power well mappings
1440  * @power_domains: power domain state
1441  *
1442  * Creates all the power wells for the current platform, initializes the
1443  * dynamic state for them and initializes the mapping of each power well to
1444  * all the power domains the power well belongs to.
1445  */
1446 int intel_display_power_map_init(struct i915_power_domains *power_domains)
1447 {
1448     struct drm_i915_private *i915 = container_of(power_domains,
1449                              struct drm_i915_private,
1450                              power_domains);
1451     /*
1452      * The enabling order will be from lower to higher indexed wells,
1453      * the disabling order is reversed.
1454      */
1455     if (!HAS_DISPLAY(i915)) {
1456         power_domains->power_well_count = 0;
1457         return 0;
1458     }
1459 
1460     if (DISPLAY_VER(i915) >= 13)
1461         return set_power_wells(power_domains, xelpd_power_wells);
1462     else if (IS_DG1(i915))
1463         return set_power_wells(power_domains, dg1_power_wells);
1464     else if (IS_ALDERLAKE_S(i915))
1465         return set_power_wells(power_domains, adls_power_wells);
1466     else if (IS_ROCKETLAKE(i915))
1467         return set_power_wells(power_domains, rkl_power_wells);
1468     else if (DISPLAY_VER(i915) == 12)
1469         return set_power_wells(power_domains, tgl_power_wells);
1470     else if (DISPLAY_VER(i915) == 11)
1471         return set_power_wells(power_domains, icl_power_wells);
1472     else if (IS_GEMINILAKE(i915))
1473         return set_power_wells(power_domains, glk_power_wells);
1474     else if (IS_BROXTON(i915))
1475         return set_power_wells(power_domains, bxt_power_wells);
1476     else if (DISPLAY_VER(i915) == 9)
1477         return set_power_wells(power_domains, skl_power_wells);
1478     else if (IS_CHERRYVIEW(i915))
1479         return set_power_wells(power_domains, chv_power_wells);
1480     else if (IS_BROADWELL(i915))
1481         return set_power_wells(power_domains, bdw_power_wells);
1482     else if (IS_HASWELL(i915))
1483         return set_power_wells(power_domains, hsw_power_wells);
1484     else if (IS_VALLEYVIEW(i915))
1485         return set_power_wells(power_domains, vlv_power_wells);
1486     else if (IS_I830(i915))
1487         return set_power_wells(power_domains, i830_power_wells);
1488     else
1489         return set_power_wells(power_domains, i9xx_power_wells);
1490 }
1491 
1492 /**
1493  * intel_display_power_map_cleanup - clean up power domain -> power well mappings
1494  * @power_domains: power domain state
1495  *
1496  * Cleans up all the state that was initialized by intel_display_power_map_init().
1497  */
1498 void intel_display_power_map_cleanup(struct i915_power_domains *power_domains)
1499 {
1500     kfree(power_domains->power_wells);
1501 }
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