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0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005 
0006 #ifndef __INTEL_DISPLAY_POWER_H__
0007 #define __INTEL_DISPLAY_POWER_H__
0008 
0009 #include "intel_runtime_pm.h"
0010 
0011 enum aux_ch;
0012 enum dpio_channel;
0013 enum dpio_phy;
0014 enum port;
0015 struct drm_i915_private;
0016 struct i915_power_well;
0017 struct intel_encoder;
0018 
0019 /*
0020  * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
0021  * consecutive, so that the pipe,transcoder,port -> power domain macros
0022  * work correctly.
0023  */
0024 enum intel_display_power_domain {
0025     POWER_DOMAIN_DISPLAY_CORE,
0026     POWER_DOMAIN_PIPE_A,
0027     POWER_DOMAIN_PIPE_B,
0028     POWER_DOMAIN_PIPE_C,
0029     POWER_DOMAIN_PIPE_D,
0030     POWER_DOMAIN_PIPE_PANEL_FITTER_A,
0031     POWER_DOMAIN_PIPE_PANEL_FITTER_B,
0032     POWER_DOMAIN_PIPE_PANEL_FITTER_C,
0033     POWER_DOMAIN_PIPE_PANEL_FITTER_D,
0034     POWER_DOMAIN_TRANSCODER_A,
0035     POWER_DOMAIN_TRANSCODER_B,
0036     POWER_DOMAIN_TRANSCODER_C,
0037     POWER_DOMAIN_TRANSCODER_D,
0038     POWER_DOMAIN_TRANSCODER_EDP,
0039     POWER_DOMAIN_TRANSCODER_DSI_A,
0040     POWER_DOMAIN_TRANSCODER_DSI_C,
0041 
0042     /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
0043     POWER_DOMAIN_TRANSCODER_VDSC_PW2,
0044 
0045     POWER_DOMAIN_PORT_DDI_LANES_A,
0046     POWER_DOMAIN_PORT_DDI_LANES_B,
0047     POWER_DOMAIN_PORT_DDI_LANES_C,
0048     POWER_DOMAIN_PORT_DDI_LANES_D,
0049     POWER_DOMAIN_PORT_DDI_LANES_E,
0050     POWER_DOMAIN_PORT_DDI_LANES_F,
0051 
0052     POWER_DOMAIN_PORT_DDI_LANES_TC1,
0053     POWER_DOMAIN_PORT_DDI_LANES_TC2,
0054     POWER_DOMAIN_PORT_DDI_LANES_TC3,
0055     POWER_DOMAIN_PORT_DDI_LANES_TC4,
0056     POWER_DOMAIN_PORT_DDI_LANES_TC5,
0057     POWER_DOMAIN_PORT_DDI_LANES_TC6,
0058 
0059     POWER_DOMAIN_PORT_DDI_IO_A,
0060     POWER_DOMAIN_PORT_DDI_IO_B,
0061     POWER_DOMAIN_PORT_DDI_IO_C,
0062     POWER_DOMAIN_PORT_DDI_IO_D,
0063     POWER_DOMAIN_PORT_DDI_IO_E,
0064     POWER_DOMAIN_PORT_DDI_IO_F,
0065 
0066     POWER_DOMAIN_PORT_DDI_IO_TC1,
0067     POWER_DOMAIN_PORT_DDI_IO_TC2,
0068     POWER_DOMAIN_PORT_DDI_IO_TC3,
0069     POWER_DOMAIN_PORT_DDI_IO_TC4,
0070     POWER_DOMAIN_PORT_DDI_IO_TC5,
0071     POWER_DOMAIN_PORT_DDI_IO_TC6,
0072 
0073     POWER_DOMAIN_PORT_DSI,
0074     POWER_DOMAIN_PORT_CRT,
0075     POWER_DOMAIN_PORT_OTHER,
0076     POWER_DOMAIN_VGA,
0077     POWER_DOMAIN_AUDIO_MMIO,
0078     POWER_DOMAIN_AUDIO_PLAYBACK,
0079     POWER_DOMAIN_AUX_A,
0080     POWER_DOMAIN_AUX_B,
0081     POWER_DOMAIN_AUX_C,
0082     POWER_DOMAIN_AUX_D,
0083     POWER_DOMAIN_AUX_E,
0084     POWER_DOMAIN_AUX_F,
0085 
0086     POWER_DOMAIN_AUX_USBC1,
0087     POWER_DOMAIN_AUX_USBC2,
0088     POWER_DOMAIN_AUX_USBC3,
0089     POWER_DOMAIN_AUX_USBC4,
0090     POWER_DOMAIN_AUX_USBC5,
0091     POWER_DOMAIN_AUX_USBC6,
0092 
0093     POWER_DOMAIN_AUX_IO_A,
0094 
0095     POWER_DOMAIN_AUX_TBT1,
0096     POWER_DOMAIN_AUX_TBT2,
0097     POWER_DOMAIN_AUX_TBT3,
0098     POWER_DOMAIN_AUX_TBT4,
0099     POWER_DOMAIN_AUX_TBT5,
0100     POWER_DOMAIN_AUX_TBT6,
0101 
0102     POWER_DOMAIN_GMBUS,
0103     POWER_DOMAIN_MODESET,
0104     POWER_DOMAIN_GT_IRQ,
0105     POWER_DOMAIN_DC_OFF,
0106     POWER_DOMAIN_TC_COLD_OFF,
0107     POWER_DOMAIN_INIT,
0108 
0109     POWER_DOMAIN_NUM,
0110     POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
0111 };
0112 
0113 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
0114 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
0115         ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
0116 #define POWER_DOMAIN_TRANSCODER(tran) \
0117     ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
0118      (tran) + POWER_DOMAIN_TRANSCODER_A)
0119 
0120 struct intel_power_domain_mask {
0121     DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
0122 };
0123 
0124 struct i915_power_domains {
0125     /*
0126      * Power wells needed for initialization at driver init and suspend
0127      * time are on. They are kept on until after the first modeset.
0128      */
0129     bool initializing;
0130     bool display_core_suspended;
0131     int power_well_count;
0132 
0133     intel_wakeref_t init_wakeref;
0134     intel_wakeref_t disable_wakeref;
0135 
0136     struct mutex lock;
0137     int domain_use_count[POWER_DOMAIN_NUM];
0138 
0139     struct delayed_work async_put_work;
0140     intel_wakeref_t async_put_wakeref;
0141     struct intel_power_domain_mask async_put_domains[2];
0142 
0143     struct i915_power_well *power_wells;
0144 };
0145 
0146 struct intel_display_power_domain_set {
0147     struct intel_power_domain_mask mask;
0148 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
0149     intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
0150 #endif
0151 };
0152 
0153 #define for_each_power_domain(__domain, __mask)             \
0154     for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++)   \
0155         for_each_if(test_bit((__domain), (__mask)->bits))
0156 
0157 int intel_power_domains_init(struct drm_i915_private *dev_priv);
0158 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
0159 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
0160 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
0161 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
0162 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
0163 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
0164                  enum i915_drm_suspend_mode);
0165 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
0166 void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
0167 
0168 void intel_display_power_suspend_late(struct drm_i915_private *i915);
0169 void intel_display_power_resume_early(struct drm_i915_private *i915);
0170 void intel_display_power_suspend(struct drm_i915_private *i915);
0171 void intel_display_power_resume(struct drm_i915_private *i915);
0172 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
0173                          u32 state);
0174 
0175 const char *
0176 intel_display_power_domain_str(enum intel_display_power_domain domain);
0177 
0178 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
0179                     enum intel_display_power_domain domain);
0180 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
0181                       enum intel_display_power_domain domain);
0182 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
0183                     enum intel_display_power_domain domain);
0184 intel_wakeref_t
0185 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
0186                    enum intel_display_power_domain domain);
0187 void __intel_display_power_put_async(struct drm_i915_private *i915,
0188                      enum intel_display_power_domain domain,
0189                      intel_wakeref_t wakeref);
0190 void intel_display_power_flush_work(struct drm_i915_private *i915);
0191 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
0192 void intel_display_power_put(struct drm_i915_private *dev_priv,
0193                  enum intel_display_power_domain domain,
0194                  intel_wakeref_t wakeref);
0195 static inline void
0196 intel_display_power_put_async(struct drm_i915_private *i915,
0197                   enum intel_display_power_domain domain,
0198                   intel_wakeref_t wakeref)
0199 {
0200     __intel_display_power_put_async(i915, domain, wakeref);
0201 }
0202 #else
0203 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
0204                        enum intel_display_power_domain domain);
0205 
0206 static inline void
0207 intel_display_power_put(struct drm_i915_private *i915,
0208             enum intel_display_power_domain domain,
0209             intel_wakeref_t wakeref)
0210 {
0211     intel_display_power_put_unchecked(i915, domain);
0212 }
0213 
0214 static inline void
0215 intel_display_power_put_async(struct drm_i915_private *i915,
0216                   enum intel_display_power_domain domain,
0217                   intel_wakeref_t wakeref)
0218 {
0219     __intel_display_power_put_async(i915, domain, -1);
0220 }
0221 #endif
0222 
0223 void
0224 intel_display_power_get_in_set(struct drm_i915_private *i915,
0225                    struct intel_display_power_domain_set *power_domain_set,
0226                    enum intel_display_power_domain domain);
0227 
0228 bool
0229 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
0230                       struct intel_display_power_domain_set *power_domain_set,
0231                       enum intel_display_power_domain domain);
0232 
0233 void
0234 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
0235                     struct intel_display_power_domain_set *power_domain_set,
0236                     struct intel_power_domain_mask *mask);
0237 
0238 static inline void
0239 intel_display_power_put_all_in_set(struct drm_i915_private *i915,
0240                    struct intel_display_power_domain_set *power_domain_set)
0241 {
0242     intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
0243 }
0244 
0245 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
0246 
0247 enum intel_display_power_domain
0248 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
0249 enum intel_display_power_domain
0250 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
0251 enum intel_display_power_domain
0252 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
0253 enum intel_display_power_domain
0254 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
0255 
0256 /*
0257  * FIXME: We should probably switch this to a 0-based scheme to be consistent
0258  * with how we now name/number DBUF_CTL instances.
0259  */
0260 enum dbuf_slice {
0261     DBUF_S1,
0262     DBUF_S2,
0263     DBUF_S3,
0264     DBUF_S4,
0265     I915_MAX_DBUF_SLICES
0266 };
0267 
0268 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
0269                  u8 req_slices);
0270 
0271 #define with_intel_display_power(i915, domain, wf) \
0272     for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
0273          intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
0274 
0275 #define with_intel_display_power_if_enabled(i915, domain, wf) \
0276     for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
0277          intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
0278 
0279 #endif /* __INTEL_DISPLAY_POWER_H__ */
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