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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2020 Intel Corporation
0004  */
0005 
0006 #include <linux/string_helpers.h>
0007 
0008 #include <drm/drm_debugfs.h>
0009 #include <drm/drm_fourcc.h>
0010 
0011 #include "i915_debugfs.h"
0012 #include "intel_de.h"
0013 #include "intel_display_debugfs.h"
0014 #include "intel_display_power.h"
0015 #include "intel_display_power_well.h"
0016 #include "intel_display_types.h"
0017 #include "intel_dmc.h"
0018 #include "intel_dp.h"
0019 #include "intel_dp_mst.h"
0020 #include "intel_drrs.h"
0021 #include "intel_fbc.h"
0022 #include "intel_fbdev.h"
0023 #include "intel_hdcp.h"
0024 #include "intel_hdmi.h"
0025 #include "intel_panel.h"
0026 #include "intel_pm.h"
0027 #include "intel_psr.h"
0028 #include "intel_sprite.h"
0029 
0030 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
0031 {
0032     return to_i915(node->minor->dev);
0033 }
0034 
0035 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
0036 {
0037     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0038 
0039     seq_printf(m, "FB tracking busy bits: 0x%08x\n",
0040            dev_priv->fb_tracking.busy_bits);
0041 
0042     seq_printf(m, "FB tracking flip bits: 0x%08x\n",
0043            dev_priv->fb_tracking.flip_bits);
0044 
0045     return 0;
0046 }
0047 
0048 static int i915_ips_status(struct seq_file *m, void *unused)
0049 {
0050     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0051     intel_wakeref_t wakeref;
0052 
0053     if (!HAS_IPS(dev_priv))
0054         return -ENODEV;
0055 
0056     wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
0057 
0058     seq_printf(m, "Enabled by kernel parameter: %s\n",
0059            str_yes_no(dev_priv->params.enable_ips));
0060 
0061     if (DISPLAY_VER(dev_priv) >= 8) {
0062         seq_puts(m, "Currently: unknown\n");
0063     } else {
0064         if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE)
0065             seq_puts(m, "Currently: enabled\n");
0066         else
0067             seq_puts(m, "Currently: disabled\n");
0068     }
0069 
0070     intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
0071 
0072     return 0;
0073 }
0074 
0075 static int i915_sr_status(struct seq_file *m, void *unused)
0076 {
0077     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0078     intel_wakeref_t wakeref;
0079     bool sr_enabled = false;
0080 
0081     wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
0082 
0083     if (DISPLAY_VER(dev_priv) >= 9)
0084         /* no global SR status; inspect per-plane WM */;
0085     else if (HAS_PCH_SPLIT(dev_priv))
0086         sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
0087     else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
0088          IS_I945G(dev_priv) || IS_I945GM(dev_priv))
0089         sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
0090     else if (IS_I915GM(dev_priv))
0091         sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
0092     else if (IS_PINEVIEW(dev_priv))
0093         sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
0094     else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0095         sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
0096 
0097     intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
0098 
0099     seq_printf(m, "self-refresh: %s\n", str_enabled_disabled(sr_enabled));
0100 
0101     return 0;
0102 }
0103 
0104 static int i915_opregion(struct seq_file *m, void *unused)
0105 {
0106     struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
0107 
0108     if (opregion->header)
0109         seq_write(m, opregion->header, OPREGION_SIZE);
0110 
0111     return 0;
0112 }
0113 
0114 static int i915_vbt(struct seq_file *m, void *unused)
0115 {
0116     struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
0117 
0118     if (opregion->vbt)
0119         seq_write(m, opregion->vbt, opregion->vbt_size);
0120 
0121     return 0;
0122 }
0123 
0124 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
0125 {
0126     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0127     struct drm_device *dev = &dev_priv->drm;
0128     struct intel_framebuffer *fbdev_fb = NULL;
0129     struct drm_framebuffer *drm_fb;
0130 
0131 #ifdef CONFIG_DRM_FBDEV_EMULATION
0132     fbdev_fb = intel_fbdev_framebuffer(dev_priv->fbdev);
0133     if (fbdev_fb) {
0134         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
0135                fbdev_fb->base.width,
0136                fbdev_fb->base.height,
0137                fbdev_fb->base.format->depth,
0138                fbdev_fb->base.format->cpp[0] * 8,
0139                fbdev_fb->base.modifier,
0140                drm_framebuffer_read_refcount(&fbdev_fb->base));
0141         i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base));
0142         seq_putc(m, '\n');
0143     }
0144 #endif
0145 
0146     mutex_lock(&dev->mode_config.fb_lock);
0147     drm_for_each_fb(drm_fb, dev) {
0148         struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
0149         if (fb == fbdev_fb)
0150             continue;
0151 
0152         seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
0153                fb->base.width,
0154                fb->base.height,
0155                fb->base.format->depth,
0156                fb->base.format->cpp[0] * 8,
0157                fb->base.modifier,
0158                drm_framebuffer_read_refcount(&fb->base));
0159         i915_debugfs_describe_obj(m, intel_fb_obj(&fb->base));
0160         seq_putc(m, '\n');
0161     }
0162     mutex_unlock(&dev->mode_config.fb_lock);
0163 
0164     return 0;
0165 }
0166 
0167 static int i915_psr_sink_status_show(struct seq_file *m, void *data)
0168 {
0169     u8 val;
0170     static const char * const sink_status[] = {
0171         "inactive",
0172         "transition to active, capture and display",
0173         "active, display from RFB",
0174         "active, capture and display on sink device timings",
0175         "transition to inactive, capture and display, timing re-sync",
0176         "reserved",
0177         "reserved",
0178         "sink internal error",
0179     };
0180     struct drm_connector *connector = m->private;
0181     struct intel_dp *intel_dp =
0182         intel_attached_dp(to_intel_connector(connector));
0183     int ret;
0184 
0185     if (!CAN_PSR(intel_dp)) {
0186         seq_puts(m, "PSR Unsupported\n");
0187         return -ENODEV;
0188     }
0189 
0190     if (connector->status != connector_status_connected)
0191         return -ENODEV;
0192 
0193     ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
0194 
0195     if (ret == 1) {
0196         const char *str = "unknown";
0197 
0198         val &= DP_PSR_SINK_STATE_MASK;
0199         if (val < ARRAY_SIZE(sink_status))
0200             str = sink_status[val];
0201         seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
0202     } else {
0203         return ret;
0204     }
0205 
0206     return 0;
0207 }
0208 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
0209 
0210 static void
0211 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
0212 {
0213     struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
0214     const char *status = "unknown";
0215     u32 val, status_val;
0216 
0217     if (intel_dp->psr.psr2_enabled) {
0218         static const char * const live_status[] = {
0219             "IDLE",
0220             "CAPTURE",
0221             "CAPTURE_FS",
0222             "SLEEP",
0223             "BUFON_FW",
0224             "ML_UP",
0225             "SU_STANDBY",
0226             "FAST_SLEEP",
0227             "DEEP_SLEEP",
0228             "BUF_ON",
0229             "TG_ON"
0230         };
0231         val = intel_de_read(dev_priv,
0232                     EDP_PSR2_STATUS(intel_dp->psr.transcoder));
0233         status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
0234         if (status_val < ARRAY_SIZE(live_status))
0235             status = live_status[status_val];
0236     } else {
0237         static const char * const live_status[] = {
0238             "IDLE",
0239             "SRDONACK",
0240             "SRDENT",
0241             "BUFOFF",
0242             "BUFON",
0243             "AUXACK",
0244             "SRDOFFACK",
0245             "SRDENT_ON",
0246         };
0247         val = intel_de_read(dev_priv,
0248                     EDP_PSR_STATUS(intel_dp->psr.transcoder));
0249         status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
0250                   EDP_PSR_STATUS_STATE_SHIFT;
0251         if (status_val < ARRAY_SIZE(live_status))
0252             status = live_status[status_val];
0253     }
0254 
0255     seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
0256 }
0257 
0258 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
0259 {
0260     struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
0261     struct intel_psr *psr = &intel_dp->psr;
0262     intel_wakeref_t wakeref;
0263     const char *status;
0264     bool enabled;
0265     u32 val;
0266 
0267     seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support));
0268     if (psr->sink_support)
0269         seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
0270     seq_puts(m, "\n");
0271 
0272     if (!psr->sink_support)
0273         return 0;
0274 
0275     wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
0276     mutex_lock(&psr->lock);
0277 
0278     if (psr->enabled)
0279         status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
0280     else
0281         status = "disabled";
0282     seq_printf(m, "PSR mode: %s\n", status);
0283 
0284     if (!psr->enabled) {
0285         seq_printf(m, "PSR sink not reliable: %s\n",
0286                str_yes_no(psr->sink_not_reliable));
0287 
0288         goto unlock;
0289     }
0290 
0291     if (psr->psr2_enabled) {
0292         val = intel_de_read(dev_priv,
0293                     EDP_PSR2_CTL(intel_dp->psr.transcoder));
0294         enabled = val & EDP_PSR2_ENABLE;
0295     } else {
0296         val = intel_de_read(dev_priv,
0297                     EDP_PSR_CTL(intel_dp->psr.transcoder));
0298         enabled = val & EDP_PSR_ENABLE;
0299     }
0300     seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
0301            str_enabled_disabled(enabled), val);
0302     psr_source_status(intel_dp, m);
0303     seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
0304            psr->busy_frontbuffer_bits);
0305 
0306     /*
0307      * SKL+ Perf counter is reset to 0 everytime DC state is entered
0308      */
0309     if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0310         val = intel_de_read(dev_priv,
0311                     EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
0312         val &= EDP_PSR_PERF_CNT_MASK;
0313         seq_printf(m, "Performance counter: %u\n", val);
0314     }
0315 
0316     if (psr->debug & I915_PSR_DEBUG_IRQ) {
0317         seq_printf(m, "Last attempted entry at: %lld\n",
0318                psr->last_entry_attempt);
0319         seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
0320     }
0321 
0322     if (psr->psr2_enabled) {
0323         u32 su_frames_val[3];
0324         int frame;
0325 
0326         /*
0327          * Reading all 3 registers before hand to minimize crossing a
0328          * frame boundary between register reads
0329          */
0330         for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
0331             val = intel_de_read(dev_priv,
0332                         PSR2_SU_STATUS(intel_dp->psr.transcoder, frame));
0333             su_frames_val[frame / 3] = val;
0334         }
0335 
0336         seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
0337 
0338         for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) {
0339             u32 su_blocks;
0340 
0341             su_blocks = su_frames_val[frame / 3] &
0342                     PSR2_SU_STATUS_MASK(frame);
0343             su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame);
0344             seq_printf(m, "%d\t%d\n", frame, su_blocks);
0345         }
0346 
0347         seq_printf(m, "PSR2 selective fetch: %s\n",
0348                str_enabled_disabled(psr->psr2_sel_fetch_enabled));
0349     }
0350 
0351 unlock:
0352     mutex_unlock(&psr->lock);
0353     intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
0354 
0355     return 0;
0356 }
0357 
0358 static int i915_edp_psr_status(struct seq_file *m, void *data)
0359 {
0360     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0361     struct intel_dp *intel_dp = NULL;
0362     struct intel_encoder *encoder;
0363 
0364     if (!HAS_PSR(dev_priv))
0365         return -ENODEV;
0366 
0367     /* Find the first EDP which supports PSR */
0368     for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
0369         intel_dp = enc_to_intel_dp(encoder);
0370         break;
0371     }
0372 
0373     if (!intel_dp)
0374         return -ENODEV;
0375 
0376     return intel_psr_status(m, intel_dp);
0377 }
0378 
0379 static int
0380 i915_edp_psr_debug_set(void *data, u64 val)
0381 {
0382     struct drm_i915_private *dev_priv = data;
0383     struct intel_encoder *encoder;
0384     intel_wakeref_t wakeref;
0385     int ret = -ENODEV;
0386 
0387     if (!HAS_PSR(dev_priv))
0388         return ret;
0389 
0390     for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
0391         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0392 
0393         drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
0394 
0395         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
0396 
0397         // TODO: split to each transcoder's PSR debug state
0398         ret = intel_psr_debug_set(intel_dp, val);
0399 
0400         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
0401     }
0402 
0403     return ret;
0404 }
0405 
0406 static int
0407 i915_edp_psr_debug_get(void *data, u64 *val)
0408 {
0409     struct drm_i915_private *dev_priv = data;
0410     struct intel_encoder *encoder;
0411 
0412     if (!HAS_PSR(dev_priv))
0413         return -ENODEV;
0414 
0415     for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
0416         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0417 
0418         // TODO: split to each transcoder's PSR debug state
0419         *val = READ_ONCE(intel_dp->psr.debug);
0420         return 0;
0421     }
0422 
0423     return -ENODEV;
0424 }
0425 
0426 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
0427             i915_edp_psr_debug_get, i915_edp_psr_debug_set,
0428             "%llu\n");
0429 
0430 static int i915_power_domain_info(struct seq_file *m, void *unused)
0431 {
0432     struct drm_i915_private *i915 = node_to_i915(m->private);
0433 
0434     intel_display_power_debug(i915, m);
0435 
0436     return 0;
0437 }
0438 
0439 static void intel_seq_print_mode(struct seq_file *m, int tabs,
0440                  const struct drm_display_mode *mode)
0441 {
0442     int i;
0443 
0444     for (i = 0; i < tabs; i++)
0445         seq_putc(m, '\t');
0446 
0447     seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
0448 }
0449 
0450 static void intel_encoder_info(struct seq_file *m,
0451                    struct intel_crtc *crtc,
0452                    struct intel_encoder *encoder)
0453 {
0454     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0455     struct drm_connector_list_iter conn_iter;
0456     struct drm_connector *connector;
0457 
0458     seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
0459            encoder->base.base.id, encoder->base.name);
0460 
0461     drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
0462     drm_for_each_connector_iter(connector, &conn_iter) {
0463         const struct drm_connector_state *conn_state =
0464             connector->state;
0465 
0466         if (conn_state->best_encoder != &encoder->base)
0467             continue;
0468 
0469         seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n",
0470                connector->base.id, connector->name);
0471     }
0472     drm_connector_list_iter_end(&conn_iter);
0473 }
0474 
0475 static void intel_panel_info(struct seq_file *m,
0476                  struct intel_connector *connector)
0477 {
0478     const struct drm_display_mode *fixed_mode;
0479 
0480     if (list_empty(&connector->panel.fixed_modes))
0481         return;
0482 
0483     seq_puts(m, "\tfixed modes:\n");
0484 
0485     list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head)
0486         intel_seq_print_mode(m, 2, fixed_mode);
0487 }
0488 
0489 static void intel_hdcp_info(struct seq_file *m,
0490                 struct intel_connector *intel_connector)
0491 {
0492     bool hdcp_cap, hdcp2_cap;
0493 
0494     if (!intel_connector->hdcp.shim) {
0495         seq_puts(m, "No Connector Support");
0496         goto out;
0497     }
0498 
0499     hdcp_cap = intel_hdcp_capable(intel_connector);
0500     hdcp2_cap = intel_hdcp2_capable(intel_connector);
0501 
0502     if (hdcp_cap)
0503         seq_puts(m, "HDCP1.4 ");
0504     if (hdcp2_cap)
0505         seq_puts(m, "HDCP2.2 ");
0506 
0507     if (!hdcp_cap && !hdcp2_cap)
0508         seq_puts(m, "None");
0509 
0510 out:
0511     seq_puts(m, "\n");
0512 }
0513 
0514 static void intel_dp_info(struct seq_file *m,
0515               struct intel_connector *intel_connector)
0516 {
0517     struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
0518     struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
0519     const struct drm_property_blob *edid = intel_connector->base.edid_blob_ptr;
0520 
0521     seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
0522     seq_printf(m, "\taudio support: %s\n",
0523            str_yes_no(intel_dp->has_audio));
0524 
0525     drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
0526                 edid ? edid->data : NULL, &intel_dp->aux);
0527 }
0528 
0529 static void intel_dp_mst_info(struct seq_file *m,
0530                   struct intel_connector *intel_connector)
0531 {
0532     bool has_audio = intel_connector->port->has_audio;
0533 
0534     seq_printf(m, "\taudio support: %s\n", str_yes_no(has_audio));
0535 }
0536 
0537 static void intel_hdmi_info(struct seq_file *m,
0538                 struct intel_connector *intel_connector)
0539 {
0540     struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
0541     struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder);
0542 
0543     seq_printf(m, "\taudio support: %s\n",
0544            str_yes_no(intel_hdmi->has_audio));
0545 }
0546 
0547 static void intel_connector_info(struct seq_file *m,
0548                  struct drm_connector *connector)
0549 {
0550     struct intel_connector *intel_connector = to_intel_connector(connector);
0551     const struct drm_connector_state *conn_state = connector->state;
0552     struct intel_encoder *encoder =
0553         to_intel_encoder(conn_state->best_encoder);
0554     const struct drm_display_mode *mode;
0555 
0556     seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n",
0557            connector->base.id, connector->name,
0558            drm_get_connector_status_name(connector->status));
0559 
0560     if (connector->status == connector_status_disconnected)
0561         return;
0562 
0563     seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
0564            connector->display_info.width_mm,
0565            connector->display_info.height_mm);
0566     seq_printf(m, "\tsubpixel order: %s\n",
0567            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
0568     seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev);
0569 
0570     if (!encoder)
0571         return;
0572 
0573     switch (connector->connector_type) {
0574     case DRM_MODE_CONNECTOR_DisplayPort:
0575     case DRM_MODE_CONNECTOR_eDP:
0576         if (encoder->type == INTEL_OUTPUT_DP_MST)
0577             intel_dp_mst_info(m, intel_connector);
0578         else
0579             intel_dp_info(m, intel_connector);
0580         break;
0581     case DRM_MODE_CONNECTOR_HDMIA:
0582         if (encoder->type == INTEL_OUTPUT_HDMI ||
0583             encoder->type == INTEL_OUTPUT_DDI)
0584             intel_hdmi_info(m, intel_connector);
0585         break;
0586     default:
0587         break;
0588     }
0589 
0590     seq_puts(m, "\tHDCP version: ");
0591     intel_hdcp_info(m, intel_connector);
0592 
0593     seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc);
0594 
0595     intel_panel_info(m, intel_connector);
0596 
0597     seq_printf(m, "\tmodes:\n");
0598     list_for_each_entry(mode, &connector->modes, head)
0599         intel_seq_print_mode(m, 2, mode);
0600 }
0601 
0602 static const char *plane_type(enum drm_plane_type type)
0603 {
0604     switch (type) {
0605     case DRM_PLANE_TYPE_OVERLAY:
0606         return "OVL";
0607     case DRM_PLANE_TYPE_PRIMARY:
0608         return "PRI";
0609     case DRM_PLANE_TYPE_CURSOR:
0610         return "CUR";
0611     /*
0612      * Deliberately omitting default: to generate compiler warnings
0613      * when a new drm_plane_type gets added.
0614      */
0615     }
0616 
0617     return "unknown";
0618 }
0619 
0620 static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation)
0621 {
0622     /*
0623      * According to doc only one DRM_MODE_ROTATE_ is allowed but this
0624      * will print them all to visualize if the values are misused
0625      */
0626     snprintf(buf, bufsize,
0627          "%s%s%s%s%s%s(0x%08x)",
0628          (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
0629          (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
0630          (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
0631          (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
0632          (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
0633          (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
0634          rotation);
0635 }
0636 
0637 static const char *plane_visibility(const struct intel_plane_state *plane_state)
0638 {
0639     if (plane_state->uapi.visible)
0640         return "visible";
0641 
0642     if (plane_state->planar_slave)
0643         return "planar-slave";
0644 
0645     return "hidden";
0646 }
0647 
0648 static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane)
0649 {
0650     const struct intel_plane_state *plane_state =
0651         to_intel_plane_state(plane->base.state);
0652     const struct drm_framebuffer *fb = plane_state->uapi.fb;
0653     struct drm_rect src, dst;
0654     char rot_str[48];
0655 
0656     src = drm_plane_state_src(&plane_state->uapi);
0657     dst = drm_plane_state_dest(&plane_state->uapi);
0658 
0659     plane_rotation(rot_str, sizeof(rot_str),
0660                plane_state->uapi.rotation);
0661 
0662     seq_puts(m, "\t\tuapi: [FB:");
0663     if (fb)
0664         seq_printf(m, "%d] %p4cc,0x%llx,%dx%d", fb->base.id,
0665                &fb->format->format, fb->modifier, fb->width,
0666                fb->height);
0667     else
0668         seq_puts(m, "0] n/a,0x0,0x0,");
0669     seq_printf(m, ", visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT
0670            ", rotation=%s\n", plane_visibility(plane_state),
0671            DRM_RECT_FP_ARG(&src), DRM_RECT_ARG(&dst), rot_str);
0672 
0673     if (plane_state->planar_linked_plane)
0674         seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n",
0675                plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name,
0676                plane_state->planar_slave ? "slave" : "master");
0677 }
0678 
0679 static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
0680 {
0681     const struct intel_plane_state *plane_state =
0682         to_intel_plane_state(plane->base.state);
0683     const struct drm_framebuffer *fb = plane_state->hw.fb;
0684     char rot_str[48];
0685 
0686     if (!fb)
0687         return;
0688 
0689     plane_rotation(rot_str, sizeof(rot_str),
0690                plane_state->hw.rotation);
0691 
0692     seq_printf(m, "\t\thw: [FB:%d] %p4cc,0x%llx,%dx%d, visible=%s, src="
0693            DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
0694            fb->base.id, &fb->format->format,
0695            fb->modifier, fb->width, fb->height,
0696            str_yes_no(plane_state->uapi.visible),
0697            DRM_RECT_FP_ARG(&plane_state->uapi.src),
0698            DRM_RECT_ARG(&plane_state->uapi.dst),
0699            rot_str);
0700 }
0701 
0702 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
0703 {
0704     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0705     struct intel_plane *plane;
0706 
0707     for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
0708         seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
0709                plane->base.base.id, plane->base.name,
0710                plane_type(plane->base.type));
0711         intel_plane_uapi_info(m, plane);
0712         intel_plane_hw_info(m, plane);
0713     }
0714 }
0715 
0716 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc)
0717 {
0718     const struct intel_crtc_state *crtc_state =
0719         to_intel_crtc_state(crtc->base.state);
0720     int num_scalers = crtc->num_scalers;
0721     int i;
0722 
0723     /* Not all platformas have a scaler */
0724     if (num_scalers) {
0725         seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
0726                num_scalers,
0727                crtc_state->scaler_state.scaler_users,
0728                crtc_state->scaler_state.scaler_id);
0729 
0730         for (i = 0; i < num_scalers; i++) {
0731             const struct intel_scaler *sc =
0732                 &crtc_state->scaler_state.scalers[i];
0733 
0734             seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
0735                    i, str_yes_no(sc->in_use), sc->mode);
0736         }
0737         seq_puts(m, "\n");
0738     } else {
0739         seq_puts(m, "\tNo scalers available on this platform\n");
0740     }
0741 }
0742 
0743 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
0744 static void crtc_updates_info(struct seq_file *m,
0745                   struct intel_crtc *crtc,
0746                   const char *hdr)
0747 {
0748     u64 count;
0749     int row;
0750 
0751     count = 0;
0752     for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++)
0753         count += crtc->debug.vbl.times[row];
0754     seq_printf(m, "%sUpdates: %llu\n", hdr, count);
0755     if (!count)
0756         return;
0757 
0758     for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) {
0759         char columns[80] = "       |";
0760         unsigned int x;
0761 
0762         if (row & 1) {
0763             const char *units;
0764 
0765             if (row > 10) {
0766                 x = 1000000;
0767                 units = "ms";
0768             } else {
0769                 x = 1000;
0770                 units = "us";
0771             }
0772 
0773             snprintf(columns, sizeof(columns), "%4ld%s |",
0774                  DIV_ROUND_CLOSEST(BIT(row + 9), x), units);
0775         }
0776 
0777         if (crtc->debug.vbl.times[row]) {
0778             x = ilog2(crtc->debug.vbl.times[row]);
0779             memset(columns + 8, '*', x);
0780             columns[8 + x] = '\0';
0781         }
0782 
0783         seq_printf(m, "%s%s\n", hdr, columns);
0784     }
0785 
0786     seq_printf(m, "%sMin update: %lluns\n",
0787            hdr, crtc->debug.vbl.min);
0788     seq_printf(m, "%sMax update: %lluns\n",
0789            hdr, crtc->debug.vbl.max);
0790     seq_printf(m, "%sAverage update: %lluns\n",
0791            hdr, div64_u64(crtc->debug.vbl.sum,  count));
0792     seq_printf(m, "%sOverruns > %uus: %u\n",
0793            hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over);
0794 }
0795 
0796 static int crtc_updates_show(struct seq_file *m, void *data)
0797 {
0798     crtc_updates_info(m, m->private, "");
0799     return 0;
0800 }
0801 
0802 static int crtc_updates_open(struct inode *inode, struct file *file)
0803 {
0804     return single_open(file, crtc_updates_show, inode->i_private);
0805 }
0806 
0807 static ssize_t crtc_updates_write(struct file *file,
0808                   const char __user *ubuf,
0809                   size_t len, loff_t *offp)
0810 {
0811     struct seq_file *m = file->private_data;
0812     struct intel_crtc *crtc = m->private;
0813 
0814     /* May race with an update. Meh. */
0815     memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl));
0816 
0817     return len;
0818 }
0819 
0820 static const struct file_operations crtc_updates_fops = {
0821     .owner = THIS_MODULE,
0822     .open = crtc_updates_open,
0823     .read = seq_read,
0824     .llseek = seq_lseek,
0825     .release = single_release,
0826     .write = crtc_updates_write
0827 };
0828 
0829 static void crtc_updates_add(struct drm_crtc *crtc)
0830 {
0831     debugfs_create_file("i915_update_info", 0644, crtc->debugfs_entry,
0832                 to_intel_crtc(crtc), &crtc_updates_fops);
0833 }
0834 
0835 #else
0836 static void crtc_updates_info(struct seq_file *m,
0837                   struct intel_crtc *crtc,
0838                   const char *hdr)
0839 {
0840 }
0841 
0842 static void crtc_updates_add(struct drm_crtc *crtc)
0843 {
0844 }
0845 #endif
0846 
0847 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
0848 {
0849     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0850     const struct intel_crtc_state *crtc_state =
0851         to_intel_crtc_state(crtc->base.state);
0852     struct intel_encoder *encoder;
0853 
0854     seq_printf(m, "[CRTC:%d:%s]:\n",
0855            crtc->base.base.id, crtc->base.name);
0856 
0857     seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n",
0858            str_yes_no(crtc_state->uapi.enable),
0859            str_yes_no(crtc_state->uapi.active),
0860            DRM_MODE_ARG(&crtc_state->uapi.mode));
0861 
0862     seq_printf(m, "\thw: enable=%s, active=%s\n",
0863            str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active));
0864     seq_printf(m, "\tadjusted_mode=" DRM_MODE_FMT "\n",
0865            DRM_MODE_ARG(&crtc_state->hw.adjusted_mode));
0866     seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n",
0867            DRM_MODE_ARG(&crtc_state->hw.pipe_mode));
0868 
0869     seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n",
0870            DRM_RECT_ARG(&crtc_state->pipe_src),
0871            str_yes_no(crtc_state->dither), crtc_state->pipe_bpp);
0872 
0873     intel_scaler_info(m, crtc);
0874 
0875     if (crtc_state->bigjoiner_pipes)
0876         seq_printf(m, "\tLinked to 0x%x pipes as a %s\n",
0877                crtc_state->bigjoiner_pipes,
0878                intel_crtc_is_bigjoiner_slave(crtc_state) ? "slave" : "master");
0879 
0880     for_each_intel_encoder_mask(&dev_priv->drm, encoder,
0881                     crtc_state->uapi.encoder_mask)
0882         intel_encoder_info(m, crtc, encoder);
0883 
0884     intel_plane_info(m, crtc);
0885 
0886     seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n",
0887            str_yes_no(!crtc->cpu_fifo_underrun_disabled),
0888            str_yes_no(!crtc->pch_fifo_underrun_disabled));
0889 
0890     crtc_updates_info(m, crtc, "\t");
0891 }
0892 
0893 static int i915_display_info(struct seq_file *m, void *unused)
0894 {
0895     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0896     struct drm_device *dev = &dev_priv->drm;
0897     struct intel_crtc *crtc;
0898     struct drm_connector *connector;
0899     struct drm_connector_list_iter conn_iter;
0900     intel_wakeref_t wakeref;
0901 
0902     wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
0903 
0904     drm_modeset_lock_all(dev);
0905 
0906     seq_printf(m, "CRTC info\n");
0907     seq_printf(m, "---------\n");
0908     for_each_intel_crtc(dev, crtc)
0909         intel_crtc_info(m, crtc);
0910 
0911     seq_printf(m, "\n");
0912     seq_printf(m, "Connector info\n");
0913     seq_printf(m, "--------------\n");
0914     drm_connector_list_iter_begin(dev, &conn_iter);
0915     drm_for_each_connector_iter(connector, &conn_iter)
0916         intel_connector_info(m, connector);
0917     drm_connector_list_iter_end(&conn_iter);
0918 
0919     drm_modeset_unlock_all(dev);
0920 
0921     intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
0922 
0923     return 0;
0924 }
0925 
0926 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
0927 {
0928     struct drm_i915_private *dev_priv = node_to_i915(m->private);
0929     struct drm_device *dev = &dev_priv->drm;
0930     int i;
0931 
0932     drm_modeset_lock_all(dev);
0933 
0934     seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
0935            dev_priv->dpll.ref_clks.nssc,
0936            dev_priv->dpll.ref_clks.ssc);
0937 
0938     for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
0939         struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
0940 
0941         seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
0942                pll->info->id);
0943         seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
0944                pll->state.pipe_mask, pll->active_mask,
0945                str_yes_no(pll->on));
0946         seq_printf(m, " tracked hardware state:\n");
0947         seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
0948         seq_printf(m, " dpll_md: 0x%08x\n",
0949                pll->state.hw_state.dpll_md);
0950         seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
0951         seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
0952         seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
0953         seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
0954         seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
0955         seq_printf(m, " div0:    0x%08x\n", pll->state.hw_state.div0);
0956         seq_printf(m, " mg_refclkin_ctl:        0x%08x\n",
0957                pll->state.hw_state.mg_refclkin_ctl);
0958         seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
0959                pll->state.hw_state.mg_clktop2_coreclkctl1);
0960         seq_printf(m, " mg_clktop2_hsclkctl:    0x%08x\n",
0961                pll->state.hw_state.mg_clktop2_hsclkctl);
0962         seq_printf(m, " mg_pll_div0:  0x%08x\n",
0963                pll->state.hw_state.mg_pll_div0);
0964         seq_printf(m, " mg_pll_div1:  0x%08x\n",
0965                pll->state.hw_state.mg_pll_div1);
0966         seq_printf(m, " mg_pll_lf:    0x%08x\n",
0967                pll->state.hw_state.mg_pll_lf);
0968         seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
0969                pll->state.hw_state.mg_pll_frac_lock);
0970         seq_printf(m, " mg_pll_ssc:   0x%08x\n",
0971                pll->state.hw_state.mg_pll_ssc);
0972         seq_printf(m, " mg_pll_bias:  0x%08x\n",
0973                pll->state.hw_state.mg_pll_bias);
0974         seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
0975                pll->state.hw_state.mg_pll_tdc_coldst_bias);
0976     }
0977     drm_modeset_unlock_all(dev);
0978 
0979     return 0;
0980 }
0981 
0982 static int i915_ipc_status_show(struct seq_file *m, void *data)
0983 {
0984     struct drm_i915_private *dev_priv = m->private;
0985 
0986     seq_printf(m, "Isochronous Priority Control: %s\n",
0987             str_yes_no(dev_priv->ipc_enabled));
0988     return 0;
0989 }
0990 
0991 static int i915_ipc_status_open(struct inode *inode, struct file *file)
0992 {
0993     struct drm_i915_private *dev_priv = inode->i_private;
0994 
0995     if (!HAS_IPC(dev_priv))
0996         return -ENODEV;
0997 
0998     return single_open(file, i915_ipc_status_show, dev_priv);
0999 }
1000 
1001 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
1002                      size_t len, loff_t *offp)
1003 {
1004     struct seq_file *m = file->private_data;
1005     struct drm_i915_private *dev_priv = m->private;
1006     intel_wakeref_t wakeref;
1007     bool enable;
1008     int ret;
1009 
1010     ret = kstrtobool_from_user(ubuf, len, &enable);
1011     if (ret < 0)
1012         return ret;
1013 
1014     with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
1015         if (!dev_priv->ipc_enabled && enable)
1016             drm_info(&dev_priv->drm,
1017                  "Enabling IPC: WM will be proper only after next commit\n");
1018         dev_priv->ipc_enabled = enable;
1019         intel_enable_ipc(dev_priv);
1020     }
1021 
1022     return len;
1023 }
1024 
1025 static const struct file_operations i915_ipc_status_fops = {
1026     .owner = THIS_MODULE,
1027     .open = i915_ipc_status_open,
1028     .read = seq_read,
1029     .llseek = seq_lseek,
1030     .release = single_release,
1031     .write = i915_ipc_status_write
1032 };
1033 
1034 static int i915_ddb_info(struct seq_file *m, void *unused)
1035 {
1036     struct drm_i915_private *dev_priv = node_to_i915(m->private);
1037     struct drm_device *dev = &dev_priv->drm;
1038     struct skl_ddb_entry *entry;
1039     struct intel_crtc *crtc;
1040 
1041     if (DISPLAY_VER(dev_priv) < 9)
1042         return -ENODEV;
1043 
1044     drm_modeset_lock_all(dev);
1045 
1046     seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
1047 
1048     for_each_intel_crtc(&dev_priv->drm, crtc) {
1049         struct intel_crtc_state *crtc_state =
1050             to_intel_crtc_state(crtc->base.state);
1051         enum pipe pipe = crtc->pipe;
1052         enum plane_id plane_id;
1053 
1054         seq_printf(m, "Pipe %c\n", pipe_name(pipe));
1055 
1056         for_each_plane_id_on_crtc(crtc, plane_id) {
1057             entry = &crtc_state->wm.skl.plane_ddb[plane_id];
1058             seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
1059                    entry->start, entry->end,
1060                    skl_ddb_entry_size(entry));
1061         }
1062 
1063         entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
1064         seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
1065                entry->end, skl_ddb_entry_size(entry));
1066     }
1067 
1068     drm_modeset_unlock_all(dev);
1069 
1070     return 0;
1071 }
1072 
1073 static int i915_drrs_status(struct seq_file *m, void *unused)
1074 {
1075     struct drm_i915_private *dev_priv = node_to_i915(m->private);
1076     struct drm_connector_list_iter conn_iter;
1077     struct intel_connector *connector;
1078     struct intel_crtc *crtc;
1079 
1080     drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
1081     for_each_intel_connector_iter(connector, &conn_iter) {
1082         seq_printf(m, "[CONNECTOR:%d:%s] DRRS type: %s\n",
1083                connector->base.base.id, connector->base.name,
1084                intel_drrs_type_str(intel_panel_drrs_type(connector)));
1085     }
1086     drm_connector_list_iter_end(&conn_iter);
1087 
1088     seq_puts(m, "\n");
1089 
1090     for_each_intel_crtc(&dev_priv->drm, crtc) {
1091         const struct intel_crtc_state *crtc_state =
1092             to_intel_crtc_state(crtc->base.state);
1093 
1094         seq_printf(m, "[CRTC:%d:%s]:\n",
1095                crtc->base.base.id, crtc->base.name);
1096 
1097         mutex_lock(&crtc->drrs.mutex);
1098 
1099         /* DRRS Supported */
1100         seq_printf(m, "\tDRRS Enabled: %s\n",
1101                str_yes_no(crtc_state->has_drrs));
1102 
1103         seq_printf(m, "\tDRRS Active: %s\n",
1104                str_yes_no(intel_drrs_is_active(crtc)));
1105 
1106         seq_printf(m, "\tBusy_frontbuffer_bits: 0x%X\n",
1107                crtc->drrs.busy_frontbuffer_bits);
1108 
1109         seq_printf(m, "\tDRRS refresh rate: %s\n",
1110                crtc->drrs.refresh_rate == DRRS_REFRESH_RATE_LOW ?
1111                "low" : "high");
1112 
1113         mutex_unlock(&crtc->drrs.mutex);
1114     }
1115 
1116     return 0;
1117 }
1118 
1119 static bool
1120 intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
1121                   enum i915_power_well_id power_well_id)
1122 {
1123     intel_wakeref_t wakeref;
1124     bool is_enabled;
1125 
1126     wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1127     is_enabled = intel_display_power_well_is_enabled(i915,
1128                              power_well_id);
1129     intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1130 
1131     return is_enabled;
1132 }
1133 
1134 static int i915_lpsp_status(struct seq_file *m, void *unused)
1135 {
1136     struct drm_i915_private *i915 = node_to_i915(m->private);
1137     bool lpsp_enabled = false;
1138 
1139     if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
1140         lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2);
1141     } else if (IS_DISPLAY_VER(i915, 11, 12)) {
1142         lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3);
1143     } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1144         lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL);
1145     } else {
1146         seq_puts(m, "LPSP: not supported\n");
1147         return 0;
1148     }
1149 
1150     seq_printf(m, "LPSP: %s\n", str_enabled_disabled(lpsp_enabled));
1151 
1152     return 0;
1153 }
1154 
1155 static int i915_dp_mst_info(struct seq_file *m, void *unused)
1156 {
1157     struct drm_i915_private *dev_priv = node_to_i915(m->private);
1158     struct drm_device *dev = &dev_priv->drm;
1159     struct intel_encoder *intel_encoder;
1160     struct intel_digital_port *dig_port;
1161     struct drm_connector *connector;
1162     struct drm_connector_list_iter conn_iter;
1163 
1164     drm_connector_list_iter_begin(dev, &conn_iter);
1165     drm_for_each_connector_iter(connector, &conn_iter) {
1166         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
1167             continue;
1168 
1169         intel_encoder = intel_attached_encoder(to_intel_connector(connector));
1170         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
1171             continue;
1172 
1173         dig_port = enc_to_dig_port(intel_encoder);
1174         if (!intel_dp_mst_source_support(&dig_port->dp))
1175             continue;
1176 
1177         seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n",
1178                dig_port->base.base.base.id,
1179                dig_port->base.base.name);
1180         drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr);
1181     }
1182     drm_connector_list_iter_end(&conn_iter);
1183 
1184     return 0;
1185 }
1186 
1187 static ssize_t i915_displayport_test_active_write(struct file *file,
1188                           const char __user *ubuf,
1189                           size_t len, loff_t *offp)
1190 {
1191     char *input_buffer;
1192     int status = 0;
1193     struct drm_device *dev;
1194     struct drm_connector *connector;
1195     struct drm_connector_list_iter conn_iter;
1196     struct intel_dp *intel_dp;
1197     int val = 0;
1198 
1199     dev = ((struct seq_file *)file->private_data)->private;
1200 
1201     if (len == 0)
1202         return 0;
1203 
1204     input_buffer = memdup_user_nul(ubuf, len);
1205     if (IS_ERR(input_buffer))
1206         return PTR_ERR(input_buffer);
1207 
1208     drm_dbg(&to_i915(dev)->drm,
1209         "Copied %d bytes from user\n", (unsigned int)len);
1210 
1211     drm_connector_list_iter_begin(dev, &conn_iter);
1212     drm_for_each_connector_iter(connector, &conn_iter) {
1213         struct intel_encoder *encoder;
1214 
1215         if (connector->connector_type !=
1216             DRM_MODE_CONNECTOR_DisplayPort)
1217             continue;
1218 
1219         encoder = to_intel_encoder(connector->encoder);
1220         if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1221             continue;
1222 
1223         if (encoder && connector->status == connector_status_connected) {
1224             intel_dp = enc_to_intel_dp(encoder);
1225             status = kstrtoint(input_buffer, 10, &val);
1226             if (status < 0)
1227                 break;
1228             drm_dbg(&to_i915(dev)->drm,
1229                 "Got %d for test active\n", val);
1230             /* To prevent erroneous activation of the compliance
1231              * testing code, only accept an actual value of 1 here
1232              */
1233             if (val == 1)
1234                 intel_dp->compliance.test_active = true;
1235             else
1236                 intel_dp->compliance.test_active = false;
1237         }
1238     }
1239     drm_connector_list_iter_end(&conn_iter);
1240     kfree(input_buffer);
1241     if (status < 0)
1242         return status;
1243 
1244     *offp += len;
1245     return len;
1246 }
1247 
1248 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
1249 {
1250     struct drm_i915_private *dev_priv = m->private;
1251     struct drm_device *dev = &dev_priv->drm;
1252     struct drm_connector *connector;
1253     struct drm_connector_list_iter conn_iter;
1254     struct intel_dp *intel_dp;
1255 
1256     drm_connector_list_iter_begin(dev, &conn_iter);
1257     drm_for_each_connector_iter(connector, &conn_iter) {
1258         struct intel_encoder *encoder;
1259 
1260         if (connector->connector_type !=
1261             DRM_MODE_CONNECTOR_DisplayPort)
1262             continue;
1263 
1264         encoder = to_intel_encoder(connector->encoder);
1265         if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1266             continue;
1267 
1268         if (encoder && connector->status == connector_status_connected) {
1269             intel_dp = enc_to_intel_dp(encoder);
1270             if (intel_dp->compliance.test_active)
1271                 seq_puts(m, "1");
1272             else
1273                 seq_puts(m, "0");
1274         } else
1275             seq_puts(m, "0");
1276     }
1277     drm_connector_list_iter_end(&conn_iter);
1278 
1279     return 0;
1280 }
1281 
1282 static int i915_displayport_test_active_open(struct inode *inode,
1283                          struct file *file)
1284 {
1285     return single_open(file, i915_displayport_test_active_show,
1286                inode->i_private);
1287 }
1288 
1289 static const struct file_operations i915_displayport_test_active_fops = {
1290     .owner = THIS_MODULE,
1291     .open = i915_displayport_test_active_open,
1292     .read = seq_read,
1293     .llseek = seq_lseek,
1294     .release = single_release,
1295     .write = i915_displayport_test_active_write
1296 };
1297 
1298 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
1299 {
1300     struct drm_i915_private *dev_priv = m->private;
1301     struct drm_device *dev = &dev_priv->drm;
1302     struct drm_connector *connector;
1303     struct drm_connector_list_iter conn_iter;
1304     struct intel_dp *intel_dp;
1305 
1306     drm_connector_list_iter_begin(dev, &conn_iter);
1307     drm_for_each_connector_iter(connector, &conn_iter) {
1308         struct intel_encoder *encoder;
1309 
1310         if (connector->connector_type !=
1311             DRM_MODE_CONNECTOR_DisplayPort)
1312             continue;
1313 
1314         encoder = to_intel_encoder(connector->encoder);
1315         if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1316             continue;
1317 
1318         if (encoder && connector->status == connector_status_connected) {
1319             intel_dp = enc_to_intel_dp(encoder);
1320             if (intel_dp->compliance.test_type ==
1321                 DP_TEST_LINK_EDID_READ)
1322                 seq_printf(m, "%lx",
1323                        intel_dp->compliance.test_data.edid);
1324             else if (intel_dp->compliance.test_type ==
1325                  DP_TEST_LINK_VIDEO_PATTERN) {
1326                 seq_printf(m, "hdisplay: %d\n",
1327                        intel_dp->compliance.test_data.hdisplay);
1328                 seq_printf(m, "vdisplay: %d\n",
1329                        intel_dp->compliance.test_data.vdisplay);
1330                 seq_printf(m, "bpc: %u\n",
1331                        intel_dp->compliance.test_data.bpc);
1332             } else if (intel_dp->compliance.test_type ==
1333                    DP_TEST_LINK_PHY_TEST_PATTERN) {
1334                 seq_printf(m, "pattern: %d\n",
1335                        intel_dp->compliance.test_data.phytest.phy_pattern);
1336                 seq_printf(m, "Number of lanes: %d\n",
1337                        intel_dp->compliance.test_data.phytest.num_lanes);
1338                 seq_printf(m, "Link Rate: %d\n",
1339                        intel_dp->compliance.test_data.phytest.link_rate);
1340                 seq_printf(m, "level: %02x\n",
1341                        intel_dp->train_set[0]);
1342             }
1343         } else
1344             seq_puts(m, "0");
1345     }
1346     drm_connector_list_iter_end(&conn_iter);
1347 
1348     return 0;
1349 }
1350 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data);
1351 
1352 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
1353 {
1354     struct drm_i915_private *dev_priv = m->private;
1355     struct drm_device *dev = &dev_priv->drm;
1356     struct drm_connector *connector;
1357     struct drm_connector_list_iter conn_iter;
1358     struct intel_dp *intel_dp;
1359 
1360     drm_connector_list_iter_begin(dev, &conn_iter);
1361     drm_for_each_connector_iter(connector, &conn_iter) {
1362         struct intel_encoder *encoder;
1363 
1364         if (connector->connector_type !=
1365             DRM_MODE_CONNECTOR_DisplayPort)
1366             continue;
1367 
1368         encoder = to_intel_encoder(connector->encoder);
1369         if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
1370             continue;
1371 
1372         if (encoder && connector->status == connector_status_connected) {
1373             intel_dp = enc_to_intel_dp(encoder);
1374             seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);
1375         } else
1376             seq_puts(m, "0");
1377     }
1378     drm_connector_list_iter_end(&conn_iter);
1379 
1380     return 0;
1381 }
1382 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
1383 
1384 static void wm_latency_show(struct seq_file *m, const u16 wm[8])
1385 {
1386     struct drm_i915_private *dev_priv = m->private;
1387     struct drm_device *dev = &dev_priv->drm;
1388     int level;
1389     int num_levels;
1390 
1391     if (IS_CHERRYVIEW(dev_priv))
1392         num_levels = 3;
1393     else if (IS_VALLEYVIEW(dev_priv))
1394         num_levels = 1;
1395     else if (IS_G4X(dev_priv))
1396         num_levels = 3;
1397     else
1398         num_levels = ilk_wm_max_level(dev_priv) + 1;
1399 
1400     drm_modeset_lock_all(dev);
1401 
1402     for (level = 0; level < num_levels; level++) {
1403         unsigned int latency = wm[level];
1404 
1405         /*
1406          * - WM1+ latency values in 0.5us units
1407          * - latencies are in us on gen9/vlv/chv
1408          */
1409         if (DISPLAY_VER(dev_priv) >= 9 ||
1410             IS_VALLEYVIEW(dev_priv) ||
1411             IS_CHERRYVIEW(dev_priv) ||
1412             IS_G4X(dev_priv))
1413             latency *= 10;
1414         else if (level > 0)
1415             latency *= 5;
1416 
1417         seq_printf(m, "WM%d %u (%u.%u usec)\n",
1418                level, wm[level], latency / 10, latency % 10);
1419     }
1420 
1421     drm_modeset_unlock_all(dev);
1422 }
1423 
1424 static int pri_wm_latency_show(struct seq_file *m, void *data)
1425 {
1426     struct drm_i915_private *dev_priv = m->private;
1427     const u16 *latencies;
1428 
1429     if (DISPLAY_VER(dev_priv) >= 9)
1430         latencies = dev_priv->wm.skl_latency;
1431     else
1432         latencies = dev_priv->wm.pri_latency;
1433 
1434     wm_latency_show(m, latencies);
1435 
1436     return 0;
1437 }
1438 
1439 static int spr_wm_latency_show(struct seq_file *m, void *data)
1440 {
1441     struct drm_i915_private *dev_priv = m->private;
1442     const u16 *latencies;
1443 
1444     if (DISPLAY_VER(dev_priv) >= 9)
1445         latencies = dev_priv->wm.skl_latency;
1446     else
1447         latencies = dev_priv->wm.spr_latency;
1448 
1449     wm_latency_show(m, latencies);
1450 
1451     return 0;
1452 }
1453 
1454 static int cur_wm_latency_show(struct seq_file *m, void *data)
1455 {
1456     struct drm_i915_private *dev_priv = m->private;
1457     const u16 *latencies;
1458 
1459     if (DISPLAY_VER(dev_priv) >= 9)
1460         latencies = dev_priv->wm.skl_latency;
1461     else
1462         latencies = dev_priv->wm.cur_latency;
1463 
1464     wm_latency_show(m, latencies);
1465 
1466     return 0;
1467 }
1468 
1469 static int pri_wm_latency_open(struct inode *inode, struct file *file)
1470 {
1471     struct drm_i915_private *dev_priv = inode->i_private;
1472 
1473     if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
1474         return -ENODEV;
1475 
1476     return single_open(file, pri_wm_latency_show, dev_priv);
1477 }
1478 
1479 static int spr_wm_latency_open(struct inode *inode, struct file *file)
1480 {
1481     struct drm_i915_private *dev_priv = inode->i_private;
1482 
1483     if (HAS_GMCH(dev_priv))
1484         return -ENODEV;
1485 
1486     return single_open(file, spr_wm_latency_show, dev_priv);
1487 }
1488 
1489 static int cur_wm_latency_open(struct inode *inode, struct file *file)
1490 {
1491     struct drm_i915_private *dev_priv = inode->i_private;
1492 
1493     if (HAS_GMCH(dev_priv))
1494         return -ENODEV;
1495 
1496     return single_open(file, cur_wm_latency_show, dev_priv);
1497 }
1498 
1499 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
1500                 size_t len, loff_t *offp, u16 wm[8])
1501 {
1502     struct seq_file *m = file->private_data;
1503     struct drm_i915_private *dev_priv = m->private;
1504     struct drm_device *dev = &dev_priv->drm;
1505     u16 new[8] = { 0 };
1506     int num_levels;
1507     int level;
1508     int ret;
1509     char tmp[32];
1510 
1511     if (IS_CHERRYVIEW(dev_priv))
1512         num_levels = 3;
1513     else if (IS_VALLEYVIEW(dev_priv))
1514         num_levels = 1;
1515     else if (IS_G4X(dev_priv))
1516         num_levels = 3;
1517     else
1518         num_levels = ilk_wm_max_level(dev_priv) + 1;
1519 
1520     if (len >= sizeof(tmp))
1521         return -EINVAL;
1522 
1523     if (copy_from_user(tmp, ubuf, len))
1524         return -EFAULT;
1525 
1526     tmp[len] = '\0';
1527 
1528     ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
1529              &new[0], &new[1], &new[2], &new[3],
1530              &new[4], &new[5], &new[6], &new[7]);
1531     if (ret != num_levels)
1532         return -EINVAL;
1533 
1534     drm_modeset_lock_all(dev);
1535 
1536     for (level = 0; level < num_levels; level++)
1537         wm[level] = new[level];
1538 
1539     drm_modeset_unlock_all(dev);
1540 
1541     return len;
1542 }
1543 
1544 
1545 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
1546                     size_t len, loff_t *offp)
1547 {
1548     struct seq_file *m = file->private_data;
1549     struct drm_i915_private *dev_priv = m->private;
1550     u16 *latencies;
1551 
1552     if (DISPLAY_VER(dev_priv) >= 9)
1553         latencies = dev_priv->wm.skl_latency;
1554     else
1555         latencies = dev_priv->wm.pri_latency;
1556 
1557     return wm_latency_write(file, ubuf, len, offp, latencies);
1558 }
1559 
1560 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
1561                     size_t len, loff_t *offp)
1562 {
1563     struct seq_file *m = file->private_data;
1564     struct drm_i915_private *dev_priv = m->private;
1565     u16 *latencies;
1566 
1567     if (DISPLAY_VER(dev_priv) >= 9)
1568         latencies = dev_priv->wm.skl_latency;
1569     else
1570         latencies = dev_priv->wm.spr_latency;
1571 
1572     return wm_latency_write(file, ubuf, len, offp, latencies);
1573 }
1574 
1575 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
1576                     size_t len, loff_t *offp)
1577 {
1578     struct seq_file *m = file->private_data;
1579     struct drm_i915_private *dev_priv = m->private;
1580     u16 *latencies;
1581 
1582     if (DISPLAY_VER(dev_priv) >= 9)
1583         latencies = dev_priv->wm.skl_latency;
1584     else
1585         latencies = dev_priv->wm.cur_latency;
1586 
1587     return wm_latency_write(file, ubuf, len, offp, latencies);
1588 }
1589 
1590 static const struct file_operations i915_pri_wm_latency_fops = {
1591     .owner = THIS_MODULE,
1592     .open = pri_wm_latency_open,
1593     .read = seq_read,
1594     .llseek = seq_lseek,
1595     .release = single_release,
1596     .write = pri_wm_latency_write
1597 };
1598 
1599 static const struct file_operations i915_spr_wm_latency_fops = {
1600     .owner = THIS_MODULE,
1601     .open = spr_wm_latency_open,
1602     .read = seq_read,
1603     .llseek = seq_lseek,
1604     .release = single_release,
1605     .write = spr_wm_latency_write
1606 };
1607 
1608 static const struct file_operations i915_cur_wm_latency_fops = {
1609     .owner = THIS_MODULE,
1610     .open = cur_wm_latency_open,
1611     .read = seq_read,
1612     .llseek = seq_lseek,
1613     .release = single_release,
1614     .write = cur_wm_latency_write
1615 };
1616 
1617 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
1618 {
1619     struct drm_i915_private *dev_priv = m->private;
1620     struct i915_hotplug *hotplug = &dev_priv->hotplug;
1621 
1622     /* Synchronize with everything first in case there's been an HPD
1623      * storm, but we haven't finished handling it in the kernel yet
1624      */
1625     intel_synchronize_irq(dev_priv);
1626     flush_work(&dev_priv->hotplug.dig_port_work);
1627     flush_delayed_work(&dev_priv->hotplug.hotplug_work);
1628 
1629     seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
1630     seq_printf(m, "Detected: %s\n",
1631            str_yes_no(delayed_work_pending(&hotplug->reenable_work)));
1632 
1633     return 0;
1634 }
1635 
1636 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
1637                     const char __user *ubuf, size_t len,
1638                     loff_t *offp)
1639 {
1640     struct seq_file *m = file->private_data;
1641     struct drm_i915_private *dev_priv = m->private;
1642     struct i915_hotplug *hotplug = &dev_priv->hotplug;
1643     unsigned int new_threshold;
1644     int i;
1645     char *newline;
1646     char tmp[16];
1647 
1648     if (len >= sizeof(tmp))
1649         return -EINVAL;
1650 
1651     if (copy_from_user(tmp, ubuf, len))
1652         return -EFAULT;
1653 
1654     tmp[len] = '\0';
1655 
1656     /* Strip newline, if any */
1657     newline = strchr(tmp, '\n');
1658     if (newline)
1659         *newline = '\0';
1660 
1661     if (strcmp(tmp, "reset") == 0)
1662         new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
1663     else if (kstrtouint(tmp, 10, &new_threshold) != 0)
1664         return -EINVAL;
1665 
1666     if (new_threshold > 0)
1667         drm_dbg_kms(&dev_priv->drm,
1668                 "Setting HPD storm detection threshold to %d\n",
1669                 new_threshold);
1670     else
1671         drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm detection\n");
1672 
1673     spin_lock_irq(&dev_priv->irq_lock);
1674     hotplug->hpd_storm_threshold = new_threshold;
1675     /* Reset the HPD storm stats so we don't accidentally trigger a storm */
1676     for_each_hpd_pin(i)
1677         hotplug->stats[i].count = 0;
1678     spin_unlock_irq(&dev_priv->irq_lock);
1679 
1680     /* Re-enable hpd immediately if we were in an irq storm */
1681     flush_delayed_work(&dev_priv->hotplug.reenable_work);
1682 
1683     return len;
1684 }
1685 
1686 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
1687 {
1688     return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
1689 }
1690 
1691 static const struct file_operations i915_hpd_storm_ctl_fops = {
1692     .owner = THIS_MODULE,
1693     .open = i915_hpd_storm_ctl_open,
1694     .read = seq_read,
1695     .llseek = seq_lseek,
1696     .release = single_release,
1697     .write = i915_hpd_storm_ctl_write
1698 };
1699 
1700 static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
1701 {
1702     struct drm_i915_private *dev_priv = m->private;
1703 
1704     seq_printf(m, "Enabled: %s\n",
1705            str_yes_no(dev_priv->hotplug.hpd_short_storm_enabled));
1706 
1707     return 0;
1708 }
1709 
1710 static int
1711 i915_hpd_short_storm_ctl_open(struct inode *inode, struct file *file)
1712 {
1713     return single_open(file, i915_hpd_short_storm_ctl_show,
1714                inode->i_private);
1715 }
1716 
1717 static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
1718                           const char __user *ubuf,
1719                           size_t len, loff_t *offp)
1720 {
1721     struct seq_file *m = file->private_data;
1722     struct drm_i915_private *dev_priv = m->private;
1723     struct i915_hotplug *hotplug = &dev_priv->hotplug;
1724     char *newline;
1725     char tmp[16];
1726     int i;
1727     bool new_state;
1728 
1729     if (len >= sizeof(tmp))
1730         return -EINVAL;
1731 
1732     if (copy_from_user(tmp, ubuf, len))
1733         return -EFAULT;
1734 
1735     tmp[len] = '\0';
1736 
1737     /* Strip newline, if any */
1738     newline = strchr(tmp, '\n');
1739     if (newline)
1740         *newline = '\0';
1741 
1742     /* Reset to the "default" state for this system */
1743     if (strcmp(tmp, "reset") == 0)
1744         new_state = !HAS_DP_MST(dev_priv);
1745     else if (kstrtobool(tmp, &new_state) != 0)
1746         return -EINVAL;
1747 
1748     drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n",
1749             new_state ? "En" : "Dis");
1750 
1751     spin_lock_irq(&dev_priv->irq_lock);
1752     hotplug->hpd_short_storm_enabled = new_state;
1753     /* Reset the HPD storm stats so we don't accidentally trigger a storm */
1754     for_each_hpd_pin(i)
1755         hotplug->stats[i].count = 0;
1756     spin_unlock_irq(&dev_priv->irq_lock);
1757 
1758     /* Re-enable hpd immediately if we were in an irq storm */
1759     flush_delayed_work(&dev_priv->hotplug.reenable_work);
1760 
1761     return len;
1762 }
1763 
1764 static const struct file_operations i915_hpd_short_storm_ctl_fops = {
1765     .owner = THIS_MODULE,
1766     .open = i915_hpd_short_storm_ctl_open,
1767     .read = seq_read,
1768     .llseek = seq_lseek,
1769     .release = single_release,
1770     .write = i915_hpd_short_storm_ctl_write,
1771 };
1772 
1773 static int i915_drrs_ctl_set(void *data, u64 val)
1774 {
1775     struct drm_i915_private *dev_priv = data;
1776     struct drm_device *dev = &dev_priv->drm;
1777     struct intel_crtc *crtc;
1778 
1779     for_each_intel_crtc(dev, crtc) {
1780         struct intel_crtc_state *crtc_state;
1781         struct drm_crtc_commit *commit;
1782         int ret;
1783 
1784         ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex);
1785         if (ret)
1786             return ret;
1787 
1788         crtc_state = to_intel_crtc_state(crtc->base.state);
1789 
1790         if (!crtc_state->hw.active ||
1791             !crtc_state->has_drrs)
1792             goto out;
1793 
1794         commit = crtc_state->uapi.commit;
1795         if (commit) {
1796             ret = wait_for_completion_interruptible(&commit->hw_done);
1797             if (ret)
1798                 goto out;
1799         }
1800 
1801         drm_dbg(&dev_priv->drm,
1802             "Manually %sactivating DRRS\n", val ? "" : "de");
1803 
1804         if (val)
1805             intel_drrs_activate(crtc_state);
1806         else
1807             intel_drrs_deactivate(crtc_state);
1808 
1809 out:
1810         drm_modeset_unlock(&crtc->base.mutex);
1811         if (ret)
1812             return ret;
1813     }
1814 
1815     return 0;
1816 }
1817 
1818 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
1819 
1820 static ssize_t
1821 i915_fifo_underrun_reset_write(struct file *filp,
1822                    const char __user *ubuf,
1823                    size_t cnt, loff_t *ppos)
1824 {
1825     struct drm_i915_private *dev_priv = filp->private_data;
1826     struct intel_crtc *crtc;
1827     struct drm_device *dev = &dev_priv->drm;
1828     int ret;
1829     bool reset;
1830 
1831     ret = kstrtobool_from_user(ubuf, cnt, &reset);
1832     if (ret)
1833         return ret;
1834 
1835     if (!reset)
1836         return cnt;
1837 
1838     for_each_intel_crtc(dev, crtc) {
1839         struct drm_crtc_commit *commit;
1840         struct intel_crtc_state *crtc_state;
1841 
1842         ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex);
1843         if (ret)
1844             return ret;
1845 
1846         crtc_state = to_intel_crtc_state(crtc->base.state);
1847         commit = crtc_state->uapi.commit;
1848         if (commit) {
1849             ret = wait_for_completion_interruptible(&commit->hw_done);
1850             if (!ret)
1851                 ret = wait_for_completion_interruptible(&commit->flip_done);
1852         }
1853 
1854         if (!ret && crtc_state->hw.active) {
1855             drm_dbg_kms(&dev_priv->drm,
1856                     "Re-arming FIFO underruns on pipe %c\n",
1857                     pipe_name(crtc->pipe));
1858 
1859             intel_crtc_arm_fifo_underrun(crtc, crtc_state);
1860         }
1861 
1862         drm_modeset_unlock(&crtc->base.mutex);
1863 
1864         if (ret)
1865             return ret;
1866     }
1867 
1868     intel_fbc_reset_underrun(dev_priv);
1869 
1870     return cnt;
1871 }
1872 
1873 static const struct file_operations i915_fifo_underrun_reset_ops = {
1874     .owner = THIS_MODULE,
1875     .open = simple_open,
1876     .write = i915_fifo_underrun_reset_write,
1877     .llseek = default_llseek,
1878 };
1879 
1880 static const struct drm_info_list intel_display_debugfs_list[] = {
1881     {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
1882     {"i915_ips_status", i915_ips_status, 0},
1883     {"i915_sr_status", i915_sr_status, 0},
1884     {"i915_opregion", i915_opregion, 0},
1885     {"i915_vbt", i915_vbt, 0},
1886     {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1887     {"i915_edp_psr_status", i915_edp_psr_status, 0},
1888     {"i915_power_domain_info", i915_power_domain_info, 0},
1889     {"i915_display_info", i915_display_info, 0},
1890     {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
1891     {"i915_dp_mst_info", i915_dp_mst_info, 0},
1892     {"i915_ddb_info", i915_ddb_info, 0},
1893     {"i915_drrs_status", i915_drrs_status, 0},
1894     {"i915_lpsp_status", i915_lpsp_status, 0},
1895 };
1896 
1897 static const struct {
1898     const char *name;
1899     const struct file_operations *fops;
1900 } intel_display_debugfs_files[] = {
1901     {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops},
1902     {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
1903     {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
1904     {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
1905     {"i915_dp_test_data", &i915_displayport_test_data_fops},
1906     {"i915_dp_test_type", &i915_displayport_test_type_fops},
1907     {"i915_dp_test_active", &i915_displayport_test_active_fops},
1908     {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
1909     {"i915_hpd_short_storm_ctl", &i915_hpd_short_storm_ctl_fops},
1910     {"i915_ipc_status", &i915_ipc_status_fops},
1911     {"i915_drrs_ctl", &i915_drrs_ctl_fops},
1912     {"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
1913 };
1914 
1915 void intel_display_debugfs_register(struct drm_i915_private *i915)
1916 {
1917     struct drm_minor *minor = i915->drm.primary;
1918     int i;
1919 
1920     for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) {
1921         debugfs_create_file(intel_display_debugfs_files[i].name,
1922                     S_IRUGO | S_IWUSR,
1923                     minor->debugfs_root,
1924                     to_i915(minor->dev),
1925                     intel_display_debugfs_files[i].fops);
1926     }
1927 
1928     drm_debugfs_create_files(intel_display_debugfs_list,
1929                  ARRAY_SIZE(intel_display_debugfs_list),
1930                  minor->debugfs_root, minor);
1931 
1932     intel_dmc_debugfs_register(i915);
1933     intel_fbc_debugfs_register(i915);
1934 }
1935 
1936 static int i915_panel_show(struct seq_file *m, void *data)
1937 {
1938     struct drm_connector *connector = m->private;
1939     struct intel_dp *intel_dp =
1940         intel_attached_dp(to_intel_connector(connector));
1941 
1942     if (connector->status != connector_status_connected)
1943         return -ENODEV;
1944 
1945     seq_printf(m, "Panel power up delay: %d\n",
1946            intel_dp->pps.panel_power_up_delay);
1947     seq_printf(m, "Panel power down delay: %d\n",
1948            intel_dp->pps.panel_power_down_delay);
1949     seq_printf(m, "Backlight on delay: %d\n",
1950            intel_dp->pps.backlight_on_delay);
1951     seq_printf(m, "Backlight off delay: %d\n",
1952            intel_dp->pps.backlight_off_delay);
1953 
1954     return 0;
1955 }
1956 DEFINE_SHOW_ATTRIBUTE(i915_panel);
1957 
1958 static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
1959 {
1960     struct drm_connector *connector = m->private;
1961     struct drm_i915_private *i915 = to_i915(connector->dev);
1962     struct intel_connector *intel_connector = to_intel_connector(connector);
1963     int ret;
1964 
1965     ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
1966     if (ret)
1967         return ret;
1968 
1969     if (!connector->encoder || connector->status != connector_status_connected) {
1970         ret = -ENODEV;
1971         goto out;
1972     }
1973 
1974     seq_printf(m, "%s:%d HDCP version: ", connector->name,
1975            connector->base.id);
1976     intel_hdcp_info(m, intel_connector);
1977 
1978 out:
1979     drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
1980 
1981     return ret;
1982 }
1983 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
1984 
1985 static int i915_psr_status_show(struct seq_file *m, void *data)
1986 {
1987     struct drm_connector *connector = m->private;
1988     struct intel_dp *intel_dp =
1989         intel_attached_dp(to_intel_connector(connector));
1990 
1991     return intel_psr_status(m, intel_dp);
1992 }
1993 DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
1994 
1995 static int i915_lpsp_capability_show(struct seq_file *m, void *data)
1996 {
1997     struct drm_connector *connector = m->private;
1998     struct drm_i915_private *i915 = to_i915(connector->dev);
1999     struct intel_encoder *encoder;
2000     bool lpsp_capable = false;
2001 
2002     encoder = intel_attached_encoder(to_intel_connector(connector));
2003     if (!encoder)
2004         return -ENODEV;
2005 
2006     if (connector->status != connector_status_connected)
2007         return -ENODEV;
2008 
2009     if (DISPLAY_VER(i915) >= 13)
2010         lpsp_capable = encoder->port <= PORT_B;
2011     else if (DISPLAY_VER(i915) >= 12)
2012         /*
2013          * Actually TGL can drive LPSP on port till DDI_C
2014          * but there is no physical connected DDI_C on TGL sku's,
2015          * even driver is not initilizing DDI_C port for gen12.
2016          */
2017         lpsp_capable = encoder->port <= PORT_B;
2018     else if (DISPLAY_VER(i915) == 11)
2019         lpsp_capable = (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2020                 connector->connector_type == DRM_MODE_CONNECTOR_eDP);
2021     else if (IS_DISPLAY_VER(i915, 9, 10))
2022         lpsp_capable = (encoder->port == PORT_A &&
2023                 (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2024                  connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
2025                  connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort));
2026     else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
2027         lpsp_capable = connector->connector_type == DRM_MODE_CONNECTOR_eDP;
2028 
2029     seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable");
2030 
2031     return 0;
2032 }
2033 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
2034 
2035 static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
2036 {
2037     struct drm_connector *connector = m->private;
2038     struct drm_device *dev = connector->dev;
2039     struct drm_crtc *crtc;
2040     struct intel_dp *intel_dp;
2041     struct drm_modeset_acquire_ctx ctx;
2042     struct intel_crtc_state *crtc_state = NULL;
2043     int ret = 0;
2044     bool try_again = false;
2045 
2046     drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2047 
2048     do {
2049         try_again = false;
2050         ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
2051                        &ctx);
2052         if (ret) {
2053             if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
2054                 try_again = true;
2055                 continue;
2056             }
2057             break;
2058         }
2059         crtc = connector->state->crtc;
2060         if (connector->status != connector_status_connected || !crtc) {
2061             ret = -ENODEV;
2062             break;
2063         }
2064         ret = drm_modeset_lock(&crtc->mutex, &ctx);
2065         if (ret == -EDEADLK) {
2066             ret = drm_modeset_backoff(&ctx);
2067             if (!ret) {
2068                 try_again = true;
2069                 continue;
2070             }
2071             break;
2072         } else if (ret) {
2073             break;
2074         }
2075         intel_dp = intel_attached_dp(to_intel_connector(connector));
2076         crtc_state = to_intel_crtc_state(crtc->state);
2077         seq_printf(m, "DSC_Enabled: %s\n",
2078                str_yes_no(crtc_state->dsc.compression_enable));
2079         seq_printf(m, "DSC_Sink_Support: %s\n",
2080                str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
2081         seq_printf(m, "Force_DSC_Enable: %s\n",
2082                str_yes_no(intel_dp->force_dsc_en));
2083         if (!intel_dp_is_edp(intel_dp))
2084             seq_printf(m, "FEC_Sink_Support: %s\n",
2085                    str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
2086     } while (try_again);
2087 
2088     drm_modeset_drop_locks(&ctx);
2089     drm_modeset_acquire_fini(&ctx);
2090 
2091     return ret;
2092 }
2093 
2094 static ssize_t i915_dsc_fec_support_write(struct file *file,
2095                       const char __user *ubuf,
2096                       size_t len, loff_t *offp)
2097 {
2098     bool dsc_enable = false;
2099     int ret;
2100     struct drm_connector *connector =
2101         ((struct seq_file *)file->private_data)->private;
2102     struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
2103     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2104     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2105 
2106     if (len == 0)
2107         return 0;
2108 
2109     drm_dbg(&i915->drm,
2110         "Copied %zu bytes from user to force DSC\n", len);
2111 
2112     ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
2113     if (ret < 0)
2114         return ret;
2115 
2116     drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
2117         (dsc_enable) ? "true" : "false");
2118     intel_dp->force_dsc_en = dsc_enable;
2119 
2120     *offp += len;
2121     return len;
2122 }
2123 
2124 static int i915_dsc_fec_support_open(struct inode *inode,
2125                      struct file *file)
2126 {
2127     return single_open(file, i915_dsc_fec_support_show,
2128                inode->i_private);
2129 }
2130 
2131 static const struct file_operations i915_dsc_fec_support_fops = {
2132     .owner = THIS_MODULE,
2133     .open = i915_dsc_fec_support_open,
2134     .read = seq_read,
2135     .llseek = seq_lseek,
2136     .release = single_release,
2137     .write = i915_dsc_fec_support_write
2138 };
2139 
2140 static int i915_dsc_bpp_show(struct seq_file *m, void *data)
2141 {
2142     struct drm_connector *connector = m->private;
2143     struct drm_device *dev = connector->dev;
2144     struct drm_crtc *crtc;
2145     struct intel_crtc_state *crtc_state;
2146     struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
2147     int ret;
2148 
2149     if (!encoder)
2150         return -ENODEV;
2151 
2152     ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
2153     if (ret)
2154         return ret;
2155 
2156     crtc = connector->state->crtc;
2157     if (connector->status != connector_status_connected || !crtc) {
2158         ret = -ENODEV;
2159         goto out;
2160     }
2161 
2162     crtc_state = to_intel_crtc_state(crtc->state);
2163     seq_printf(m, "Compressed_BPP: %d\n", crtc_state->dsc.compressed_bpp);
2164 
2165 out:    drm_modeset_unlock(&dev->mode_config.connection_mutex);
2166 
2167     return ret;
2168 }
2169 
2170 static ssize_t i915_dsc_bpp_write(struct file *file,
2171                   const char __user *ubuf,
2172                   size_t len, loff_t *offp)
2173 {
2174     struct drm_connector *connector =
2175         ((struct seq_file *)file->private_data)->private;
2176     struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
2177     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2178     int dsc_bpp = 0;
2179     int ret;
2180 
2181     ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpp);
2182     if (ret < 0)
2183         return ret;
2184 
2185     intel_dp->force_dsc_bpp = dsc_bpp;
2186     *offp += len;
2187 
2188     return len;
2189 }
2190 
2191 static int i915_dsc_bpp_open(struct inode *inode,
2192                  struct file *file)
2193 {
2194     return single_open(file, i915_dsc_bpp_show,
2195                inode->i_private);
2196 }
2197 
2198 static const struct file_operations i915_dsc_bpp_fops = {
2199     .owner = THIS_MODULE,
2200     .open = i915_dsc_bpp_open,
2201     .read = seq_read,
2202     .llseek = seq_lseek,
2203     .release = single_release,
2204     .write = i915_dsc_bpp_write
2205 };
2206 
2207 /*
2208  * Returns the Current CRTC's bpc.
2209  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
2210  */
2211 static int i915_current_bpc_show(struct seq_file *m, void *data)
2212 {
2213     struct intel_crtc *crtc = to_intel_crtc(m->private);
2214     struct intel_crtc_state *crtc_state;
2215     int ret;
2216 
2217     ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex);
2218     if (ret)
2219         return ret;
2220 
2221     crtc_state = to_intel_crtc_state(crtc->base.state);
2222     seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3);
2223 
2224     drm_modeset_unlock(&crtc->base.mutex);
2225 
2226     return ret;
2227 }
2228 DEFINE_SHOW_ATTRIBUTE(i915_current_bpc);
2229 
2230 /**
2231  * intel_connector_debugfs_add - add i915 specific connector debugfs files
2232  * @connector: pointer to a registered drm_connector
2233  *
2234  * Cleanup will be done by drm_connector_unregister() through a call to
2235  * drm_debugfs_connector_remove().
2236  */
2237 void intel_connector_debugfs_add(struct intel_connector *intel_connector)
2238 {
2239     struct drm_connector *connector = &intel_connector->base;
2240     struct dentry *root = connector->debugfs_entry;
2241     struct drm_i915_private *dev_priv = to_i915(connector->dev);
2242 
2243     /* The connector must have been registered beforehands. */
2244     if (!root)
2245         return;
2246 
2247     if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
2248         debugfs_create_file("i915_panel_timings", S_IRUGO, root,
2249                     connector, &i915_panel_fops);
2250         debugfs_create_file("i915_psr_sink_status", S_IRUGO, root,
2251                     connector, &i915_psr_sink_status_fops);
2252     }
2253 
2254     if (HAS_PSR(dev_priv) &&
2255         connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
2256         debugfs_create_file("i915_psr_status", 0444, root,
2257                     connector, &i915_psr_status_fops);
2258     }
2259 
2260     if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2261         connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
2262         connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
2263         debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root,
2264                     connector, &i915_hdcp_sink_capability_fops);
2265     }
2266 
2267     if (DISPLAY_VER(dev_priv) >= 11 &&
2268         ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
2269         !to_intel_connector(connector)->mst_port) ||
2270         connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
2271         debugfs_create_file("i915_dsc_fec_support", 0644, root,
2272                     connector, &i915_dsc_fec_support_fops);
2273 
2274         debugfs_create_file("i915_dsc_bpp", 0644, root,
2275                     connector, &i915_dsc_bpp_fops);
2276     }
2277 
2278     if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
2279         connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
2280         connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2281         connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
2282         connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
2283         debugfs_create_file("i915_lpsp_capability", 0444, root,
2284                     connector, &i915_lpsp_capability_fops);
2285 }
2286 
2287 /**
2288  * intel_crtc_debugfs_add - add i915 specific crtc debugfs files
2289  * @crtc: pointer to a drm_crtc
2290  *
2291  * Failure to add debugfs entries should generally be ignored.
2292  */
2293 void intel_crtc_debugfs_add(struct drm_crtc *crtc)
2294 {
2295     if (!crtc->debugfs_entry)
2296         return;
2297 
2298     crtc_updates_add(crtc);
2299     intel_fbc_crtc_debugfs_add(to_intel_crtc(crtc));
2300 
2301     debugfs_create_file("i915_current_bpc", 0444, crtc->debugfs_entry, crtc,
2302                 &i915_current_bpc_fops);
2303 }
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