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0001 /*
0002  * Copyright © 2006-2019 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  *
0023  */
0024 
0025 #ifndef _INTEL_DISPLAY_H_
0026 #define _INTEL_DISPLAY_H_
0027 
0028 #include <drm/drm_util.h>
0029 
0030 #include "i915_reg_defs.h"
0031 
0032 enum drm_scaling_filter;
0033 struct dpll;
0034 struct drm_connector;
0035 struct drm_device;
0036 struct drm_display_mode;
0037 struct drm_encoder;
0038 struct drm_file;
0039 struct drm_format_info;
0040 struct drm_framebuffer;
0041 struct drm_i915_gem_object;
0042 struct drm_i915_private;
0043 struct drm_mode_fb_cmd2;
0044 struct drm_modeset_acquire_ctx;
0045 struct drm_plane;
0046 struct drm_plane_state;
0047 struct i915_address_space;
0048 struct i915_ggtt_view;
0049 struct intel_atomic_state;
0050 struct intel_crtc;
0051 struct intel_crtc_state;
0052 struct intel_digital_port;
0053 struct intel_dp;
0054 struct intel_encoder;
0055 struct intel_initial_plane_config;
0056 struct intel_load_detect_pipe;
0057 struct intel_plane;
0058 struct intel_plane_state;
0059 struct intel_power_domain_mask;
0060 struct intel_remapped_info;
0061 struct intel_rotation_info;
0062 struct pci_dev;
0063 
0064 enum i915_gpio {
0065     GPIOA,
0066     GPIOB,
0067     GPIOC,
0068     GPIOD,
0069     GPIOE,
0070     GPIOF,
0071     GPIOG,
0072     GPIOH,
0073     __GPIOI_UNUSED,
0074     GPIOJ,
0075     GPIOK,
0076     GPIOL,
0077     GPIOM,
0078     GPION,
0079     GPIOO,
0080 };
0081 
0082 /*
0083  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
0084  * rest have consecutive values and match the enum values of transcoders
0085  * with a 1:1 transcoder -> pipe mapping.
0086  */
0087 enum pipe {
0088     INVALID_PIPE = -1,
0089 
0090     PIPE_A = 0,
0091     PIPE_B,
0092     PIPE_C,
0093     PIPE_D,
0094     _PIPE_EDP,
0095 
0096     I915_MAX_PIPES = _PIPE_EDP
0097 };
0098 
0099 #define pipe_name(p) ((p) + 'A')
0100 
0101 enum transcoder {
0102     INVALID_TRANSCODER = -1,
0103     /*
0104      * The following transcoders have a 1:1 transcoder -> pipe mapping,
0105      * keep their values fixed: the code assumes that TRANSCODER_A=0, the
0106      * rest have consecutive values and match the enum values of the pipes
0107      * they map to.
0108      */
0109     TRANSCODER_A = PIPE_A,
0110     TRANSCODER_B = PIPE_B,
0111     TRANSCODER_C = PIPE_C,
0112     TRANSCODER_D = PIPE_D,
0113 
0114     /*
0115      * The following transcoders can map to any pipe, their enum value
0116      * doesn't need to stay fixed.
0117      */
0118     TRANSCODER_EDP,
0119     TRANSCODER_DSI_0,
0120     TRANSCODER_DSI_1,
0121     TRANSCODER_DSI_A = TRANSCODER_DSI_0,    /* legacy DSI */
0122     TRANSCODER_DSI_C = TRANSCODER_DSI_1,    /* legacy DSI */
0123 
0124     I915_MAX_TRANSCODERS
0125 };
0126 
0127 static inline const char *transcoder_name(enum transcoder transcoder)
0128 {
0129     switch (transcoder) {
0130     case TRANSCODER_A:
0131         return "A";
0132     case TRANSCODER_B:
0133         return "B";
0134     case TRANSCODER_C:
0135         return "C";
0136     case TRANSCODER_D:
0137         return "D";
0138     case TRANSCODER_EDP:
0139         return "EDP";
0140     case TRANSCODER_DSI_A:
0141         return "DSI A";
0142     case TRANSCODER_DSI_C:
0143         return "DSI C";
0144     default:
0145         return "<invalid>";
0146     }
0147 }
0148 
0149 static inline bool transcoder_is_dsi(enum transcoder transcoder)
0150 {
0151     return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
0152 }
0153 
0154 /*
0155  * Global legacy plane identifier. Valid only for primary/sprite
0156  * planes on pre-g4x, and only for primary planes on g4x-bdw.
0157  */
0158 enum i9xx_plane_id {
0159     PLANE_A,
0160     PLANE_B,
0161     PLANE_C,
0162 };
0163 
0164 #define plane_name(p) ((p) + 'A')
0165 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
0166 
0167 /*
0168  * Per-pipe plane identifier.
0169  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
0170  * number of planes per CRTC.  Not all platforms really have this many planes,
0171  * which means some arrays of size I915_MAX_PLANES may have unused entries
0172  * between the topmost sprite plane and the cursor plane.
0173  *
0174  * This is expected to be passed to various register macros
0175  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
0176  */
0177 enum plane_id {
0178     PLANE_PRIMARY,
0179     PLANE_SPRITE0,
0180     PLANE_SPRITE1,
0181     PLANE_SPRITE2,
0182     PLANE_SPRITE3,
0183     PLANE_SPRITE4,
0184     PLANE_SPRITE5,
0185     PLANE_CURSOR,
0186 
0187     I915_MAX_PLANES,
0188 };
0189 
0190 #define for_each_plane_id_on_crtc(__crtc, __p) \
0191     for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
0192         for_each_if((__crtc)->plane_ids_mask & BIT(__p))
0193 
0194 #define for_each_dbuf_slice(__dev_priv, __slice) \
0195     for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
0196         for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
0197 
0198 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
0199     for_each_dbuf_slice((__dev_priv), (__slice)) \
0200         for_each_if((__mask) & BIT(__slice))
0201 
0202 enum port {
0203     PORT_NONE = -1,
0204 
0205     PORT_A = 0,
0206     PORT_B,
0207     PORT_C,
0208     PORT_D,
0209     PORT_E,
0210     PORT_F,
0211     PORT_G,
0212     PORT_H,
0213     PORT_I,
0214 
0215     /* tgl+ */
0216     PORT_TC1 = PORT_D,
0217     PORT_TC2,
0218     PORT_TC3,
0219     PORT_TC4,
0220     PORT_TC5,
0221     PORT_TC6,
0222 
0223     /* XE_LPD repositions D/E offsets and bitfields */
0224     PORT_D_XELPD = PORT_TC5,
0225     PORT_E_XELPD,
0226 
0227     I915_MAX_PORTS
0228 };
0229 
0230 #define port_name(p) ((p) + 'A')
0231 
0232 /*
0233  * Ports identifier referenced from other drivers.
0234  * Expected to remain stable over time
0235  */
0236 static inline const char *port_identifier(enum port port)
0237 {
0238     switch (port) {
0239     case PORT_A:
0240         return "Port A";
0241     case PORT_B:
0242         return "Port B";
0243     case PORT_C:
0244         return "Port C";
0245     case PORT_D:
0246         return "Port D";
0247     case PORT_E:
0248         return "Port E";
0249     case PORT_F:
0250         return "Port F";
0251     case PORT_G:
0252         return "Port G";
0253     case PORT_H:
0254         return "Port H";
0255     case PORT_I:
0256         return "Port I";
0257     default:
0258         return "<invalid>";
0259     }
0260 }
0261 
0262 enum tc_port {
0263     TC_PORT_NONE = -1,
0264 
0265     TC_PORT_1 = 0,
0266     TC_PORT_2,
0267     TC_PORT_3,
0268     TC_PORT_4,
0269     TC_PORT_5,
0270     TC_PORT_6,
0271 
0272     I915_MAX_TC_PORTS
0273 };
0274 
0275 enum tc_port_mode {
0276     TC_PORT_DISCONNECTED,
0277     TC_PORT_TBT_ALT,
0278     TC_PORT_DP_ALT,
0279     TC_PORT_LEGACY,
0280 };
0281 
0282 enum dpio_channel {
0283     DPIO_CH0,
0284     DPIO_CH1
0285 };
0286 
0287 enum dpio_phy {
0288     DPIO_PHY0,
0289     DPIO_PHY1,
0290     DPIO_PHY2,
0291 };
0292 
0293 enum aux_ch {
0294     AUX_CH_A,
0295     AUX_CH_B,
0296     AUX_CH_C,
0297     AUX_CH_D,
0298     AUX_CH_E, /* ICL+ */
0299     AUX_CH_F,
0300     AUX_CH_G,
0301     AUX_CH_H,
0302     AUX_CH_I,
0303 
0304     /* tgl+ */
0305     AUX_CH_USBC1 = AUX_CH_D,
0306     AUX_CH_USBC2,
0307     AUX_CH_USBC3,
0308     AUX_CH_USBC4,
0309     AUX_CH_USBC5,
0310     AUX_CH_USBC6,
0311 
0312     /* XE_LPD repositions D/E offsets and bitfields */
0313     AUX_CH_D_XELPD = AUX_CH_USBC5,
0314     AUX_CH_E_XELPD,
0315 };
0316 
0317 #define aux_ch_name(a) ((a) + 'A')
0318 
0319 /* Used by dp and fdi links */
0320 struct intel_link_m_n {
0321     u32 tu;
0322     u32 data_m;
0323     u32 data_n;
0324     u32 link_m;
0325     u32 link_n;
0326 };
0327 
0328 enum phy {
0329     PHY_NONE = -1,
0330 
0331     PHY_A = 0,
0332     PHY_B,
0333     PHY_C,
0334     PHY_D,
0335     PHY_E,
0336     PHY_F,
0337     PHY_G,
0338     PHY_H,
0339     PHY_I,
0340 
0341     I915_MAX_PHYS
0342 };
0343 
0344 #define phy_name(a) ((a) + 'A')
0345 
0346 enum phy_fia {
0347     FIA1,
0348     FIA2,
0349     FIA3,
0350 };
0351 
0352 enum hpd_pin {
0353     HPD_NONE = 0,
0354     HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
0355     HPD_CRT,
0356     HPD_SDVO_B,
0357     HPD_SDVO_C,
0358     HPD_PORT_A,
0359     HPD_PORT_B,
0360     HPD_PORT_C,
0361     HPD_PORT_D,
0362     HPD_PORT_E,
0363     HPD_PORT_TC1,
0364     HPD_PORT_TC2,
0365     HPD_PORT_TC3,
0366     HPD_PORT_TC4,
0367     HPD_PORT_TC5,
0368     HPD_PORT_TC6,
0369 
0370     HPD_NUM_PINS
0371 };
0372 
0373 #define for_each_hpd_pin(__pin) \
0374     for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
0375 
0376 #define for_each_pipe(__dev_priv, __p) \
0377     for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
0378         for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p))
0379 
0380 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
0381     for_each_pipe(__dev_priv, __p) \
0382         for_each_if((__mask) & BIT(__p))
0383 
0384 #define for_each_cpu_transcoder(__dev_priv, __t) \
0385     for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
0386         for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))
0387 
0388 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
0389     for_each_cpu_transcoder(__dev_priv, __t) \
0390         for_each_if ((__mask) & BIT(__t))
0391 
0392 #define for_each_sprite(__dev_priv, __p, __s)               \
0393     for ((__s) = 0;                         \
0394          (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];  \
0395          (__s)++)
0396 
0397 #define for_each_port(__port) \
0398     for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
0399 
0400 #define for_each_port_masked(__port, __ports_mask)          \
0401     for_each_port(__port)                       \
0402         for_each_if((__ports_mask) & BIT(__port))
0403 
0404 #define for_each_phy_masked(__phy, __phys_mask) \
0405     for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)   \
0406         for_each_if((__phys_mask) & BIT(__phy))
0407 
0408 #define for_each_crtc(dev, crtc) \
0409     list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
0410 
0411 #define for_each_intel_plane(dev, intel_plane) \
0412     list_for_each_entry(intel_plane,            \
0413                 &(dev)->mode_config.plane_list, \
0414                 base.head)
0415 
0416 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)     \
0417     list_for_each_entry(intel_plane,                \
0418                 &(dev)->mode_config.plane_list,     \
0419                 base.head)                  \
0420         for_each_if((plane_mask) &              \
0421                 drm_plane_mask(&intel_plane->base))
0422 
0423 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)  \
0424     list_for_each_entry(intel_plane,                \
0425                 &(dev)->mode_config.plane_list,     \
0426                 base.head)                  \
0427         for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
0428 
0429 #define for_each_intel_crtc(dev, intel_crtc)                \
0430     list_for_each_entry(intel_crtc,                 \
0431                 &(dev)->mode_config.crtc_list,      \
0432                 base.head)
0433 
0434 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask)    \
0435     list_for_each_entry(intel_crtc,                 \
0436                 &(dev)->mode_config.crtc_list,      \
0437                 base.head)                  \
0438         for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
0439 
0440 #define for_each_intel_encoder(dev, intel_encoder)      \
0441     list_for_each_entry(intel_encoder,          \
0442                 &(dev)->mode_config.encoder_list,   \
0443                 base.head)
0444 
0445 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask)   \
0446     list_for_each_entry(intel_encoder,              \
0447                 &(dev)->mode_config.encoder_list,       \
0448                 base.head)                  \
0449         for_each_if((encoder_mask) &                \
0450                 drm_encoder_mask(&intel_encoder->base))
0451 
0452 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
0453     list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
0454         for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
0455                 intel_encoder_can_psr(intel_encoder))
0456 
0457 #define for_each_intel_dp(dev, intel_encoder)           \
0458     for_each_intel_encoder(dev, intel_encoder)      \
0459         for_each_if(intel_encoder_is_dp(intel_encoder))
0460 
0461 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
0462     for_each_intel_encoder((dev), (intel_encoder)) \
0463         for_each_if(intel_encoder_can_psr(intel_encoder))
0464 
0465 #define for_each_intel_connector_iter(intel_connector, iter) \
0466     while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
0467 
0468 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
0469     list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
0470         for_each_if((intel_encoder)->base.crtc == (__crtc))
0471 
0472 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
0473     list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
0474         for_each_if((intel_connector)->base.encoder == (__encoder))
0475 
0476 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
0477     for ((__i) = 0; \
0478          (__i) < (__state)->base.dev->mode_config.num_total_plane && \
0479              ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
0480               (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
0481          (__i)++) \
0482         for_each_if(plane)
0483 
0484 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
0485     for ((__i) = 0; \
0486          (__i) < (__state)->base.dev->mode_config.num_total_plane && \
0487              ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
0488               (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
0489          (__i)++) \
0490         for_each_if(plane)
0491 
0492 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
0493     for ((__i) = 0; \
0494          (__i) < (__state)->base.dev->mode_config.num_crtc && \
0495              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
0496               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
0497          (__i)++) \
0498         for_each_if(crtc)
0499 
0500 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
0501     for ((__i) = 0; \
0502          (__i) < (__state)->base.dev->mode_config.num_total_plane && \
0503              ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
0504               (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
0505               (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
0506          (__i)++) \
0507         for_each_if(plane)
0508 
0509 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
0510     for ((__i) = 0; \
0511          (__i) < (__state)->base.dev->mode_config.num_crtc && \
0512              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
0513               (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
0514               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
0515          (__i)++) \
0516         for_each_if(crtc)
0517 
0518 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
0519     for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
0520          (__i) >= 0  && \
0521          ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
0522           (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
0523           (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
0524          (__i)--) \
0525         for_each_if(crtc)
0526 
0527 #define intel_atomic_crtc_state_for_each_plane_state( \
0528           plane, plane_state, \
0529           crtc_state) \
0530     for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
0531                 ((crtc_state)->uapi.plane_mask)) \
0532         for_each_if ((plane_state = \
0533                   to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
0534 
0535 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
0536     for ((__i) = 0; \
0537          (__i) < (__state)->base.num_connector; \
0538          (__i)++) \
0539         for_each_if ((__state)->base.connectors[__i].ptr && \
0540                  ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
0541                  (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
0542 
0543 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
0544                      struct intel_crtc *crtc);
0545 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
0546                u8 active_pipes);
0547 void intel_link_compute_m_n(u16 bpp, int nlanes,
0548                 int pixel_clock, int link_clock,
0549                 struct intel_link_m_n *m_n,
0550                 bool constant_n, bool fec_enable);
0551 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
0552                   u32 pixel_format, u64 modifier);
0553 enum drm_mode_status
0554 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
0555                 const struct drm_display_mode *mode,
0556                 bool bigjoiner);
0557 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
0558 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
0559 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
0560 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
0561 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
0562 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
0563 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
0564 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
0565                    const struct intel_crtc_state *pipe_config,
0566                    bool fastset);
0567 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
0568 
0569 void intel_plane_destroy(struct drm_plane *plane);
0570 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
0571 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
0572 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
0573 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
0574 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
0575 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
0576 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
0577 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
0578               const char *name, u32 reg, int ref_freq);
0579 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
0580                const char *name, u32 reg);
0581 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
0582 unsigned int intel_fb_xy_to_linear(int x, int y,
0583                    const struct intel_plane_state *state,
0584                    int plane);
0585 void intel_add_fb_offsets(int *x, int *y,
0586               const struct intel_plane_state *state, int plane);
0587 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
0588 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
0589 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
0590 int intel_display_suspend(struct drm_device *dev);
0591 void intel_encoder_destroy(struct drm_encoder *encoder);
0592 struct drm_display_mode *
0593 intel_encoder_current_mode(struct intel_encoder *encoder);
0594 void intel_encoder_get_config(struct intel_encoder *encoder,
0595                   struct intel_crtc_state *crtc_state);
0596 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
0597 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
0598 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
0599 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
0600                   enum port port);
0601 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
0602                       struct drm_file *file_priv);
0603 
0604 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
0605 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
0606              struct intel_digital_port *dig_port,
0607              unsigned int expected_mask);
0608 int intel_get_load_detect_pipe(struct drm_connector *connector,
0609                    struct intel_load_detect_pipe *old,
0610                    struct drm_modeset_acquire_ctx *ctx);
0611 void intel_release_load_detect_pipe(struct drm_connector *connector,
0612                     struct intel_load_detect_pipe *old,
0613                     struct drm_modeset_acquire_ctx *ctx);
0614 struct drm_framebuffer *
0615 intel_framebuffer_create(struct drm_i915_gem_object *obj,
0616              struct drm_mode_fb_cmd2 *mode_cmd);
0617 
0618 bool intel_fuzzy_clock_check(int clock1, int clock2);
0619 
0620 void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
0621 void intel_display_finish_reset(struct drm_i915_private *dev_priv);
0622 void intel_zero_m_n(struct intel_link_m_n *m_n);
0623 void intel_set_m_n(struct drm_i915_private *i915,
0624            const struct intel_link_m_n *m_n,
0625            i915_reg_t data_m_reg, i915_reg_t data_n_reg,
0626            i915_reg_t link_m_reg, i915_reg_t link_n_reg);
0627 void intel_get_m_n(struct drm_i915_private *i915,
0628            struct intel_link_m_n *m_n,
0629            i915_reg_t data_m_reg, i915_reg_t data_n_reg,
0630            i915_reg_t link_m_reg, i915_reg_t link_n_reg);
0631 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
0632                     enum transcoder transcoder);
0633 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
0634                     enum transcoder cpu_transcoder,
0635                     const struct intel_link_m_n *m_n);
0636 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
0637                     enum transcoder cpu_transcoder,
0638                     const struct intel_link_m_n *m_n);
0639 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
0640                     enum transcoder cpu_transcoder,
0641                     struct intel_link_m_n *m_n);
0642 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
0643                     enum transcoder cpu_transcoder,
0644                     struct intel_link_m_n *m_n);
0645 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
0646              struct intel_crtc_state *pipe_config);
0647 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
0648 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
0649 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
0650 enum intel_display_power_domain
0651 intel_aux_power_domain(struct intel_digital_port *dig_port);
0652 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
0653                   struct intel_crtc_state *crtc_state);
0654 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
0655 
0656 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
0657 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
0658 
0659 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
0660 
0661 struct intel_encoder *
0662 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
0663                const struct intel_crtc_state *crtc_state);
0664 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
0665                   struct intel_plane *plane);
0666 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
0667                  struct intel_plane_state *plane_state,
0668                  bool visible);
0669 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
0670 
0671 void intel_display_driver_register(struct drm_i915_private *i915);
0672 void intel_display_driver_unregister(struct drm_i915_private *i915);
0673 
0674 void intel_update_watermarks(struct drm_i915_private *i915);
0675 
0676 /* modesetting */
0677 bool intel_modeset_probe_defer(struct pci_dev *pdev);
0678 void intel_modeset_init_hw(struct drm_i915_private *i915);
0679 int intel_modeset_init_noirq(struct drm_i915_private *i915);
0680 int intel_modeset_init_nogem(struct drm_i915_private *i915);
0681 int intel_modeset_init(struct drm_i915_private *i915);
0682 void intel_modeset_driver_remove(struct drm_i915_private *i915);
0683 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
0684 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
0685 void intel_display_resume(struct drm_device *dev);
0686 int intel_modeset_all_pipes(struct intel_atomic_state *state);
0687 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
0688                       struct intel_power_domain_mask *old_domains);
0689 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
0690                       struct intel_power_domain_mask *domains);
0691 
0692 /* modesetting asserts */
0693 void assert_transcoder(struct drm_i915_private *dev_priv,
0694                enum transcoder cpu_transcoder, bool state);
0695 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
0696 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
0697 
0698 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
0699  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
0700  * which may not necessarily be a user visible problem.  This will either
0701  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
0702  * enable distros and users to tailor their preferred amount of i915 abrt
0703  * spam.
0704  */
0705 #define I915_STATE_WARN(condition, format...) ({            \
0706     int __ret_warn_on = !!(condition);              \
0707     if (unlikely(__ret_warn_on))                    \
0708         if (!WARN(i915_modparams.verbose_state_checks, format)) \
0709             DRM_ERROR(format);              \
0710     unlikely(__ret_warn_on);                    \
0711 })
0712 
0713 #define I915_STATE_WARN_ON(x)                       \
0714     I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
0715 
0716 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
0717 
0718 #endif
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