i915/display/intel_de.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_DE_H__
0007 #define __INTEL_DE_H__
0008
0009 #include "i915_drv.h"
0010 #include "i915_trace.h"
0011 #include "intel_uncore.h"
0012
0013 static inline u32
0014 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
0015 {
0016     return intel_uncore_read(&i915->uncore, reg);
0017 }
0018
0019 static inline void
0020 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
0021 {
0022     intel_uncore_posting_read(&i915->uncore, reg);
0023 }
0024
0025 static inline void
0026 intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
0027 {
0028     intel_uncore_write(&i915->uncore, reg, val);
0029 }
0030
0031 static inline void
0032 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
0033 {
0034     intel_uncore_rmw(&i915->uncore, reg, clear, set);
0035 }
0036
0037 static inline int
0038 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
0039                u32 mask, u32 value, unsigned int timeout)
0040 {
0041     return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
0042 }
0043
0044 static inline int
0045 intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
0046               u32 mask, unsigned int timeout)
0047 {
0048     return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
0049 }
0050
0051 static inline int
0052 intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
0053             u32 mask, unsigned int timeout)
0054 {
0055     return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
0056 }
0057
0058 /*
0059  * Unlocked mmio-accessors, think carefully before using these.
0060  *
0061  * Certain architectures will die if the same cacheline is concurrently accessed
0062  * by different clients (e.g. on Ivybridge). Access to registers should
0063  * therefore generally be serialised, by either the dev_priv->uncore.lock or
0064  * a more localised lock guarding all access to that bank of registers.
0065  */
0066 static inline u32
0067 intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
0068 {
0069     u32 val;
0070
0071     val = intel_uncore_read_fw(&i915->uncore, reg);
0072     trace_i915_reg_rw(false, reg, val, sizeof(val), true);
0073
0074     return val;
0075 }
0076
0077 static inline void
0078 intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
0079 {
0080     trace_i915_reg_rw(true, reg, val, sizeof(val), true);
0081     intel_uncore_write_fw(&i915->uncore, reg, val);
0082 }
0083
0084 #endif /* __INTEL_DE_H__ */