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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2020 Intel Corporation
0004  */
0005 
0006 #include "i915_drv.h"
0007 #include "intel_ddi.h"
0008 #include "intel_ddi_buf_trans.h"
0009 #include "intel_de.h"
0010 #include "intel_display_types.h"
0011 #include "intel_dp.h"
0012 
0013 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
0014  * them for both DP and FDI transports, allowing those ports to
0015  * automatically adapt to HDMI connections as well
0016  */
0017 static const union intel_ddi_buf_trans_entry _hsw_trans_dp[] = {
0018     { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
0019     { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
0020     { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
0021     { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
0022     { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
0023     { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
0024     { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
0025     { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
0026     { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
0027 };
0028 
0029 static const struct intel_ddi_buf_trans hsw_trans_dp = {
0030     .entries = _hsw_trans_dp,
0031     .num_entries = ARRAY_SIZE(_hsw_trans_dp),
0032 };
0033 
0034 static const union intel_ddi_buf_trans_entry _hsw_trans_fdi[] = {
0035     { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
0036     { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } },
0037     { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } },
0038     { .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } },
0039     { .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } },
0040     { .hsw = { 0x00D75FFF, 0x00160004, 0x0 } },
0041     { .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } },
0042     { .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } },
0043     { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } },
0044 };
0045 
0046 static const struct intel_ddi_buf_trans hsw_trans_fdi = {
0047     .entries = _hsw_trans_fdi,
0048     .num_entries = ARRAY_SIZE(_hsw_trans_fdi),
0049 };
0050 
0051 static const union intel_ddi_buf_trans_entry _hsw_trans_hdmi[] = {
0052                             /* Idx  NT mV d T mV d  db  */
0053     { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0:   400 400 0   */
0054     { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1:   400 500 2   */
0055     { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, /* 2:   400 600 3.5 */
0056     { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, /* 3:   600 600 0   */
0057     { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } }, /* 4:   600 750 2   */
0058     { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, /* 5:   600 900 3.5 */
0059     { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, /* 6:   800 800 0   */
0060     { .hsw = { 0x80E79FFF, 0x00030002, 0x0 } }, /* 7:   800 1000    2   */
0061     { .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } }, /* 8:   850 850 0   */
0062     { .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } }, /* 9:   900 900 0   */
0063     { .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } }, /* 10:  950 950 0   */
0064     { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11:  1000    1000    0   */
0065 };
0066 
0067 static const struct intel_ddi_buf_trans hsw_trans_hdmi = {
0068     .entries = _hsw_trans_hdmi,
0069     .num_entries = ARRAY_SIZE(_hsw_trans_hdmi),
0070     .hdmi_default_entry = 6,
0071 };
0072 
0073 static const union intel_ddi_buf_trans_entry _bdw_trans_edp[] = {
0074     { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } },
0075     { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } },
0076     { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } },
0077     { .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } },
0078     { .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } },
0079     { .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } },
0080     { .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } },
0081     { .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } },
0082     { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } },
0083 };
0084 
0085 static const struct intel_ddi_buf_trans bdw_trans_edp = {
0086     .entries = _bdw_trans_edp,
0087     .num_entries = ARRAY_SIZE(_bdw_trans_edp),
0088 };
0089 
0090 static const union intel_ddi_buf_trans_entry _bdw_trans_dp[] = {
0091     { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
0092     { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },
0093     { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },
0094     { .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } },
0095     { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },
0096     { .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } },
0097     { .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } },
0098     { .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } },
0099     { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } },
0100 };
0101 
0102 static const struct intel_ddi_buf_trans bdw_trans_dp = {
0103     .entries = _bdw_trans_dp,
0104     .num_entries = ARRAY_SIZE(_bdw_trans_dp),
0105 };
0106 
0107 static const union intel_ddi_buf_trans_entry _bdw_trans_fdi[] = {
0108     { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } },
0109     { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } },
0110     { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } },
0111     { .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } },
0112     { .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } },
0113     { .hsw = { 0x00D75FFF, 0x00090004, 0x0 } },
0114     { .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } },
0115     { .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } },
0116     { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } },
0117 };
0118 
0119 static const struct intel_ddi_buf_trans bdw_trans_fdi = {
0120     .entries = _bdw_trans_fdi,
0121     .num_entries = ARRAY_SIZE(_bdw_trans_fdi),
0122 };
0123 
0124 static const union intel_ddi_buf_trans_entry _bdw_trans_hdmi[] = {
0125                             /* Idx  NT mV d T mV df db  */
0126     { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0:   400 400 0   */
0127     { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1:   400 600 3.5 */
0128     { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, /* 2:   400 800 6   */
0129     { .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } }, /* 3:   450 450 0   */
0130     { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, /* 4:   600 600 0   */
0131     { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } }, /* 5:   600 800 2.5 */
0132     { .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } }, /* 6:   600 1000    4.5 */
0133     { .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } }, /* 7:   800 800 0   */
0134     { .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } }, /* 8:   800 1000    2   */
0135     { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9:   1000    1000    0   */
0136 };
0137 
0138 static const struct intel_ddi_buf_trans bdw_trans_hdmi = {
0139     .entries = _bdw_trans_hdmi,
0140     .num_entries = ARRAY_SIZE(_bdw_trans_hdmi),
0141     .hdmi_default_entry = 7,
0142 };
0143 
0144 /* Skylake H and S */
0145 static const union intel_ddi_buf_trans_entry _skl_trans_dp[] = {
0146     { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
0147     { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
0148     { .hsw = { 0x00007011, 0x00000088, 0x0 } },
0149     { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
0150     { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
0151     { .hsw = { 0x00005012, 0x00000088, 0x0 } },
0152     { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
0153     { .hsw = { 0x00002016, 0x000000DF, 0x0 } },
0154     { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
0155 };
0156 
0157 static const struct intel_ddi_buf_trans skl_trans_dp = {
0158     .entries = _skl_trans_dp,
0159     .num_entries = ARRAY_SIZE(_skl_trans_dp),
0160 };
0161 
0162 /* Skylake U */
0163 static const union intel_ddi_buf_trans_entry _skl_u_trans_dp[] = {
0164     { .hsw = { 0x0000201B, 0x000000A2, 0x0 } },
0165     { .hsw = { 0x00005012, 0x00000088, 0x0 } },
0166     { .hsw = { 0x80007011, 0x000000CD, 0x1 } },
0167     { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
0168     { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
0169     { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
0170     { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
0171     { .hsw = { 0x00002016, 0x00000088, 0x0 } },
0172     { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
0173 };
0174 
0175 static const struct intel_ddi_buf_trans skl_u_trans_dp = {
0176     .entries = _skl_u_trans_dp,
0177     .num_entries = ARRAY_SIZE(_skl_u_trans_dp),
0178 };
0179 
0180 /* Skylake Y */
0181 static const union intel_ddi_buf_trans_entry _skl_y_trans_dp[] = {
0182     { .hsw = { 0x00000018, 0x000000A2, 0x0 } },
0183     { .hsw = { 0x00005012, 0x00000088, 0x0 } },
0184     { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
0185     { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
0186     { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
0187     { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
0188     { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
0189     { .hsw = { 0x00000018, 0x00000088, 0x0 } },
0190     { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
0191 };
0192 
0193 static const struct intel_ddi_buf_trans skl_y_trans_dp = {
0194     .entries = _skl_y_trans_dp,
0195     .num_entries = ARRAY_SIZE(_skl_y_trans_dp),
0196 };
0197 
0198 /* Kabylake H and S */
0199 static const union intel_ddi_buf_trans_entry _kbl_trans_dp[] = {
0200     { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
0201     { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
0202     { .hsw = { 0x00007011, 0x00000088, 0x0 } },
0203     { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
0204     { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
0205     { .hsw = { 0x00005012, 0x00000088, 0x0 } },
0206     { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
0207     { .hsw = { 0x00002016, 0x00000097, 0x0 } },
0208     { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
0209 };
0210 
0211 static const struct intel_ddi_buf_trans kbl_trans_dp = {
0212     .entries = _kbl_trans_dp,
0213     .num_entries = ARRAY_SIZE(_kbl_trans_dp),
0214 };
0215 
0216 /* Kabylake U */
0217 static const union intel_ddi_buf_trans_entry _kbl_u_trans_dp[] = {
0218     { .hsw = { 0x0000201B, 0x000000A1, 0x0 } },
0219     { .hsw = { 0x00005012, 0x00000088, 0x0 } },
0220     { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
0221     { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
0222     { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
0223     { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
0224     { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
0225     { .hsw = { 0x00002016, 0x0000004F, 0x0 } },
0226     { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
0227 };
0228 
0229 static const struct intel_ddi_buf_trans kbl_u_trans_dp = {
0230     .entries = _kbl_u_trans_dp,
0231     .num_entries = ARRAY_SIZE(_kbl_u_trans_dp),
0232 };
0233 
0234 /* Kabylake Y */
0235 static const union intel_ddi_buf_trans_entry _kbl_y_trans_dp[] = {
0236     { .hsw = { 0x00001017, 0x000000A1, 0x0 } },
0237     { .hsw = { 0x00005012, 0x00000088, 0x0 } },
0238     { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
0239     { .hsw = { 0x8000800F, 0x000000C0, 0x3 } },
0240     { .hsw = { 0x00001017, 0x0000009D, 0x0 } },
0241     { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
0242     { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
0243     { .hsw = { 0x00001017, 0x0000004C, 0x0 } },
0244     { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
0245 };
0246 
0247 static const struct intel_ddi_buf_trans kbl_y_trans_dp = {
0248     .entries = _kbl_y_trans_dp,
0249     .num_entries = ARRAY_SIZE(_kbl_y_trans_dp),
0250 };
0251 
0252 /*
0253  * Skylake/Kabylake H and S
0254  * eDP 1.4 low vswing translation parameters
0255  */
0256 static const union intel_ddi_buf_trans_entry _skl_trans_edp[] = {
0257     { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
0258     { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
0259     { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
0260     { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
0261     { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
0262     { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
0263     { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
0264     { .hsw = { 0x00000018, 0x000000AB, 0x0 } },
0265     { .hsw = { 0x00007013, 0x0000009F, 0x0 } },
0266     { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
0267 };
0268 
0269 static const struct intel_ddi_buf_trans skl_trans_edp = {
0270     .entries = _skl_trans_edp,
0271     .num_entries = ARRAY_SIZE(_skl_trans_edp),
0272 };
0273 
0274 /*
0275  * Skylake/Kabylake U
0276  * eDP 1.4 low vswing translation parameters
0277  */
0278 static const union intel_ddi_buf_trans_entry _skl_u_trans_edp[] = {
0279     { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
0280     { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
0281     { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
0282     { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
0283     { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
0284     { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
0285     { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
0286     { .hsw = { 0x00002016, 0x000000AB, 0x0 } },
0287     { .hsw = { 0x00005013, 0x0000009F, 0x0 } },
0288     { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
0289 };
0290 
0291 static const struct intel_ddi_buf_trans skl_u_trans_edp = {
0292     .entries = _skl_u_trans_edp,
0293     .num_entries = ARRAY_SIZE(_skl_u_trans_edp),
0294 };
0295 
0296 /*
0297  * Skylake/Kabylake Y
0298  * eDP 1.4 low vswing translation parameters
0299  */
0300 static const union intel_ddi_buf_trans_entry _skl_y_trans_edp[] = {
0301     { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
0302     { .hsw = { 0x00004013, 0x000000AB, 0x0 } },
0303     { .hsw = { 0x00007011, 0x000000A4, 0x0 } },
0304     { .hsw = { 0x00009010, 0x000000DF, 0x0 } },
0305     { .hsw = { 0x00000018, 0x000000AA, 0x0 } },
0306     { .hsw = { 0x00006013, 0x000000A4, 0x0 } },
0307     { .hsw = { 0x00007011, 0x0000009D, 0x0 } },
0308     { .hsw = { 0x00000018, 0x000000A0, 0x0 } },
0309     { .hsw = { 0x00006012, 0x000000DF, 0x0 } },
0310     { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
0311 };
0312 
0313 static const struct intel_ddi_buf_trans skl_y_trans_edp = {
0314     .entries = _skl_y_trans_edp,
0315     .num_entries = ARRAY_SIZE(_skl_y_trans_edp),
0316 };
0317 
0318 /* Skylake/Kabylake U, H and S */
0319 static const union intel_ddi_buf_trans_entry _skl_trans_hdmi[] = {
0320     { .hsw = { 0x00000018, 0x000000AC, 0x0 } },
0321     { .hsw = { 0x00005012, 0x0000009D, 0x0 } },
0322     { .hsw = { 0x00007011, 0x00000088, 0x0 } },
0323     { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
0324     { .hsw = { 0x00000018, 0x00000098, 0x0 } },
0325     { .hsw = { 0x00004013, 0x00000088, 0x0 } },
0326     { .hsw = { 0x80006012, 0x000000CD, 0x1 } },
0327     { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
0328     { .hsw = { 0x80003015, 0x000000CD, 0x1 } }, /* Default */
0329     { .hsw = { 0x80003015, 0x000000C0, 0x1 } },
0330     { .hsw = { 0x80000018, 0x000000C0, 0x1 } },
0331 };
0332 
0333 static const struct intel_ddi_buf_trans skl_trans_hdmi = {
0334     .entries = _skl_trans_hdmi,
0335     .num_entries = ARRAY_SIZE(_skl_trans_hdmi),
0336     .hdmi_default_entry = 8,
0337 };
0338 
0339 /* Skylake/Kabylake Y */
0340 static const union intel_ddi_buf_trans_entry _skl_y_trans_hdmi[] = {
0341     { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
0342     { .hsw = { 0x00005012, 0x000000DF, 0x0 } },
0343     { .hsw = { 0x80007011, 0x000000CB, 0x3 } },
0344     { .hsw = { 0x00000018, 0x000000A4, 0x0 } },
0345     { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
0346     { .hsw = { 0x00004013, 0x00000080, 0x0 } },
0347     { .hsw = { 0x80006013, 0x000000C0, 0x3 } },
0348     { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
0349     { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, /* Default */
0350     { .hsw = { 0x80003015, 0x000000C0, 0x3 } },
0351     { .hsw = { 0x80000018, 0x000000C0, 0x3 } },
0352 };
0353 
0354 static const struct intel_ddi_buf_trans skl_y_trans_hdmi = {
0355     .entries = _skl_y_trans_hdmi,
0356     .num_entries = ARRAY_SIZE(_skl_y_trans_hdmi),
0357     .hdmi_default_entry = 8,
0358 };
0359 
0360 static const union intel_ddi_buf_trans_entry _bxt_trans_dp[] = {
0361                         /* Idx  NT mV diff  db  */
0362     { .bxt = { 52,  0x9A, 0, 128, } },  /* 0:   400     0   */
0363     { .bxt = { 78,  0x9A, 0, 85,  } },  /* 1:   400     3.5 */
0364     { .bxt = { 104, 0x9A, 0, 64,  } },  /* 2:   400     6   */
0365     { .bxt = { 154, 0x9A, 0, 43,  } },  /* 3:   400     9.5 */
0366     { .bxt = { 77,  0x9A, 0, 128, } },  /* 4:   600     0   */
0367     { .bxt = { 116, 0x9A, 0, 85,  } },  /* 5:   600     3.5 */
0368     { .bxt = { 154, 0x9A, 0, 64,  } },  /* 6:   600     6   */
0369     { .bxt = { 102, 0x9A, 0, 128, } },  /* 7:   800     0   */
0370     { .bxt = { 154, 0x9A, 0, 85,  } },  /* 8:   800     3.5 */
0371     { .bxt = { 154, 0x9A, 1, 128, } },  /* 9:   1200        0   */
0372 };
0373 
0374 static const struct intel_ddi_buf_trans bxt_trans_dp = {
0375     .entries = _bxt_trans_dp,
0376     .num_entries = ARRAY_SIZE(_bxt_trans_dp),
0377 };
0378 
0379 static const union intel_ddi_buf_trans_entry _bxt_trans_edp[] = {
0380                     /* Idx  NT mV diff  db  */
0381     { .bxt = { 26, 0, 0, 128, } },  /* 0:   200     0   */
0382     { .bxt = { 38, 0, 0, 112, } },  /* 1:   200     1.5 */
0383     { .bxt = { 48, 0, 0, 96,  } },  /* 2:   200     4   */
0384     { .bxt = { 54, 0, 0, 69,  } },  /* 3:   200     6   */
0385     { .bxt = { 32, 0, 0, 128, } },  /* 4:   250     0   */
0386     { .bxt = { 48, 0, 0, 104, } },  /* 5:   250     1.5 */
0387     { .bxt = { 54, 0, 0, 85,  } },  /* 6:   250     4   */
0388     { .bxt = { 43, 0, 0, 128, } },  /* 7:   300     0   */
0389     { .bxt = { 54, 0, 0, 101, } },  /* 8:   300     1.5 */
0390     { .bxt = { 48, 0, 0, 128, } },  /* 9:   300     0   */
0391 };
0392 
0393 static const struct intel_ddi_buf_trans bxt_trans_edp = {
0394     .entries = _bxt_trans_edp,
0395     .num_entries = ARRAY_SIZE(_bxt_trans_edp),
0396 };
0397 
0398 /* BSpec has 2 recommended values - entries 0 and 8.
0399  * Using the entry with higher vswing.
0400  */
0401 static const union intel_ddi_buf_trans_entry _bxt_trans_hdmi[] = {
0402                         /* Idx  NT mV diff  db  */
0403     { .bxt = { 52,  0x9A, 0, 128, } },  /* 0:   400     0   */
0404     { .bxt = { 52,  0x9A, 0, 85,  } },  /* 1:   400     3.5 */
0405     { .bxt = { 52,  0x9A, 0, 64,  } },  /* 2:   400     6   */
0406     { .bxt = { 42,  0x9A, 0, 43,  } },  /* 3:   400     9.5 */
0407     { .bxt = { 77,  0x9A, 0, 128, } },  /* 4:   600     0   */
0408     { .bxt = { 77,  0x9A, 0, 85,  } },  /* 5:   600     3.5 */
0409     { .bxt = { 77,  0x9A, 0, 64,  } },  /* 6:   600     6   */
0410     { .bxt = { 102, 0x9A, 0, 128, } },  /* 7:   800     0   */
0411     { .bxt = { 102, 0x9A, 0, 85,  } },  /* 8:   800     3.5 */
0412     { .bxt = { 154, 0x9A, 1, 128, } },  /* 9:   1200        0   */
0413 };
0414 
0415 static const struct intel_ddi_buf_trans bxt_trans_hdmi = {
0416     .entries = _bxt_trans_hdmi,
0417     .num_entries = ARRAY_SIZE(_bxt_trans_hdmi),
0418     .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
0419 };
0420 
0421 /* icl_combo_phy_trans */
0422 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
0423                             /* NT mV Trans mV db    */
0424     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0425     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0426     { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350   700      6.0   */
0427     { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900      8.2   */
0428     { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0429     { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700      2.9   */
0430     { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900      5.1   */
0431     { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650   700      0.6   */
0432     { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900      3.5   */
0433     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0434 };
0435 
0436 static const struct intel_ddi_buf_trans icl_combo_phy_trans_dp_hbr2_edp_hbr3 = {
0437     .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
0438     .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
0439 };
0440 
0441 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_edp_hbr2[] = {
0442                             /* NT mV Trans mV db    */
0443     { .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200   200      0.0   */
0444     { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200   250      1.9   */
0445     { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200   300      3.5   */
0446     { .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } }, /* 200   350      4.9   */
0447     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250   250      0.0   */
0448     { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250   300      1.6   */
0449     { .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } }, /* 250   350      2.9   */
0450     { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300   300      0.0   */
0451     { .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 300   350      1.3   */
0452     { .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0453 };
0454 
0455 static const struct intel_ddi_buf_trans icl_combo_phy_trans_edp_hbr2 = {
0456     .entries = _icl_combo_phy_trans_edp_hbr2,
0457     .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2),
0458 };
0459 
0460 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_hdmi[] = {
0461                             /* NT mV Trans mV db    */
0462     { .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450   450      0.0   */
0463     { .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450   650      3.2   */
0464     { .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450   850      5.5   */
0465     { .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650   650      0.0   ALS */
0466     { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650   850      2.3   */
0467     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850   850      0.0   */
0468     { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   850      3.0   */
0469 };
0470 
0471 static const struct intel_ddi_buf_trans icl_combo_phy_trans_hdmi = {
0472     .entries = _icl_combo_phy_trans_hdmi,
0473     .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_hdmi),
0474     .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1,
0475 };
0476 
0477 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_dp[] = {
0478                             /* NT mV Trans mV db    */
0479     { .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0480     { .icl = { 0xA, 0x47, 0x38, 0x00, 0x07 } }, /* 350   500      3.1   */
0481     { .icl = { 0xC, 0x64, 0x33, 0x00, 0x0C } }, /* 350   700      6.0   */
0482     { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 350   900      8.2   */
0483     { .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0484     { .icl = { 0xC, 0x64, 0x37, 0x00, 0x08 } }, /* 500   700      2.9   */
0485     { .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500   900      5.1   */
0486     { .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650   700      0.6   */
0487     { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600   900      3.5   */
0488     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0489 };
0490 
0491 static const struct intel_ddi_buf_trans ehl_combo_phy_trans_dp = {
0492     .entries = _ehl_combo_phy_trans_dp,
0493     .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_dp),
0494 };
0495 
0496 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_edp_hbr2[] = {
0497                             /* NT mV Trans mV db    */
0498     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200   200      0.0   */
0499     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200   250      1.9   */
0500     { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200   300      3.5   */
0501     { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 200   350      4.9   */
0502     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250   250      0.0   */
0503     { .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } }, /* 250   300      1.6   */
0504     { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 250   350      2.9   */
0505     { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300   300      0.0   */
0506     { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300   350      1.3   */
0507     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0508 };
0509 
0510 static const struct intel_ddi_buf_trans ehl_combo_phy_trans_edp_hbr2 = {
0511     .entries = _ehl_combo_phy_trans_edp_hbr2,
0512     .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_edp_hbr2),
0513 };
0514 
0515 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr[] = {
0516                             /* NT mV Trans mV db    */
0517     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200   200      0.0   */
0518     { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200   250      1.9   */
0519     { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200   300      3.5   */
0520     { .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } }, /* 200   350      4.9   */
0521     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250   250      0.0   */
0522     { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250   300      1.6   */
0523     { .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } }, /* 250   350      2.9   */
0524     { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300   300      0.0   */
0525     { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300   350      1.3   */
0526     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0527 };
0528 
0529 static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr = {
0530     .entries = _jsl_combo_phy_trans_edp_hbr,
0531     .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr),
0532 };
0533 
0534 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr2[] = {
0535                             /* NT mV Trans mV db    */
0536     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200   200      0.0   */
0537     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200   250      1.9   */
0538     { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200   300      3.5   */
0539     { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 200   350      4.9   */
0540     { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250   250      0.0   */
0541     { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250   300      1.6   */
0542     { .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } }, /* 250   350      2.9   */
0543     { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300   300      0.0   */
0544     { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300   350      1.3   */
0545     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0546 };
0547 
0548 static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr2 = {
0549     .entries = _jsl_combo_phy_trans_edp_hbr2,
0550     .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr2),
0551 };
0552 
0553 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_rbr_hbr[] = {
0554                             /* NT mV Trans mV db    */
0555     { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0556     { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350   500      3.1   */
0557     { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350   700      6.0   */
0558     { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350   900      8.2   */
0559     { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0560     { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500   700      2.9   */
0561     { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500   900      5.1   */
0562     { .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } }, /* 650   700      0.6   */
0563     { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600   900      3.5   */
0564     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0565 };
0566 
0567 static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_rbr_hbr = {
0568     .entries = _dg1_combo_phy_trans_dp_rbr_hbr,
0569     .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_rbr_hbr),
0570 };
0571 
0572 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_hbr2_hbr3[] = {
0573                             /* NT mV Trans mV db    */
0574     { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0575     { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350   500      3.1   */
0576     { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350   700      6.0   */
0577     { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350   900      8.2   */
0578     { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0579     { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500   700      2.9   */
0580     { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500   900      5.1   */
0581     { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650   700      0.6   */
0582     { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900      3.5   */
0583     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0584 };
0585 
0586 static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_hbr2_hbr3 = {
0587     .entries = _dg1_combo_phy_trans_dp_hbr2_hbr3,
0588     .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_hbr2_hbr3),
0589 };
0590 
0591 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_rbr_hbr[] = {
0592                     /* Voltage swing  pre-emphasis */
0593     { .mg = { 0x18, 0x00, 0x00 } }, /* 0              0   */
0594     { .mg = { 0x1D, 0x00, 0x05 } }, /* 0              1   */
0595     { .mg = { 0x24, 0x00, 0x0C } }, /* 0              2   */
0596     { .mg = { 0x2B, 0x00, 0x14 } }, /* 0              3   */
0597     { .mg = { 0x21, 0x00, 0x00 } }, /* 1              0   */
0598     { .mg = { 0x2B, 0x00, 0x08 } }, /* 1              1   */
0599     { .mg = { 0x30, 0x00, 0x0F } }, /* 1              2   */
0600     { .mg = { 0x31, 0x00, 0x03 } }, /* 2              0   */
0601     { .mg = { 0x34, 0x00, 0x0B } }, /* 2              1   */
0602     { .mg = { 0x3F, 0x00, 0x00 } }, /* 3              0   */
0603 };
0604 
0605 static const struct intel_ddi_buf_trans icl_mg_phy_trans_rbr_hbr = {
0606     .entries = _icl_mg_phy_trans_rbr_hbr,
0607     .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_rbr_hbr),
0608 };
0609 
0610 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hbr2_hbr3[] = {
0611                     /* Voltage swing  pre-emphasis */
0612     { .mg = { 0x18, 0x00, 0x00 } }, /* 0              0   */
0613     { .mg = { 0x1D, 0x00, 0x05 } }, /* 0              1   */
0614     { .mg = { 0x24, 0x00, 0x0C } }, /* 0              2   */
0615     { .mg = { 0x2B, 0x00, 0x14 } }, /* 0              3   */
0616     { .mg = { 0x26, 0x00, 0x00 } }, /* 1              0   */
0617     { .mg = { 0x2C, 0x00, 0x07 } }, /* 1              1   */
0618     { .mg = { 0x33, 0x00, 0x0C } }, /* 1              2   */
0619     { .mg = { 0x2E, 0x00, 0x00 } }, /* 2              0   */
0620     { .mg = { 0x36, 0x00, 0x09 } }, /* 2              1   */
0621     { .mg = { 0x3F, 0x00, 0x00 } }, /* 3              0   */
0622 };
0623 
0624 static const struct intel_ddi_buf_trans icl_mg_phy_trans_hbr2_hbr3 = {
0625     .entries = _icl_mg_phy_trans_hbr2_hbr3,
0626     .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hbr2_hbr3),
0627 };
0628 
0629 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hdmi[] = {
0630                     /* HDMI Preset  VS  Pre-emph */
0631     { .mg = { 0x1A, 0x0, 0x0 } },   /* 1        400mV   0dB */
0632     { .mg = { 0x20, 0x0, 0x0 } },   /* 2        500mV   0dB */
0633     { .mg = { 0x29, 0x0, 0x0 } },   /* 3        650mV   0dB */
0634     { .mg = { 0x32, 0x0, 0x0 } },   /* 4        800mV   0dB */
0635     { .mg = { 0x3F, 0x0, 0x0 } },   /* 5        1000mV  0dB */
0636     { .mg = { 0x3A, 0x0, 0x5 } },   /* 6        Full    -1.5 dB */
0637     { .mg = { 0x39, 0x0, 0x6 } },   /* 7        Full    -1.8 dB */
0638     { .mg = { 0x38, 0x0, 0x7 } },   /* 8        Full    -2 dB */
0639     { .mg = { 0x37, 0x0, 0x8 } },   /* 9        Full    -2.5 dB */
0640     { .mg = { 0x36, 0x0, 0x9 } },   /* 10       Full    -3 dB */
0641 };
0642 
0643 static const struct intel_ddi_buf_trans icl_mg_phy_trans_hdmi = {
0644     .entries = _icl_mg_phy_trans_hdmi,
0645     .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hdmi),
0646     .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_trans_hdmi) - 1,
0647 };
0648 
0649 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr[] = {
0650                     /* VS   pre-emp Non-trans mV    Pre-emph dB */
0651     { .dkl = { 0x7, 0x0, 0x00 } },  /* 0    0   400mV       0 dB */
0652     { .dkl = { 0x5, 0x0, 0x05 } },  /* 0    1   400mV       3.5 dB */
0653     { .dkl = { 0x2, 0x0, 0x0B } },  /* 0    2   400mV       6 dB */
0654     { .dkl = { 0x0, 0x0, 0x18 } },  /* 0    3   400mV       9.5 dB */
0655     { .dkl = { 0x5, 0x0, 0x00 } },  /* 1    0   600mV       0 dB */
0656     { .dkl = { 0x2, 0x0, 0x08 } },  /* 1    1   600mV       3.5 dB */
0657     { .dkl = { 0x0, 0x0, 0x14 } },  /* 1    2   600mV       6 dB */
0658     { .dkl = { 0x2, 0x0, 0x00 } },  /* 2    0   800mV       0 dB */
0659     { .dkl = { 0x0, 0x0, 0x0B } },  /* 2    1   800mV       3.5 dB */
0660     { .dkl = { 0x0, 0x0, 0x00 } },  /* 3    0   1200mV      0 dB HDMI default */
0661 };
0662 
0663 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr = {
0664     .entries = _tgl_dkl_phy_trans_dp_hbr,
0665     .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr),
0666 };
0667 
0668 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr2[] = {
0669                     /* VS   pre-emp Non-trans mV    Pre-emph dB */
0670     { .dkl = { 0x7, 0x0, 0x00 } },  /* 0    0   400mV       0 dB */
0671     { .dkl = { 0x5, 0x0, 0x05 } },  /* 0    1   400mV       3.5 dB */
0672     { .dkl = { 0x2, 0x0, 0x0B } },  /* 0    2   400mV       6 dB */
0673     { .dkl = { 0x0, 0x0, 0x19 } },  /* 0    3   400mV       9.5 dB */
0674     { .dkl = { 0x5, 0x0, 0x00 } },  /* 1    0   600mV       0 dB */
0675     { .dkl = { 0x2, 0x0, 0x08 } },  /* 1    1   600mV       3.5 dB */
0676     { .dkl = { 0x0, 0x0, 0x14 } },  /* 1    2   600mV       6 dB */
0677     { .dkl = { 0x2, 0x0, 0x00 } },  /* 2    0   800mV       0 dB */
0678     { .dkl = { 0x0, 0x0, 0x0B } },  /* 2    1   800mV       3.5 dB */
0679     { .dkl = { 0x0, 0x0, 0x00 } },  /* 3    0   1200mV      0 dB HDMI default */
0680 };
0681 
0682 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr2 = {
0683     .entries = _tgl_dkl_phy_trans_dp_hbr2,
0684     .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr2),
0685 };
0686 
0687 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_hdmi[] = {
0688                     /* HDMI Preset  VS  Pre-emph */
0689     { .dkl = { 0x7, 0x0, 0x0 } },   /* 1        400mV   0dB */
0690     { .dkl = { 0x6, 0x0, 0x0 } },   /* 2        500mV   0dB */
0691     { .dkl = { 0x4, 0x0, 0x0 } },   /* 3        650mV   0dB */
0692     { .dkl = { 0x2, 0x0, 0x0 } },   /* 4        800mV   0dB */
0693     { .dkl = { 0x0, 0x0, 0x0 } },   /* 5        1000mV  0dB */
0694     { .dkl = { 0x0, 0x0, 0x5 } },   /* 6        Full    -1.5 dB */
0695     { .dkl = { 0x0, 0x0, 0x6 } },   /* 7        Full    -1.8 dB */
0696     { .dkl = { 0x0, 0x0, 0x7 } },   /* 8        Full    -2 dB */
0697     { .dkl = { 0x0, 0x0, 0x8 } },   /* 9        Full    -2.5 dB */
0698     { .dkl = { 0x0, 0x0, 0xA } },   /* 10       Full    -3 dB */
0699 };
0700 
0701 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_hdmi = {
0702     .entries = _tgl_dkl_phy_trans_hdmi,
0703     .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi),
0704     .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi) - 1,
0705 };
0706 
0707 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr[] = {
0708                             /* NT mV Trans mV db    */
0709     { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0710     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0711     { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350   700      6.0   */
0712     { .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350   900      8.2   */
0713     { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0714     { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700      2.9   */
0715     { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900      5.1   */
0716     { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650   700      0.6   */
0717     { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900      3.5   */
0718     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0719 };
0720 
0721 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr = {
0722     .entries = _tgl_combo_phy_trans_dp_hbr,
0723     .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr),
0724 };
0725 
0726 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr2[] = {
0727                             /* NT mV Trans mV db    */
0728     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0729     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0730     { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350   700      6.0   */
0731     { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900      8.2   */
0732     { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0733     { .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } }, /* 500   700      2.9   */
0734     { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900      5.1   */
0735     { .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650   700      0.6   */
0736     { .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600   900      3.5   */
0737     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0738 };
0739 
0740 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr2 = {
0741     .entries = _tgl_combo_phy_trans_dp_hbr2,
0742     .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr2),
0743 };
0744 
0745 static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_trans_dp_hbr2[] = {
0746                             /* NT mV Trans mV db    */
0747     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0748     { .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350   500      3.1   */
0749     { .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } }, /* 350   700      6.0   */
0750     { .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } }, /* 350   900      8.2   */
0751     { .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0752     { .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } }, /* 500   700      2.9   */
0753     { .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 500   900      5.1   */
0754     { .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } }, /* 650   700      0.6   */
0755     { .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } }, /* 600   900      3.5   */
0756     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0757 };
0758 
0759 static const struct intel_ddi_buf_trans tgl_uy_combo_phy_trans_dp_hbr2 = {
0760     .entries = _tgl_uy_combo_phy_trans_dp_hbr2,
0761     .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_trans_dp_hbr2),
0762 };
0763 
0764 /*
0765  * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
0766  * that DisplayPort specification requires
0767  */
0768 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_edp_hbr2_hobl[] = {
0769                             /* VS   pre-emp */
0770     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0    0   */
0771     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0    1   */
0772     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0    2   */
0773     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0    3   */
0774     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1    0   */
0775     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1    1   */
0776     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1    2   */
0777     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2    0   */
0778     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2    1   */
0779 };
0780 
0781 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_edp_hbr2_hobl = {
0782     .entries = _tgl_combo_phy_trans_edp_hbr2_hobl,
0783     .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_edp_hbr2_hobl),
0784 };
0785 
0786 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr[] = {
0787                             /* NT mV Trans mV db    */
0788     { .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0789     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0790     { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350   700      6.0   */
0791     { .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } }, /* 350   900      8.2   */
0792     { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0793     { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700      2.9   */
0794     { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900      5.1   */
0795     { .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } }, /* 650   700      0.6   */
0796     { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900      3.5   */
0797     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0798 };
0799 
0800 static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr = {
0801     .entries = _rkl_combo_phy_trans_dp_hbr,
0802     .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr),
0803 };
0804 
0805 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr2_hbr3[] = {
0806                             /* NT mV Trans mV db    */
0807     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0808     { .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350   500      3.1   */
0809     { .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } }, /* 350   700      6.0   */
0810     { .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350   900      8.2   */
0811     { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0812     { .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } }, /* 500   700      2.9   */
0813     { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900      5.1   */
0814     { .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } }, /* 650   700      0.6   */
0815     { .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } }, /* 600   900      3.5   */
0816     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0817 };
0818 
0819 static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr2_hbr3 = {
0820     .entries = _rkl_combo_phy_trans_dp_hbr2_hbr3,
0821     .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr2_hbr3),
0822 };
0823 
0824 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_dp_hbr2_hbr3[] = {
0825                             /* NT mV Trans mV db    */
0826     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0827     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0828     { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350   700      6.0   */
0829     { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350   900      8.2   */
0830     { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0831     { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500   700      2.9   */
0832     { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500   900      5.1   */
0833     { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650   700      0.6   */
0834     { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900      3.5   */
0835     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0836 };
0837 
0838 static const struct intel_ddi_buf_trans adls_combo_phy_trans_dp_hbr2_hbr3 = {
0839     .entries = _adls_combo_phy_trans_dp_hbr2_hbr3,
0840     .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_dp_hbr2_hbr3),
0841 };
0842 
0843 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr2[] = {
0844                             /* NT mV Trans mV db    */
0845     { .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } }, /* 200   200      0.0   */
0846     { .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } }, /* 200   250      1.9   */
0847     { .icl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } }, /* 200   300      3.5   */
0848     { .icl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } }, /* 200   350      4.9   */
0849     { .icl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } }, /* 250   250      0.0   */
0850     { .icl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } }, /* 250   300      1.6   */
0851     { .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250   350      2.9   */
0852     { .icl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } }, /* 300   300      0.0   */
0853     { .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300   350      1.3   */
0854     { .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } }, /* 350   350      0.0   */
0855 };
0856 
0857 static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr2 = {
0858     .entries = _adls_combo_phy_trans_edp_hbr2,
0859     .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr2),
0860 };
0861 
0862 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr3[] = {
0863                             /* NT mV Trans mV db    */
0864     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0865     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0866     { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350   700      6.0   */
0867     { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350   900      8.2   */
0868     { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0869     { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500   700      2.9   */
0870     { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500   900      5.1   */
0871     { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650   700      0.6   */
0872     { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900      3.5   */
0873     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0874 };
0875 
0876 static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr3 = {
0877     .entries = _adls_combo_phy_trans_edp_hbr3,
0878     .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr3),
0879 };
0880 
0881 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr[] = {
0882                             /* NT mV Trans mV db    */
0883     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0884     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0885     { .icl = { 0xC, 0x71, 0x31, 0x00, 0x0E } }, /* 350   700      6.0   */
0886     { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350   900      8.2   */
0887     { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0888     { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700      2.9   */
0889     { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900      5.1   */
0890     { .icl = { 0xC, 0x7C, 0x3C, 0x00, 0x03 } }, /* 650   700      0.6   */
0891     { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900      3.5   */
0892     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0893 };
0894 
0895 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr = {
0896     .entries = _adlp_combo_phy_trans_dp_hbr,
0897     .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr),
0898 };
0899 
0900 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_hbr3[] = {
0901                             /* NT mV Trans mV db    */
0902     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0903     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0904     { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0F } }, /* 350   700      6.0   */
0905     { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900      8.2   */
0906     { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0907     { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700      2.9   */
0908     { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500   900      5.1   */
0909     { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650   700      0.6   */
0910     { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600   900      3.5   */
0911     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0912 };
0913 
0914 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_edp_hbr2[] = {
0915                             /* NT mV Trans mV db    */
0916     { .icl = { 0x4, 0x50, 0x38, 0x00, 0x07 } }, /* 200   200      0.0   */
0917     { .icl = { 0x4, 0x58, 0x35, 0x00, 0x0A } }, /* 200   250      1.9   */
0918     { .icl = { 0x4, 0x60, 0x34, 0x00, 0x0B } }, /* 200   300      3.5   */
0919     { .icl = { 0x4, 0x6A, 0x32, 0x00, 0x0D } }, /* 200   350      4.9   */
0920     { .icl = { 0x4, 0x5E, 0x38, 0x00, 0x07 } }, /* 250   250      0.0   */
0921     { .icl = { 0x4, 0x61, 0x36, 0x00, 0x09 } }, /* 250   300      1.6   */
0922     { .icl = { 0x4, 0x6B, 0x34, 0x00, 0x0B } }, /* 250   350      2.9   */
0923     { .icl = { 0x4, 0x69, 0x39, 0x00, 0x06 } }, /* 300   300      0.0   */
0924     { .icl = { 0x4, 0x73, 0x37, 0x00, 0x08 } }, /* 300   350      1.3   */
0925     { .icl = { 0x4, 0x7A, 0x38, 0x00, 0x07 } }, /* 350   350      0.0   */
0926 };
0927 
0928 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
0929                             /* NT mV Trans mV db    */
0930     { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350      0.0   */
0931     { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500      3.1   */
0932     { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0f } }, /* 350   700      6.0   */
0933     { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900      8.2   */
0934     { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500      0.0   */
0935     { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700      2.9   */
0936     { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500   900      5.1   */
0937     { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650   700      0.6   */
0938     { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600   900      3.5   */
0939     { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900      0.0   */
0940 };
0941 
0942 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = {
0943     .entries = _adlp_combo_phy_trans_dp_hbr2_hbr3,
0944     .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3),
0945 };
0946 
0947 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = {
0948     .entries = _adlp_combo_phy_trans_dp_hbr2_edp_hbr3,
0949     .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_edp_hbr3),
0950 };
0951 
0952 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = {
0953     .entries = _adlp_combo_phy_trans_edp_hbr2,
0954     .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_edp_hbr2),
0955 };
0956 
0957 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr[] = {
0958                     /* VS   pre-emp Non-trans mV    Pre-emph dB */
0959     { .dkl = { 0x7, 0x0, 0x01 } },  /* 0    0   400mV       0 dB */
0960     { .dkl = { 0x5, 0x0, 0x06 } },  /* 0    1   400mV       3.5 dB */
0961     { .dkl = { 0x2, 0x0, 0x0B } },  /* 0    2   400mV       6 dB */
0962     { .dkl = { 0x0, 0x0, 0x17 } },  /* 0    3   400mV       9.5 dB */
0963     { .dkl = { 0x5, 0x0, 0x00 } },  /* 1    0   600mV       0 dB */
0964     { .dkl = { 0x2, 0x0, 0x08 } },  /* 1    1   600mV       3.5 dB */
0965     { .dkl = { 0x0, 0x0, 0x14 } },  /* 1    2   600mV       6 dB */
0966     { .dkl = { 0x2, 0x0, 0x00 } },  /* 2    0   800mV       0 dB */
0967     { .dkl = { 0x0, 0x0, 0x0B } },  /* 2    1   800mV       3.5 dB */
0968     { .dkl = { 0x0, 0x0, 0x00 } },  /* 3    0   1200mV      0 dB */
0969 };
0970 
0971 static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr = {
0972     .entries = _adlp_dkl_phy_trans_dp_hbr,
0973     .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr),
0974 };
0975 
0976 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr2_hbr3[] = {
0977                     /* VS   pre-emp Non-trans mV    Pre-emph dB */
0978     { .dkl = { 0x7, 0x0, 0x00 } },  /* 0    0   400mV       0 dB */
0979     { .dkl = { 0x5, 0x0, 0x04 } },  /* 0    1   400mV       3.5 dB */
0980     { .dkl = { 0x2, 0x0, 0x0A } },  /* 0    2   400mV       6 dB */
0981     { .dkl = { 0x0, 0x0, 0x18 } },  /* 0    3   400mV       9.5 dB */
0982     { .dkl = { 0x5, 0x0, 0x00 } },  /* 1    0   600mV       0 dB */
0983     { .dkl = { 0x2, 0x0, 0x06 } },  /* 1    1   600mV       3.5 dB */
0984     { .dkl = { 0x0, 0x0, 0x14 } },  /* 1    2   600mV       6 dB */
0985     { .dkl = { 0x2, 0x0, 0x00 } },  /* 2    0   800mV       0 dB */
0986     { .dkl = { 0x0, 0x0, 0x09 } },  /* 2    1   800mV       3.5 dB */
0987     { .dkl = { 0x0, 0x0, 0x00 } },  /* 3    0   1200mV      0 dB */
0988 };
0989 
0990 static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = {
0991     .entries = _adlp_dkl_phy_trans_dp_hbr2_hbr3,
0992     .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr2_hbr3),
0993 };
0994 
0995 static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = {
0996     { .snps = { 25, 0, 0 } },   /* VS 0, pre-emph 0 */
0997     { .snps = { 32, 0, 6 } },   /* VS 0, pre-emph 1 */
0998     { .snps = { 35, 0, 10 } },  /* VS 0, pre-emph 2 */
0999     { .snps = { 43, 0, 17 } },  /* VS 0, pre-emph 3 */
1000     { .snps = { 35, 0, 0 } },   /* VS 1, pre-emph 0 */
1001     { .snps = { 45, 0, 8 } },   /* VS 1, pre-emph 1 */
1002     { .snps = { 48, 0, 14 } },  /* VS 1, pre-emph 2 */
1003     { .snps = { 47, 0, 0 } },   /* VS 2, pre-emph 0 */
1004     { .snps = { 55, 0, 7 } },   /* VS 2, pre-emph 1 */
1005     { .snps = { 62, 0, 0 } },   /* VS 3, pre-emph 0 */
1006 };
1007 
1008 static const struct intel_ddi_buf_trans dg2_snps_trans = {
1009     .entries = _dg2_snps_trans,
1010     .num_entries = ARRAY_SIZE(_dg2_snps_trans),
1011     .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_trans) - 1,
1012 };
1013 
1014 static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = {
1015     { .snps = { 62, 0, 0 } },   /* preset 0 */
1016     { .snps = { 55, 0, 7 } },   /* preset 1 */
1017     { .snps = { 50, 0, 12 } },  /* preset 2 */
1018     { .snps = { 44, 0, 18 } },  /* preset 3 */
1019     { .snps = { 35, 0, 21 } },  /* preset 4 */
1020     { .snps = { 59, 3, 0 } },   /* preset 5 */
1021     { .snps = { 53, 3, 6 } },   /* preset 6 */
1022     { .snps = { 48, 3, 11 } },  /* preset 7 */
1023     { .snps = { 42, 5, 15 } },  /* preset 8 */
1024     { .snps = { 37, 5, 20 } },  /* preset 9 */
1025     { .snps = { 56, 6, 0 } },   /* preset 10 */
1026     { .snps = { 48, 7, 7 } },   /* preset 11 */
1027     { .snps = { 45, 7, 10 } },  /* preset 12 */
1028     { .snps = { 39, 8, 15 } },  /* preset 13 */
1029     { .snps = { 48, 14, 0 } },  /* preset 14 */
1030     { .snps = { 45, 4, 4 } },   /* preset 15 */
1031 };
1032 
1033 static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
1034     .entries = _dg2_snps_trans_uhbr,
1035     .num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
1036 };
1037 
1038 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
1039 {
1040     return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
1041 }
1042 
1043 static bool use_edp_hobl(struct intel_encoder *encoder)
1044 {
1045     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1046     struct intel_connector *connector = intel_dp->attached_connector;
1047 
1048     return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed;
1049 }
1050 
1051 static bool use_edp_low_vswing(struct intel_encoder *encoder)
1052 {
1053     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1054     struct intel_connector *connector = intel_dp->attached_connector;
1055 
1056     return connector->panel.vbt.edp.low_vswing;
1057 }
1058 
1059 static const struct intel_ddi_buf_trans *
1060 intel_get_buf_trans(const struct intel_ddi_buf_trans *trans, int *num_entries)
1061 {
1062     *num_entries = trans->num_entries;
1063     return trans;
1064 }
1065 
1066 static const struct intel_ddi_buf_trans *
1067 hsw_get_buf_trans(struct intel_encoder *encoder,
1068           const struct intel_crtc_state *crtc_state,
1069           int *n_entries)
1070 {
1071     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1072         return intel_get_buf_trans(&hsw_trans_fdi, n_entries);
1073     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1074         return intel_get_buf_trans(&hsw_trans_hdmi, n_entries);
1075     else
1076         return intel_get_buf_trans(&hsw_trans_dp, n_entries);
1077 }
1078 
1079 static const struct intel_ddi_buf_trans *
1080 bdw_get_buf_trans(struct intel_encoder *encoder,
1081           const struct intel_crtc_state *crtc_state,
1082           int *n_entries)
1083 {
1084     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1085         return intel_get_buf_trans(&bdw_trans_fdi, n_entries);
1086     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1087         return intel_get_buf_trans(&bdw_trans_hdmi, n_entries);
1088     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1089          use_edp_low_vswing(encoder))
1090         return intel_get_buf_trans(&bdw_trans_edp, n_entries);
1091     else
1092         return intel_get_buf_trans(&bdw_trans_dp, n_entries);
1093 }
1094 
1095 static int skl_buf_trans_num_entries(enum port port, int n_entries)
1096 {
1097     /* Only DDIA and DDIE can select the 10th register with DP */
1098     if (port == PORT_A || port == PORT_E)
1099         return min(n_entries, 10);
1100     else
1101         return min(n_entries, 9);
1102 }
1103 
1104 static const struct intel_ddi_buf_trans *
1105 _skl_get_buf_trans_dp(struct intel_encoder *encoder,
1106               const struct intel_ddi_buf_trans *trans,
1107               int *n_entries)
1108 {
1109     trans = intel_get_buf_trans(trans, n_entries);
1110     *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
1111     return trans;
1112 }
1113 
1114 static const struct intel_ddi_buf_trans *
1115 skl_y_get_buf_trans(struct intel_encoder *encoder,
1116             const struct intel_crtc_state *crtc_state,
1117             int *n_entries)
1118 {
1119     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1120         return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1121     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1122          use_edp_low_vswing(encoder))
1123         return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1124     else
1125         return _skl_get_buf_trans_dp(encoder, &skl_y_trans_dp, n_entries);
1126 }
1127 
1128 static const struct intel_ddi_buf_trans *
1129 skl_u_get_buf_trans(struct intel_encoder *encoder,
1130             const struct intel_crtc_state *crtc_state,
1131             int *n_entries)
1132 {
1133     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1134         return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1135     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1136          use_edp_low_vswing(encoder))
1137         return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1138     else
1139         return _skl_get_buf_trans_dp(encoder, &skl_u_trans_dp, n_entries);
1140 }
1141 
1142 static const struct intel_ddi_buf_trans *
1143 skl_get_buf_trans(struct intel_encoder *encoder,
1144           const struct intel_crtc_state *crtc_state,
1145           int *n_entries)
1146 {
1147     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1148         return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1149     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1150          use_edp_low_vswing(encoder))
1151         return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1152     else
1153         return _skl_get_buf_trans_dp(encoder, &skl_trans_dp, n_entries);
1154 }
1155 
1156 static const struct intel_ddi_buf_trans *
1157 kbl_y_get_buf_trans(struct intel_encoder *encoder,
1158             const struct intel_crtc_state *crtc_state,
1159             int *n_entries)
1160 {
1161     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1162         return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1163     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1164          use_edp_low_vswing(encoder))
1165         return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1166     else
1167         return _skl_get_buf_trans_dp(encoder, &kbl_y_trans_dp, n_entries);
1168 }
1169 
1170 static const struct intel_ddi_buf_trans *
1171 kbl_u_get_buf_trans(struct intel_encoder *encoder,
1172             const struct intel_crtc_state *crtc_state,
1173             int *n_entries)
1174 {
1175     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1176         return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1177     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1178          use_edp_low_vswing(encoder))
1179         return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1180     else
1181         return _skl_get_buf_trans_dp(encoder, &kbl_u_trans_dp, n_entries);
1182 }
1183 
1184 static const struct intel_ddi_buf_trans *
1185 kbl_get_buf_trans(struct intel_encoder *encoder,
1186           const struct intel_crtc_state *crtc_state,
1187           int *n_entries)
1188 {
1189     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1190         return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1191     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1192          use_edp_low_vswing(encoder))
1193         return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1194     else
1195         return _skl_get_buf_trans_dp(encoder, &kbl_trans_dp, n_entries);
1196 }
1197 
1198 static const struct intel_ddi_buf_trans *
1199 bxt_get_buf_trans(struct intel_encoder *encoder,
1200           const struct intel_crtc_state *crtc_state,
1201           int *n_entries)
1202 {
1203     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1204         return intel_get_buf_trans(&bxt_trans_hdmi, n_entries);
1205     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1206          use_edp_low_vswing(encoder))
1207         return intel_get_buf_trans(&bxt_trans_edp, n_entries);
1208     else
1209         return intel_get_buf_trans(&bxt_trans_dp, n_entries);
1210 }
1211 
1212 static const struct intel_ddi_buf_trans *
1213 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1214                const struct intel_crtc_state *crtc_state,
1215                int *n_entries)
1216 {
1217     return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1218                    n_entries);
1219 }
1220 
1221 static const struct intel_ddi_buf_trans *
1222 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1223                 const struct intel_crtc_state *crtc_state,
1224                 int *n_entries)
1225 {
1226     if (crtc_state->port_clock > 540000) {
1227         return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1228                        n_entries);
1229     } else if (use_edp_low_vswing(encoder)) {
1230         return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1231                        n_entries);
1232     }
1233 
1234     return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1235 }
1236 
1237 static const struct intel_ddi_buf_trans *
1238 icl_get_combo_buf_trans(struct intel_encoder *encoder,
1239             const struct intel_crtc_state *crtc_state,
1240             int *n_entries)
1241 {
1242     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1243         return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1244     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1245         return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1246     else
1247         return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1248 }
1249 
1250 static const struct intel_ddi_buf_trans *
1251 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1252             const struct intel_crtc_state *crtc_state,
1253             int *n_entries)
1254 {
1255     if (crtc_state->port_clock > 270000) {
1256         return intel_get_buf_trans(&icl_mg_phy_trans_hbr2_hbr3,
1257                        n_entries);
1258     } else {
1259         return intel_get_buf_trans(&icl_mg_phy_trans_rbr_hbr,
1260                        n_entries);
1261     }
1262 }
1263 
1264 static const struct intel_ddi_buf_trans *
1265 icl_get_mg_buf_trans(struct intel_encoder *encoder,
1266              const struct intel_crtc_state *crtc_state,
1267              int *n_entries)
1268 {
1269     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1270         return intel_get_buf_trans(&icl_mg_phy_trans_hdmi, n_entries);
1271     else
1272         return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1273 }
1274 
1275 static const struct intel_ddi_buf_trans *
1276 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1277                 const struct intel_crtc_state *crtc_state,
1278                 int *n_entries)
1279 {
1280     if (crtc_state->port_clock > 270000)
1281         return intel_get_buf_trans(&ehl_combo_phy_trans_edp_hbr2, n_entries);
1282     else
1283         return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries);
1284 }
1285 
1286 static const struct intel_ddi_buf_trans *
1287 ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1288             const struct intel_crtc_state *crtc_state,
1289             int *n_entries)
1290 {
1291     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1292         return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1293     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1294          use_edp_low_vswing(encoder))
1295         return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1296     else
1297         return intel_get_buf_trans(&ehl_combo_phy_trans_dp, n_entries);
1298 }
1299 
1300 static const struct intel_ddi_buf_trans *
1301 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1302                 const struct intel_crtc_state *crtc_state,
1303                 int *n_entries)
1304 {
1305     if (crtc_state->port_clock > 270000)
1306         return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr2, n_entries);
1307     else
1308         return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr, n_entries);
1309 }
1310 
1311 static const struct intel_ddi_buf_trans *
1312 jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1313             const struct intel_crtc_state *crtc_state,
1314             int *n_entries)
1315 {
1316     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1317         return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1318     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1319          use_edp_low_vswing(encoder))
1320         return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1321     else
1322         return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries);
1323 }
1324 
1325 static const struct intel_ddi_buf_trans *
1326 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1327                const struct intel_crtc_state *crtc_state,
1328                int *n_entries)
1329 {
1330     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1331 
1332     if (crtc_state->port_clock > 270000) {
1333         if (IS_TGL_UY(dev_priv)) {
1334             return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
1335                            n_entries);
1336         } else {
1337             return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr2,
1338                            n_entries);
1339         }
1340     } else {
1341         return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr,
1342                        n_entries);
1343     }
1344 }
1345 
1346 static const struct intel_ddi_buf_trans *
1347 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1348                 const struct intel_crtc_state *crtc_state,
1349                 int *n_entries)
1350 {
1351     if (crtc_state->port_clock > 540000) {
1352         return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1353                        n_entries);
1354     } else if (use_edp_hobl(encoder)) {
1355         return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1356                        n_entries);
1357     } else if (use_edp_low_vswing(encoder)) {
1358         return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1359                        n_entries);
1360     }
1361 
1362     return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1363 }
1364 
1365 static const struct intel_ddi_buf_trans *
1366 tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1367             const struct intel_crtc_state *crtc_state,
1368             int *n_entries)
1369 {
1370     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1371         return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1372     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1373         return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1374     else
1375         return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1376 }
1377 
1378 static const struct intel_ddi_buf_trans *
1379 dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1380                const struct intel_crtc_state *crtc_state,
1381                int *n_entries)
1382 {
1383     if (crtc_state->port_clock > 270000)
1384         return intel_get_buf_trans(&dg1_combo_phy_trans_dp_hbr2_hbr3,
1385                        n_entries);
1386     else
1387         return intel_get_buf_trans(&dg1_combo_phy_trans_dp_rbr_hbr,
1388                        n_entries);
1389 }
1390 
1391 static const struct intel_ddi_buf_trans *
1392 dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1393                 const struct intel_crtc_state *crtc_state,
1394                 int *n_entries)
1395 {
1396     if (crtc_state->port_clock > 540000)
1397         return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1398                        n_entries);
1399     else if (use_edp_hobl(encoder))
1400         return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1401                        n_entries);
1402     else if (use_edp_low_vswing(encoder))
1403         return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1404                        n_entries);
1405     else
1406         return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1407 }
1408 
1409 static const struct intel_ddi_buf_trans *
1410 dg1_get_combo_buf_trans(struct intel_encoder *encoder,
1411             const struct intel_crtc_state *crtc_state,
1412             int *n_entries)
1413 {
1414     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1415         return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1416     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1417         return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1418     else
1419         return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1420 }
1421 
1422 static const struct intel_ddi_buf_trans *
1423 rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1424                const struct intel_crtc_state *crtc_state,
1425                int *n_entries)
1426 {
1427     if (crtc_state->port_clock > 270000)
1428         return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1429     else
1430         return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr, n_entries);
1431 }
1432 
1433 static const struct intel_ddi_buf_trans *
1434 rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1435                 const struct intel_crtc_state *crtc_state,
1436                 int *n_entries)
1437 {
1438     if (crtc_state->port_clock > 540000) {
1439         return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1440                        n_entries);
1441     } else if (use_edp_hobl(encoder)) {
1442         return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1443                        n_entries);
1444     } else if (use_edp_low_vswing(encoder)) {
1445         return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1446                        n_entries);
1447     }
1448 
1449     return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1450 }
1451 
1452 static const struct intel_ddi_buf_trans *
1453 rkl_get_combo_buf_trans(struct intel_encoder *encoder,
1454             const struct intel_crtc_state *crtc_state,
1455             int *n_entries)
1456 {
1457     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1458         return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1459     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1460         return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1461     else
1462         return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1463 }
1464 
1465 static const struct intel_ddi_buf_trans *
1466 adls_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1467                 const struct intel_crtc_state *crtc_state,
1468                 int *n_entries)
1469 {
1470     if (crtc_state->port_clock > 270000)
1471         return intel_get_buf_trans(&adls_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1472     else
1473         return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, n_entries);
1474 }
1475 
1476 static const struct intel_ddi_buf_trans *
1477 adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1478                  const struct intel_crtc_state *crtc_state,
1479                  int *n_entries)
1480 {
1481     if (crtc_state->port_clock > 540000)
1482         return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr3, n_entries);
1483     else if (use_edp_hobl(encoder))
1484         return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries);
1485     else if (use_edp_low_vswing(encoder))
1486         return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr2, n_entries);
1487     else
1488         return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1489 }
1490 
1491 static const struct intel_ddi_buf_trans *
1492 adls_get_combo_buf_trans(struct intel_encoder *encoder,
1493              const struct intel_crtc_state *crtc_state,
1494              int *n_entries)
1495 {
1496     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1497         return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1498     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1499         return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1500     else
1501         return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1502 }
1503 
1504 static const struct intel_ddi_buf_trans *
1505 adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1506                 const struct intel_crtc_state *crtc_state,
1507                 int *n_entries)
1508 {
1509     if (crtc_state->port_clock > 270000)
1510         return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1511     else
1512         return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr, n_entries);
1513 }
1514 
1515 static const struct intel_ddi_buf_trans *
1516 adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1517                  const struct intel_crtc_state *crtc_state,
1518                  int *n_entries)
1519 {
1520     if (crtc_state->port_clock > 540000) {
1521         return intel_get_buf_trans(&adlp_combo_phy_trans_edp_hbr3,
1522                        n_entries);
1523     } else if (use_edp_hobl(encoder)) {
1524         return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1525                        n_entries);
1526     } else if (use_edp_low_vswing(encoder)) {
1527         return intel_get_buf_trans(&adlp_combo_phy_trans_edp_up_to_hbr2,
1528                        n_entries);
1529     }
1530 
1531     return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1532 }
1533 
1534 static const struct intel_ddi_buf_trans *
1535 adlp_get_combo_buf_trans(struct intel_encoder *encoder,
1536              const struct intel_crtc_state *crtc_state,
1537              int *n_entries)
1538 {
1539     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1540         return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1541     else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1542         return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1543     else
1544         return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1545 }
1546 
1547 static const struct intel_ddi_buf_trans *
1548 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1549              const struct intel_crtc_state *crtc_state,
1550              int *n_entries)
1551 {
1552     if (crtc_state->port_clock > 270000) {
1553         return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr2,
1554                        n_entries);
1555     } else {
1556         return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr,
1557                        n_entries);
1558     }
1559 }
1560 
1561 static const struct intel_ddi_buf_trans *
1562 tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1563               const struct intel_crtc_state *crtc_state,
1564               int *n_entries)
1565 {
1566     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1567         return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1568     else
1569         return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1570 }
1571 
1572 static const struct intel_ddi_buf_trans *
1573 adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1574               const struct intel_crtc_state *crtc_state,
1575               int *n_entries)
1576 {
1577     if (crtc_state->port_clock > 270000) {
1578         return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr2_hbr3,
1579                        n_entries);
1580     } else {
1581         return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr,
1582                        n_entries);
1583     }
1584 }
1585 
1586 static const struct intel_ddi_buf_trans *
1587 adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
1588                const struct intel_crtc_state *crtc_state,
1589                int *n_entries)
1590 {
1591     if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1592         return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1593     else
1594         return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1595 }
1596 
1597 static const struct intel_ddi_buf_trans *
1598 dg2_get_snps_buf_trans(struct intel_encoder *encoder,
1599                const struct intel_crtc_state *crtc_state,
1600                int *n_entries)
1601 {
1602     if (intel_crtc_has_dp_encoder(crtc_state) &&
1603         intel_dp_is_uhbr(crtc_state))
1604         return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
1605     else
1606         return intel_get_buf_trans(&dg2_snps_trans, n_entries);
1607 }
1608 
1609 void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
1610 {
1611     struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1612     enum phy phy = intel_port_to_phy(i915, encoder->port);
1613 
1614     if (IS_DG2(i915)) {
1615         encoder->get_buf_trans = dg2_get_snps_buf_trans;
1616     } else if (IS_ALDERLAKE_P(i915)) {
1617         if (intel_phy_is_combo(i915, phy))
1618             encoder->get_buf_trans = adlp_get_combo_buf_trans;
1619         else
1620             encoder->get_buf_trans = adlp_get_dkl_buf_trans;
1621     } else if (IS_ALDERLAKE_S(i915)) {
1622         encoder->get_buf_trans = adls_get_combo_buf_trans;
1623     } else if (IS_ROCKETLAKE(i915)) {
1624         encoder->get_buf_trans = rkl_get_combo_buf_trans;
1625     } else if (IS_DG1(i915)) {
1626         encoder->get_buf_trans = dg1_get_combo_buf_trans;
1627     } else if (DISPLAY_VER(i915) >= 12) {
1628         if (intel_phy_is_combo(i915, phy))
1629             encoder->get_buf_trans = tgl_get_combo_buf_trans;
1630         else
1631             encoder->get_buf_trans = tgl_get_dkl_buf_trans;
1632     } else if (DISPLAY_VER(i915) == 11) {
1633         if (IS_PLATFORM(i915, INTEL_JASPERLAKE))
1634             encoder->get_buf_trans = jsl_get_combo_buf_trans;
1635         else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
1636             encoder->get_buf_trans = ehl_get_combo_buf_trans;
1637         else if (intel_phy_is_combo(i915, phy))
1638             encoder->get_buf_trans = icl_get_combo_buf_trans;
1639         else
1640             encoder->get_buf_trans = icl_get_mg_buf_trans;
1641     } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1642         encoder->get_buf_trans = bxt_get_buf_trans;
1643     } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
1644         encoder->get_buf_trans = kbl_y_get_buf_trans;
1645     } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
1646         encoder->get_buf_trans = kbl_u_get_buf_trans;
1647     } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
1648         encoder->get_buf_trans = kbl_get_buf_trans;
1649     } else if (IS_SKL_ULX(i915)) {
1650         encoder->get_buf_trans = skl_y_get_buf_trans;
1651     } else if (IS_SKL_ULT(i915)) {
1652         encoder->get_buf_trans = skl_u_get_buf_trans;
1653     } else if (IS_SKYLAKE(i915)) {
1654         encoder->get_buf_trans = skl_get_buf_trans;
1655     } else if (IS_BROADWELL(i915)) {
1656         encoder->get_buf_trans = bdw_get_buf_trans;
1657     } else if (IS_HASWELL(i915)) {
1658         encoder->get_buf_trans = hsw_get_buf_trans;
1659     } else {
1660         MISSING_CASE(INTEL_INFO(i915)->platform);
1661     }
1662 }
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