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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005 
0006 #include "i915_drv.h"
0007 #include "intel_crtc_state_dump.h"
0008 #include "intel_display_types.h"
0009 #include "intel_hdmi.h"
0010 #include "intel_vrr.h"
0011 
0012 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
0013                     const struct drm_display_mode *mode)
0014 {
0015     drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
0016             "type: 0x%x flags: 0x%x\n",
0017             mode->crtc_clock,
0018             mode->crtc_hdisplay, mode->crtc_hsync_start,
0019             mode->crtc_hsync_end, mode->crtc_htotal,
0020             mode->crtc_vdisplay, mode->crtc_vsync_start,
0021             mode->crtc_vsync_end, mode->crtc_vtotal,
0022             mode->type, mode->flags);
0023 }
0024 
0025 static void
0026 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
0027               const char *id, unsigned int lane_count,
0028               const struct intel_link_m_n *m_n)
0029 {
0030     struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
0031 
0032     drm_dbg_kms(&i915->drm,
0033             "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
0034             id, lane_count,
0035             m_n->data_m, m_n->data_n,
0036             m_n->link_m, m_n->link_n, m_n->tu);
0037 }
0038 
0039 static void
0040 intel_dump_infoframe(struct drm_i915_private *i915,
0041              const union hdmi_infoframe *frame)
0042 {
0043     if (!drm_debug_enabled(DRM_UT_KMS))
0044         return;
0045 
0046     hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame);
0047 }
0048 
0049 static void
0050 intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
0051               const struct drm_dp_vsc_sdp *vsc)
0052 {
0053     if (!drm_debug_enabled(DRM_UT_KMS))
0054         return;
0055 
0056     drm_dp_vsc_sdp_log(KERN_DEBUG, i915->drm.dev, vsc);
0057 }
0058 
0059 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
0060 
0061 static const char * const output_type_str[] = {
0062     OUTPUT_TYPE(UNUSED),
0063     OUTPUT_TYPE(ANALOG),
0064     OUTPUT_TYPE(DVO),
0065     OUTPUT_TYPE(SDVO),
0066     OUTPUT_TYPE(LVDS),
0067     OUTPUT_TYPE(TVOUT),
0068     OUTPUT_TYPE(HDMI),
0069     OUTPUT_TYPE(DP),
0070     OUTPUT_TYPE(EDP),
0071     OUTPUT_TYPE(DSI),
0072     OUTPUT_TYPE(DDI),
0073     OUTPUT_TYPE(DP_MST),
0074 };
0075 
0076 #undef OUTPUT_TYPE
0077 
0078 static void snprintf_output_types(char *buf, size_t len,
0079                   unsigned int output_types)
0080 {
0081     char *str = buf;
0082     int i;
0083 
0084     str[0] = '\0';
0085 
0086     for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
0087         int r;
0088 
0089         if ((output_types & BIT(i)) == 0)
0090             continue;
0091 
0092         r = snprintf(str, len, "%s%s",
0093                  str != buf ? "," : "", output_type_str[i]);
0094         if (r >= len)
0095             break;
0096         str += r;
0097         len -= r;
0098 
0099         output_types &= ~BIT(i);
0100     }
0101 
0102     WARN_ON_ONCE(output_types != 0);
0103 }
0104 
0105 static const char * const output_format_str[] = {
0106     [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
0107     [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
0108     [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
0109 };
0110 
0111 static const char *output_formats(enum intel_output_format format)
0112 {
0113     if (format >= ARRAY_SIZE(output_format_str))
0114         return "invalid";
0115     return output_format_str[format];
0116 }
0117 
0118 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
0119 {
0120     struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
0121     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0122     const struct drm_framebuffer *fb = plane_state->hw.fb;
0123 
0124     if (!fb) {
0125         drm_dbg_kms(&i915->drm,
0126                 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
0127                 plane->base.base.id, plane->base.name,
0128                 str_yes_no(plane_state->uapi.visible));
0129         return;
0130     }
0131 
0132     drm_dbg_kms(&i915->drm,
0133             "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
0134             plane->base.base.id, plane->base.name,
0135             fb->base.id, fb->width, fb->height, &fb->format->format,
0136             fb->modifier, str_yes_no(plane_state->uapi.visible));
0137     drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
0138             plane_state->hw.rotation, plane_state->scaler_id);
0139     if (plane_state->uapi.visible)
0140         drm_dbg_kms(&i915->drm,
0141                 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
0142                 DRM_RECT_FP_ARG(&plane_state->uapi.src),
0143                 DRM_RECT_ARG(&plane_state->uapi.dst));
0144 }
0145 
0146 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
0147                struct intel_atomic_state *state,
0148                const char *context)
0149 {
0150     struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
0151     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0152     const struct intel_plane_state *plane_state;
0153     struct intel_plane *plane;
0154     char buf[64];
0155     int i;
0156 
0157     drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] enable: %s [%s]\n",
0158             crtc->base.base.id, crtc->base.name,
0159             str_yes_no(pipe_config->hw.enable), context);
0160 
0161     if (!pipe_config->hw.enable)
0162         goto dump_planes;
0163 
0164     snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
0165     drm_dbg_kms(&i915->drm,
0166             "active: %s, output_types: %s (0x%x), output format: %s\n",
0167             str_yes_no(pipe_config->hw.active),
0168             buf, pipe_config->output_types,
0169             output_formats(pipe_config->output_format));
0170 
0171     drm_dbg_kms(&i915->drm,
0172             "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
0173             transcoder_name(pipe_config->cpu_transcoder),
0174             pipe_config->pipe_bpp, pipe_config->dither);
0175 
0176     drm_dbg_kms(&i915->drm, "MST master transcoder: %s\n",
0177             transcoder_name(pipe_config->mst_master_transcoder));
0178 
0179     drm_dbg_kms(&i915->drm,
0180             "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
0181             transcoder_name(pipe_config->master_transcoder),
0182             pipe_config->sync_mode_slaves_mask);
0183 
0184     drm_dbg_kms(&i915->drm, "bigjoiner: %s, pipes: 0x%x\n",
0185             intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
0186             intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
0187             pipe_config->bigjoiner_pipes);
0188 
0189     drm_dbg_kms(&i915->drm, "splitter: %s, link count %d, overlap %d\n",
0190             str_enabled_disabled(pipe_config->splitter.enable),
0191             pipe_config->splitter.link_count,
0192             pipe_config->splitter.pixel_overlap);
0193 
0194     if (pipe_config->has_pch_encoder)
0195         intel_dump_m_n_config(pipe_config, "fdi",
0196                       pipe_config->fdi_lanes,
0197                       &pipe_config->fdi_m_n);
0198 
0199     if (intel_crtc_has_dp_encoder(pipe_config)) {
0200         intel_dump_m_n_config(pipe_config, "dp m_n",
0201                       pipe_config->lane_count,
0202                       &pipe_config->dp_m_n);
0203         intel_dump_m_n_config(pipe_config, "dp m2_n2",
0204                       pipe_config->lane_count,
0205                       &pipe_config->dp_m2_n2);
0206     }
0207 
0208     drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",
0209             pipe_config->framestart_delay, pipe_config->msa_timing_delay);
0210 
0211     drm_dbg_kms(&i915->drm,
0212             "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
0213             pipe_config->has_audio, pipe_config->has_infoframe,
0214             pipe_config->infoframes.enable);
0215 
0216     if (pipe_config->infoframes.enable &
0217         intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
0218         drm_dbg_kms(&i915->drm, "GCP: 0x%x\n",
0219                 pipe_config->infoframes.gcp);
0220     if (pipe_config->infoframes.enable &
0221         intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
0222         intel_dump_infoframe(i915, &pipe_config->infoframes.avi);
0223     if (pipe_config->infoframes.enable &
0224         intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
0225         intel_dump_infoframe(i915, &pipe_config->infoframes.spd);
0226     if (pipe_config->infoframes.enable &
0227         intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
0228         intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi);
0229     if (pipe_config->infoframes.enable &
0230         intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
0231         intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
0232     if (pipe_config->infoframes.enable &
0233         intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
0234         intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
0235     if (pipe_config->infoframes.enable &
0236         intel_hdmi_infoframe_enable(DP_SDP_VSC))
0237         intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc);
0238 
0239     drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
0240             str_yes_no(pipe_config->vrr.enable),
0241             pipe_config->vrr.vmin, pipe_config->vrr.vmax,
0242             pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
0243             pipe_config->vrr.flipline,
0244             intel_vrr_vmin_vblank_start(pipe_config),
0245             intel_vrr_vmax_vblank_start(pipe_config));
0246 
0247     drm_dbg_kms(&i915->drm, "requested mode: " DRM_MODE_FMT "\n",
0248             DRM_MODE_ARG(&pipe_config->hw.mode));
0249     drm_dbg_kms(&i915->drm, "adjusted mode: " DRM_MODE_FMT "\n",
0250             DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
0251     intel_dump_crtc_timings(i915, &pipe_config->hw.adjusted_mode);
0252     drm_dbg_kms(&i915->drm, "pipe mode: " DRM_MODE_FMT "\n",
0253             DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
0254     intel_dump_crtc_timings(i915, &pipe_config->hw.pipe_mode);
0255     drm_dbg_kms(&i915->drm,
0256             "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
0257             pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
0258             pipe_config->pixel_rate);
0259 
0260     drm_dbg_kms(&i915->drm, "linetime: %d, ips linetime: %d\n",
0261             pipe_config->linetime, pipe_config->ips_linetime);
0262 
0263     if (DISPLAY_VER(i915) >= 9)
0264         drm_dbg_kms(&i915->drm,
0265                 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
0266                 crtc->num_scalers,
0267                 pipe_config->scaler_state.scaler_users,
0268                 pipe_config->scaler_state.scaler_id);
0269 
0270     if (HAS_GMCH(i915))
0271         drm_dbg_kms(&i915->drm,
0272                 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
0273                 pipe_config->gmch_pfit.control,
0274                 pipe_config->gmch_pfit.pgm_ratios,
0275                 pipe_config->gmch_pfit.lvds_border_bits);
0276     else
0277         drm_dbg_kms(&i915->drm,
0278                 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
0279                 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
0280                 str_enabled_disabled(pipe_config->pch_pfit.enabled),
0281                 str_yes_no(pipe_config->pch_pfit.force_thru));
0282 
0283     drm_dbg_kms(&i915->drm, "ips: %i, double wide: %i, drrs: %i\n",
0284             pipe_config->ips_enabled, pipe_config->double_wide,
0285             pipe_config->has_drrs);
0286 
0287     intel_dpll_dump_hw_state(i915, &pipe_config->dpll_hw_state);
0288 
0289     if (IS_CHERRYVIEW(i915))
0290         drm_dbg_kms(&i915->drm,
0291                 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
0292                 pipe_config->cgm_mode, pipe_config->gamma_mode,
0293                 pipe_config->gamma_enable, pipe_config->csc_enable);
0294     else
0295         drm_dbg_kms(&i915->drm,
0296                 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
0297                 pipe_config->csc_mode, pipe_config->gamma_mode,
0298                 pipe_config->gamma_enable, pipe_config->csc_enable);
0299 
0300     drm_dbg_kms(&i915->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
0301             pipe_config->hw.degamma_lut ?
0302             drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
0303             pipe_config->hw.gamma_lut ?
0304             drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
0305 
0306 dump_planes:
0307     if (!state)
0308         return;
0309 
0310     for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
0311         if (plane->pipe == crtc->pipe)
0312             intel_dump_plane_state(plane_state);
0313     }
0314 }
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