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0001 /*
0002  * Copyright © 2006-2007 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0021  * DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors:
0024  *  Eric Anholt <eric@anholt.net>
0025  */
0026 
0027 #include <linux/dmi.h>
0028 #include <linux/i2c.h>
0029 #include <linux/slab.h>
0030 
0031 #include <drm/drm_atomic_helper.h>
0032 #include <drm/drm_crtc.h>
0033 #include <drm/drm_edid.h>
0034 #include <drm/drm_probe_helper.h>
0035 
0036 #include "i915_drv.h"
0037 #include "intel_connector.h"
0038 #include "intel_crt.h"
0039 #include "intel_crtc.h"
0040 #include "intel_ddi.h"
0041 #include "intel_ddi_buf_trans.h"
0042 #include "intel_de.h"
0043 #include "intel_display_types.h"
0044 #include "intel_fdi.h"
0045 #include "intel_fifo_underrun.h"
0046 #include "intel_gmbus.h"
0047 #include "intel_hotplug.h"
0048 #include "intel_pch_display.h"
0049 
0050 /* Here's the desired hotplug mode */
0051 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |        \
0052                ADPA_CRT_HOTPLUG_WARMUP_10MS |       \
0053                ADPA_CRT_HOTPLUG_SAMPLE_4S |         \
0054                ADPA_CRT_HOTPLUG_VOLTAGE_50 |        \
0055                ADPA_CRT_HOTPLUG_VOLREF_325MV |      \
0056                ADPA_CRT_HOTPLUG_ENABLE)
0057 
0058 struct intel_crt {
0059     struct intel_encoder base;
0060     /* DPMS state is stored in the connector, which we need in the
0061      * encoder's enable/disable callbacks */
0062     struct intel_connector *connector;
0063     bool force_hotplug_required;
0064     i915_reg_t adpa_reg;
0065 };
0066 
0067 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
0068 {
0069     return container_of(encoder, struct intel_crt, base);
0070 }
0071 
0072 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
0073 {
0074     return intel_encoder_to_crt(intel_attached_encoder(connector));
0075 }
0076 
0077 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
0078                 i915_reg_t adpa_reg, enum pipe *pipe)
0079 {
0080     u32 val;
0081 
0082     val = intel_de_read(dev_priv, adpa_reg);
0083 
0084     /* asserts want to know the pipe even if the port is disabled */
0085     if (HAS_PCH_CPT(dev_priv))
0086         *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
0087     else
0088         *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
0089 
0090     return val & ADPA_DAC_ENABLE;
0091 }
0092 
0093 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
0094                    enum pipe *pipe)
0095 {
0096     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0097     struct intel_crt *crt = intel_encoder_to_crt(encoder);
0098     intel_wakeref_t wakeref;
0099     bool ret;
0100 
0101     wakeref = intel_display_power_get_if_enabled(dev_priv,
0102                              encoder->power_domain);
0103     if (!wakeref)
0104         return false;
0105 
0106     ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
0107 
0108     intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
0109 
0110     return ret;
0111 }
0112 
0113 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
0114 {
0115     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0116     struct intel_crt *crt = intel_encoder_to_crt(encoder);
0117     u32 tmp, flags = 0;
0118 
0119     tmp = intel_de_read(dev_priv, crt->adpa_reg);
0120 
0121     if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
0122         flags |= DRM_MODE_FLAG_PHSYNC;
0123     else
0124         flags |= DRM_MODE_FLAG_NHSYNC;
0125 
0126     if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
0127         flags |= DRM_MODE_FLAG_PVSYNC;
0128     else
0129         flags |= DRM_MODE_FLAG_NVSYNC;
0130 
0131     return flags;
0132 }
0133 
0134 static void intel_crt_get_config(struct intel_encoder *encoder,
0135                  struct intel_crtc_state *pipe_config)
0136 {
0137     pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
0138 
0139     pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
0140 
0141     pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
0142 }
0143 
0144 static void hsw_crt_get_config(struct intel_encoder *encoder,
0145                    struct intel_crtc_state *pipe_config)
0146 {
0147     lpt_pch_get_config(pipe_config);
0148 
0149     hsw_ddi_get_config(encoder, pipe_config);
0150 
0151     pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
0152                           DRM_MODE_FLAG_NHSYNC |
0153                           DRM_MODE_FLAG_PVSYNC |
0154                           DRM_MODE_FLAG_NVSYNC);
0155     pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
0156 }
0157 
0158 /* Note: The caller is required to filter out dpms modes not supported by the
0159  * platform. */
0160 static void intel_crt_set_dpms(struct intel_encoder *encoder,
0161                    const struct intel_crtc_state *crtc_state,
0162                    int mode)
0163 {
0164     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0165     struct intel_crt *crt = intel_encoder_to_crt(encoder);
0166     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0167     const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
0168     u32 adpa;
0169 
0170     if (DISPLAY_VER(dev_priv) >= 5)
0171         adpa = ADPA_HOTPLUG_BITS;
0172     else
0173         adpa = 0;
0174 
0175     if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
0176         adpa |= ADPA_HSYNC_ACTIVE_HIGH;
0177     if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
0178         adpa |= ADPA_VSYNC_ACTIVE_HIGH;
0179 
0180     /* For CPT allow 3 pipe config, for others just use A or B */
0181     if (HAS_PCH_LPT(dev_priv))
0182         ; /* Those bits don't exist here */
0183     else if (HAS_PCH_CPT(dev_priv))
0184         adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
0185     else
0186         adpa |= ADPA_PIPE_SEL(crtc->pipe);
0187 
0188     if (!HAS_PCH_SPLIT(dev_priv))
0189         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
0190 
0191     switch (mode) {
0192     case DRM_MODE_DPMS_ON:
0193         adpa |= ADPA_DAC_ENABLE;
0194         break;
0195     case DRM_MODE_DPMS_STANDBY:
0196         adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
0197         break;
0198     case DRM_MODE_DPMS_SUSPEND:
0199         adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
0200         break;
0201     case DRM_MODE_DPMS_OFF:
0202         adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
0203         break;
0204     }
0205 
0206     intel_de_write(dev_priv, crt->adpa_reg, adpa);
0207 }
0208 
0209 static void intel_disable_crt(struct intel_atomic_state *state,
0210                   struct intel_encoder *encoder,
0211                   const struct intel_crtc_state *old_crtc_state,
0212                   const struct drm_connector_state *old_conn_state)
0213 {
0214     intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
0215 }
0216 
0217 static void pch_disable_crt(struct intel_atomic_state *state,
0218                 struct intel_encoder *encoder,
0219                 const struct intel_crtc_state *old_crtc_state,
0220                 const struct drm_connector_state *old_conn_state)
0221 {
0222 }
0223 
0224 static void pch_post_disable_crt(struct intel_atomic_state *state,
0225                  struct intel_encoder *encoder,
0226                  const struct intel_crtc_state *old_crtc_state,
0227                  const struct drm_connector_state *old_conn_state)
0228 {
0229     intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
0230 }
0231 
0232 static void hsw_disable_crt(struct intel_atomic_state *state,
0233                 struct intel_encoder *encoder,
0234                 const struct intel_crtc_state *old_crtc_state,
0235                 const struct drm_connector_state *old_conn_state)
0236 {
0237     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0238 
0239     drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
0240 
0241     intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
0242 }
0243 
0244 static void hsw_post_disable_crt(struct intel_atomic_state *state,
0245                  struct intel_encoder *encoder,
0246                  const struct intel_crtc_state *old_crtc_state,
0247                  const struct drm_connector_state *old_conn_state)
0248 {
0249     struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
0250     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0251 
0252     intel_crtc_vblank_off(old_crtc_state);
0253 
0254     intel_disable_transcoder(old_crtc_state);
0255 
0256     intel_ddi_disable_transcoder_func(old_crtc_state);
0257 
0258     ilk_pfit_disable(old_crtc_state);
0259 
0260     intel_ddi_disable_pipe_clock(old_crtc_state);
0261 
0262     pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
0263 
0264     lpt_pch_disable(state, crtc);
0265 
0266     hsw_fdi_disable(encoder);
0267 
0268     drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
0269 
0270     intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
0271 }
0272 
0273 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
0274                    struct intel_encoder *encoder,
0275                    const struct intel_crtc_state *crtc_state,
0276                    const struct drm_connector_state *conn_state)
0277 {
0278     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0279 
0280     drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
0281 
0282     intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
0283 }
0284 
0285 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
0286                    struct intel_encoder *encoder,
0287                    const struct intel_crtc_state *crtc_state,
0288                    const struct drm_connector_state *conn_state)
0289 {
0290     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0291     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0292     enum pipe pipe = crtc->pipe;
0293 
0294     drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
0295 
0296     intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0297 
0298     hsw_fdi_link_train(encoder, crtc_state);
0299 
0300     intel_ddi_enable_pipe_clock(encoder, crtc_state);
0301 }
0302 
0303 static void hsw_enable_crt(struct intel_atomic_state *state,
0304                struct intel_encoder *encoder,
0305                const struct intel_crtc_state *crtc_state,
0306                const struct drm_connector_state *conn_state)
0307 {
0308     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0309     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0310     enum pipe pipe = crtc->pipe;
0311 
0312     drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
0313 
0314     intel_ddi_enable_transcoder_func(encoder, crtc_state);
0315 
0316     intel_enable_transcoder(crtc_state);
0317 
0318     lpt_pch_enable(state, crtc);
0319 
0320     intel_crtc_vblank_on(crtc_state);
0321 
0322     intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
0323 
0324     intel_crtc_wait_for_next_vblank(crtc);
0325     intel_crtc_wait_for_next_vblank(crtc);
0326     intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
0327     intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
0328 }
0329 
0330 static void intel_enable_crt(struct intel_atomic_state *state,
0331                  struct intel_encoder *encoder,
0332                  const struct intel_crtc_state *crtc_state,
0333                  const struct drm_connector_state *conn_state)
0334 {
0335     intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
0336 }
0337 
0338 static enum drm_mode_status
0339 intel_crt_mode_valid(struct drm_connector *connector,
0340              struct drm_display_mode *mode)
0341 {
0342     struct drm_device *dev = connector->dev;
0343     struct drm_i915_private *dev_priv = to_i915(dev);
0344     int max_dotclk = dev_priv->max_dotclk_freq;
0345     int max_clock;
0346 
0347     if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
0348         return MODE_NO_DBLESCAN;
0349 
0350     if (mode->clock < 25000)
0351         return MODE_CLOCK_LOW;
0352 
0353     if (HAS_PCH_LPT(dev_priv))
0354         max_clock = 180000;
0355     else if (IS_VALLEYVIEW(dev_priv))
0356         /*
0357          * 270 MHz due to current DPLL limits,
0358          * DAC limit supposedly 355 MHz.
0359          */
0360         max_clock = 270000;
0361     else if (IS_DISPLAY_VER(dev_priv, 3, 4))
0362         max_clock = 400000;
0363     else
0364         max_clock = 350000;
0365     if (mode->clock > max_clock)
0366         return MODE_CLOCK_HIGH;
0367 
0368     if (mode->clock > max_dotclk)
0369         return MODE_CLOCK_HIGH;
0370 
0371     /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
0372     if (HAS_PCH_LPT(dev_priv) &&
0373         ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
0374         return MODE_CLOCK_HIGH;
0375 
0376     /* HSW/BDW FDI limited to 4k */
0377     if (mode->hdisplay > 4096)
0378         return MODE_H_ILLEGAL;
0379 
0380     return MODE_OK;
0381 }
0382 
0383 static int intel_crt_compute_config(struct intel_encoder *encoder,
0384                     struct intel_crtc_state *pipe_config,
0385                     struct drm_connector_state *conn_state)
0386 {
0387     struct drm_display_mode *adjusted_mode =
0388         &pipe_config->hw.adjusted_mode;
0389 
0390     if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
0391         return -EINVAL;
0392 
0393     pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
0394 
0395     return 0;
0396 }
0397 
0398 static int pch_crt_compute_config(struct intel_encoder *encoder,
0399                   struct intel_crtc_state *pipe_config,
0400                   struct drm_connector_state *conn_state)
0401 {
0402     struct drm_display_mode *adjusted_mode =
0403         &pipe_config->hw.adjusted_mode;
0404 
0405     if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
0406         return -EINVAL;
0407 
0408     pipe_config->has_pch_encoder = true;
0409     pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
0410 
0411     return 0;
0412 }
0413 
0414 static int hsw_crt_compute_config(struct intel_encoder *encoder,
0415                   struct intel_crtc_state *pipe_config,
0416                   struct drm_connector_state *conn_state)
0417 {
0418     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0419     struct drm_display_mode *adjusted_mode =
0420         &pipe_config->hw.adjusted_mode;
0421 
0422     if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
0423         return -EINVAL;
0424 
0425     /* HSW/BDW FDI limited to 4k */
0426     if (adjusted_mode->crtc_hdisplay > 4096 ||
0427         adjusted_mode->crtc_hblank_start > 4096)
0428         return -EINVAL;
0429 
0430     pipe_config->has_pch_encoder = true;
0431     pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
0432 
0433     /* LPT FDI RX only supports 8bpc. */
0434     if (HAS_PCH_LPT(dev_priv)) {
0435         if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
0436             drm_dbg_kms(&dev_priv->drm,
0437                     "LPT only supports 24bpp\n");
0438             return -EINVAL;
0439         }
0440 
0441         pipe_config->pipe_bpp = 24;
0442     }
0443 
0444     /* FDI must always be 2.7 GHz */
0445     pipe_config->port_clock = 135000 * 2;
0446 
0447     return 0;
0448 }
0449 
0450 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
0451 {
0452     struct drm_device *dev = connector->dev;
0453     struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
0454     struct drm_i915_private *dev_priv = to_i915(dev);
0455     u32 adpa;
0456     bool ret;
0457 
0458     /* The first time through, trigger an explicit detection cycle */
0459     if (crt->force_hotplug_required) {
0460         bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
0461         u32 save_adpa;
0462 
0463         crt->force_hotplug_required = false;
0464 
0465         save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
0466         drm_dbg_kms(&dev_priv->drm,
0467                 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
0468 
0469         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
0470         if (turn_off_dac)
0471             adpa &= ~ADPA_DAC_ENABLE;
0472 
0473         intel_de_write(dev_priv, crt->adpa_reg, adpa);
0474 
0475         if (intel_de_wait_for_clear(dev_priv,
0476                         crt->adpa_reg,
0477                         ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
0478                         1000))
0479             drm_dbg_kms(&dev_priv->drm,
0480                     "timed out waiting for FORCE_TRIGGER");
0481 
0482         if (turn_off_dac) {
0483             intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
0484             intel_de_posting_read(dev_priv, crt->adpa_reg);
0485         }
0486     }
0487 
0488     /* Check the status to see if both blue and green are on now */
0489     adpa = intel_de_read(dev_priv, crt->adpa_reg);
0490     if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
0491         ret = true;
0492     else
0493         ret = false;
0494     drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
0495             adpa, ret);
0496 
0497     return ret;
0498 }
0499 
0500 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
0501 {
0502     struct drm_device *dev = connector->dev;
0503     struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
0504     struct drm_i915_private *dev_priv = to_i915(dev);
0505     bool reenable_hpd;
0506     u32 adpa;
0507     bool ret;
0508     u32 save_adpa;
0509 
0510     /*
0511      * Doing a force trigger causes a hpd interrupt to get sent, which can
0512      * get us stuck in a loop if we're polling:
0513      *  - We enable power wells and reset the ADPA
0514      *  - output_poll_exec does force probe on VGA, triggering a hpd
0515      *  - HPD handler waits for poll to unlock dev->mode_config.mutex
0516      *  - output_poll_exec shuts off the ADPA, unlocks
0517      *    dev->mode_config.mutex
0518      *  - HPD handler runs, resets ADPA and brings us back to the start
0519      *
0520      * Just disable HPD interrupts here to prevent this
0521      */
0522     reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
0523 
0524     save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
0525     drm_dbg_kms(&dev_priv->drm,
0526             "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
0527 
0528     adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
0529 
0530     intel_de_write(dev_priv, crt->adpa_reg, adpa);
0531 
0532     if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
0533                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
0534         drm_dbg_kms(&dev_priv->drm,
0535                 "timed out waiting for FORCE_TRIGGER");
0536         intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
0537     }
0538 
0539     /* Check the status to see if both blue and green are on now */
0540     adpa = intel_de_read(dev_priv, crt->adpa_reg);
0541     if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
0542         ret = true;
0543     else
0544         ret = false;
0545 
0546     drm_dbg_kms(&dev_priv->drm,
0547             "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
0548 
0549     if (reenable_hpd)
0550         intel_hpd_enable(dev_priv, crt->base.hpd_pin);
0551 
0552     return ret;
0553 }
0554 
0555 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
0556 {
0557     struct drm_device *dev = connector->dev;
0558     struct drm_i915_private *dev_priv = to_i915(dev);
0559     u32 stat;
0560     bool ret = false;
0561     int i, tries = 0;
0562 
0563     if (HAS_PCH_SPLIT(dev_priv))
0564         return ilk_crt_detect_hotplug(connector);
0565 
0566     if (IS_VALLEYVIEW(dev_priv))
0567         return valleyview_crt_detect_hotplug(connector);
0568 
0569     /*
0570      * On 4 series desktop, CRT detect sequence need to be done twice
0571      * to get a reliable result.
0572      */
0573 
0574     if (IS_G45(dev_priv))
0575         tries = 2;
0576     else
0577         tries = 1;
0578 
0579     for (i = 0; i < tries ; i++) {
0580         /* turn on the FORCE_DETECT */
0581         i915_hotplug_interrupt_update(dev_priv,
0582                           CRT_HOTPLUG_FORCE_DETECT,
0583                           CRT_HOTPLUG_FORCE_DETECT);
0584         /* wait for FORCE_DETECT to go off */
0585         if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
0586                         CRT_HOTPLUG_FORCE_DETECT, 1000))
0587             drm_dbg_kms(&dev_priv->drm,
0588                     "timed out waiting for FORCE_DETECT to go off");
0589     }
0590 
0591     stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
0592     if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
0593         ret = true;
0594 
0595     /* clear the interrupt we just generated, if any */
0596     intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
0597 
0598     i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
0599 
0600     return ret;
0601 }
0602 
0603 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
0604                 struct i2c_adapter *i2c)
0605 {
0606     struct edid *edid;
0607 
0608     edid = drm_get_edid(connector, i2c);
0609 
0610     if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
0611         drm_dbg_kms(connector->dev,
0612                 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
0613         intel_gmbus_force_bit(i2c, true);
0614         edid = drm_get_edid(connector, i2c);
0615         intel_gmbus_force_bit(i2c, false);
0616     }
0617 
0618     return edid;
0619 }
0620 
0621 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
0622 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
0623                 struct i2c_adapter *adapter)
0624 {
0625     struct edid *edid;
0626     int ret;
0627 
0628     edid = intel_crt_get_edid(connector, adapter);
0629     if (!edid)
0630         return 0;
0631 
0632     ret = intel_connector_update_modes(connector, edid);
0633     kfree(edid);
0634 
0635     return ret;
0636 }
0637 
0638 static bool intel_crt_detect_ddc(struct drm_connector *connector)
0639 {
0640     struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
0641     struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
0642     struct edid *edid;
0643     struct i2c_adapter *i2c;
0644     bool ret = false;
0645 
0646     BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
0647 
0648     i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
0649     edid = intel_crt_get_edid(connector, i2c);
0650 
0651     if (edid) {
0652         bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
0653 
0654         /*
0655          * This may be a DVI-I connector with a shared DDC
0656          * link between analog and digital outputs, so we
0657          * have to check the EDID input spec of the attached device.
0658          */
0659         if (!is_digital) {
0660             drm_dbg_kms(&dev_priv->drm,
0661                     "CRT detected via DDC:0x50 [EDID]\n");
0662             ret = true;
0663         } else {
0664             drm_dbg_kms(&dev_priv->drm,
0665                     "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
0666         }
0667     } else {
0668         drm_dbg_kms(&dev_priv->drm,
0669                 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
0670     }
0671 
0672     kfree(edid);
0673 
0674     return ret;
0675 }
0676 
0677 static enum drm_connector_status
0678 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
0679 {
0680     struct drm_device *dev = crt->base.base.dev;
0681     struct drm_i915_private *dev_priv = to_i915(dev);
0682     struct intel_uncore *uncore = &dev_priv->uncore;
0683     u32 save_bclrpat;
0684     u32 save_vtotal;
0685     u32 vtotal, vactive;
0686     u32 vsample;
0687     u32 vblank, vblank_start, vblank_end;
0688     u32 dsl;
0689     i915_reg_t bclrpat_reg, vtotal_reg,
0690         vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
0691     u8 st00;
0692     enum drm_connector_status status;
0693 
0694     drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
0695 
0696     bclrpat_reg = BCLRPAT(pipe);
0697     vtotal_reg = VTOTAL(pipe);
0698     vblank_reg = VBLANK(pipe);
0699     vsync_reg = VSYNC(pipe);
0700     pipeconf_reg = PIPECONF(pipe);
0701     pipe_dsl_reg = PIPEDSL(pipe);
0702 
0703     save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
0704     save_vtotal = intel_uncore_read(uncore, vtotal_reg);
0705     vblank = intel_uncore_read(uncore, vblank_reg);
0706 
0707     vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
0708     vactive = (save_vtotal & 0x7ff) + 1;
0709 
0710     vblank_start = (vblank & 0xfff) + 1;
0711     vblank_end = ((vblank >> 16) & 0xfff) + 1;
0712 
0713     /* Set the border color to purple. */
0714     intel_uncore_write(uncore, bclrpat_reg, 0x500050);
0715 
0716     if (DISPLAY_VER(dev_priv) != 2) {
0717         u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
0718         intel_uncore_write(uncore,
0719                    pipeconf_reg,
0720                    pipeconf | PIPECONF_FORCE_BORDER);
0721         intel_uncore_posting_read(uncore, pipeconf_reg);
0722         /* Wait for next Vblank to substitue
0723          * border color for Color info */
0724         intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
0725         st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
0726         status = ((st00 & (1 << 4)) != 0) ?
0727             connector_status_connected :
0728             connector_status_disconnected;
0729 
0730         intel_uncore_write(uncore, pipeconf_reg, pipeconf);
0731     } else {
0732         bool restore_vblank = false;
0733         int count, detect;
0734 
0735         /*
0736         * If there isn't any border, add some.
0737         * Yes, this will flicker
0738         */
0739         if (vblank_start <= vactive && vblank_end >= vtotal) {
0740             u32 vsync = intel_de_read(dev_priv, vsync_reg);
0741             u32 vsync_start = (vsync & 0xffff) + 1;
0742 
0743             vblank_start = vsync_start;
0744             intel_uncore_write(uncore,
0745                        vblank_reg,
0746                        (vblank_start - 1) |
0747                        ((vblank_end - 1) << 16));
0748             restore_vblank = true;
0749         }
0750         /* sample in the vertical border, selecting the larger one */
0751         if (vblank_start - vactive >= vtotal - vblank_end)
0752             vsample = (vblank_start + vactive) >> 1;
0753         else
0754             vsample = (vtotal + vblank_end) >> 1;
0755 
0756         /*
0757          * Wait for the border to be displayed
0758          */
0759         while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
0760             ;
0761         while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
0762                vsample)
0763             ;
0764         /*
0765          * Watch ST00 for an entire scanline
0766          */
0767         detect = 0;
0768         count = 0;
0769         do {
0770             count++;
0771             /* Read the ST00 VGA status register */
0772             st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
0773             if (st00 & (1 << 4))
0774                 detect++;
0775         } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
0776 
0777         /* restore vblank if necessary */
0778         if (restore_vblank)
0779             intel_uncore_write(uncore, vblank_reg, vblank);
0780         /*
0781          * If more than 3/4 of the scanline detected a monitor,
0782          * then it is assumed to be present. This works even on i830,
0783          * where there isn't any way to force the border color across
0784          * the screen
0785          */
0786         status = detect * 4 > count * 3 ?
0787              connector_status_connected :
0788              connector_status_disconnected;
0789     }
0790 
0791     /* Restore previous settings */
0792     intel_uncore_write(uncore, bclrpat_reg, save_bclrpat);
0793 
0794     return status;
0795 }
0796 
0797 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
0798 {
0799     DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
0800     return 1;
0801 }
0802 
0803 static const struct dmi_system_id intel_spurious_crt_detect[] = {
0804     {
0805         .callback = intel_spurious_crt_detect_dmi_callback,
0806         .ident = "ACER ZGB",
0807         .matches = {
0808             DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
0809             DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
0810         },
0811     },
0812     {
0813         .callback = intel_spurious_crt_detect_dmi_callback,
0814         .ident = "Intel DZ77BH-55K",
0815         .matches = {
0816             DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
0817             DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
0818         },
0819     },
0820     { }
0821 };
0822 
0823 static int
0824 intel_crt_detect(struct drm_connector *connector,
0825          struct drm_modeset_acquire_ctx *ctx,
0826          bool force)
0827 {
0828     struct drm_i915_private *dev_priv = to_i915(connector->dev);
0829     struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
0830     struct intel_encoder *intel_encoder = &crt->base;
0831     intel_wakeref_t wakeref;
0832     int status, ret;
0833     struct intel_load_detect_pipe tmp;
0834 
0835     drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
0836             connector->base.id, connector->name,
0837             force);
0838 
0839     if (!INTEL_DISPLAY_ENABLED(dev_priv))
0840         return connector_status_disconnected;
0841 
0842     if (dev_priv->params.load_detect_test) {
0843         wakeref = intel_display_power_get(dev_priv,
0844                           intel_encoder->power_domain);
0845         goto load_detect;
0846     }
0847 
0848     /* Skip machines without VGA that falsely report hotplug events */
0849     if (dmi_check_system(intel_spurious_crt_detect))
0850         return connector_status_disconnected;
0851 
0852     wakeref = intel_display_power_get(dev_priv,
0853                       intel_encoder->power_domain);
0854 
0855     if (I915_HAS_HOTPLUG(dev_priv)) {
0856         /* We can not rely on the HPD pin always being correctly wired
0857          * up, for example many KVM do not pass it through, and so
0858          * only trust an assertion that the monitor is connected.
0859          */
0860         if (intel_crt_detect_hotplug(connector)) {
0861             drm_dbg_kms(&dev_priv->drm,
0862                     "CRT detected via hotplug\n");
0863             status = connector_status_connected;
0864             goto out;
0865         } else
0866             drm_dbg_kms(&dev_priv->drm,
0867                     "CRT not detected via hotplug\n");
0868     }
0869 
0870     if (intel_crt_detect_ddc(connector)) {
0871         status = connector_status_connected;
0872         goto out;
0873     }
0874 
0875     /* Load detection is broken on HPD capable machines. Whoever wants a
0876      * broken monitor (without edid) to work behind a broken kvm (that fails
0877      * to have the right resistors for HP detection) needs to fix this up.
0878      * For now just bail out. */
0879     if (I915_HAS_HOTPLUG(dev_priv)) {
0880         status = connector_status_disconnected;
0881         goto out;
0882     }
0883 
0884 load_detect:
0885     if (!force) {
0886         status = connector->status;
0887         goto out;
0888     }
0889 
0890     /* for pre-945g platforms use load detect */
0891     ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
0892     if (ret > 0) {
0893         if (intel_crt_detect_ddc(connector))
0894             status = connector_status_connected;
0895         else if (DISPLAY_VER(dev_priv) < 4)
0896             status = intel_crt_load_detect(crt,
0897                 to_intel_crtc(connector->state->crtc)->pipe);
0898         else if (dev_priv->params.load_detect_test)
0899             status = connector_status_disconnected;
0900         else
0901             status = connector_status_unknown;
0902         intel_release_load_detect_pipe(connector, &tmp, ctx);
0903     } else if (ret == 0) {
0904         status = connector_status_unknown;
0905     } else {
0906         status = ret;
0907     }
0908 
0909 out:
0910     intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
0911 
0912     /*
0913      * Make sure the refs for power wells enabled during detect are
0914      * dropped to avoid a new detect cycle triggered by HPD polling.
0915      */
0916     intel_display_power_flush_work(dev_priv);
0917 
0918     return status;
0919 }
0920 
0921 static int intel_crt_get_modes(struct drm_connector *connector)
0922 {
0923     struct drm_device *dev = connector->dev;
0924     struct drm_i915_private *dev_priv = to_i915(dev);
0925     struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
0926     struct intel_encoder *intel_encoder = &crt->base;
0927     intel_wakeref_t wakeref;
0928     struct i2c_adapter *i2c;
0929     int ret;
0930 
0931     wakeref = intel_display_power_get(dev_priv,
0932                       intel_encoder->power_domain);
0933 
0934     i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
0935     ret = intel_crt_ddc_get_modes(connector, i2c);
0936     if (ret || !IS_G4X(dev_priv))
0937         goto out;
0938 
0939     /* Try to probe digital port for output in DVI-I -> VGA mode. */
0940     i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
0941     ret = intel_crt_ddc_get_modes(connector, i2c);
0942 
0943 out:
0944     intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
0945 
0946     return ret;
0947 }
0948 
0949 void intel_crt_reset(struct drm_encoder *encoder)
0950 {
0951     struct drm_i915_private *dev_priv = to_i915(encoder->dev);
0952     struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
0953 
0954     if (DISPLAY_VER(dev_priv) >= 5) {
0955         u32 adpa;
0956 
0957         adpa = intel_de_read(dev_priv, crt->adpa_reg);
0958         adpa &= ~ADPA_CRT_HOTPLUG_MASK;
0959         adpa |= ADPA_HOTPLUG_BITS;
0960         intel_de_write(dev_priv, crt->adpa_reg, adpa);
0961         intel_de_posting_read(dev_priv, crt->adpa_reg);
0962 
0963         drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
0964         crt->force_hotplug_required = true;
0965     }
0966 
0967 }
0968 
0969 /*
0970  * Routines for controlling stuff on the analog port
0971  */
0972 
0973 static const struct drm_connector_funcs intel_crt_connector_funcs = {
0974     .fill_modes = drm_helper_probe_single_connector_modes,
0975     .late_register = intel_connector_register,
0976     .early_unregister = intel_connector_unregister,
0977     .destroy = intel_connector_destroy,
0978     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
0979     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
0980 };
0981 
0982 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
0983     .detect_ctx = intel_crt_detect,
0984     .mode_valid = intel_crt_mode_valid,
0985     .get_modes = intel_crt_get_modes,
0986 };
0987 
0988 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
0989     .reset = intel_crt_reset,
0990     .destroy = intel_encoder_destroy,
0991 };
0992 
0993 void intel_crt_init(struct drm_i915_private *dev_priv)
0994 {
0995     struct drm_connector *connector;
0996     struct intel_crt *crt;
0997     struct intel_connector *intel_connector;
0998     i915_reg_t adpa_reg;
0999     u32 adpa;
1000 
1001     if (HAS_PCH_SPLIT(dev_priv))
1002         adpa_reg = PCH_ADPA;
1003     else if (IS_VALLEYVIEW(dev_priv))
1004         adpa_reg = VLV_ADPA;
1005     else
1006         adpa_reg = ADPA;
1007 
1008     adpa = intel_de_read(dev_priv, adpa_reg);
1009     if ((adpa & ADPA_DAC_ENABLE) == 0) {
1010         /*
1011          * On some machines (some IVB at least) CRT can be
1012          * fused off, but there's no known fuse bit to
1013          * indicate that. On these machine the ADPA register
1014          * works normally, except the DAC enable bit won't
1015          * take. So the only way to tell is attempt to enable
1016          * it and see what happens.
1017          */
1018         intel_de_write(dev_priv, adpa_reg,
1019                    adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1020         if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1021             return;
1022         intel_de_write(dev_priv, adpa_reg, adpa);
1023     }
1024 
1025     crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1026     if (!crt)
1027         return;
1028 
1029     intel_connector = intel_connector_alloc();
1030     if (!intel_connector) {
1031         kfree(crt);
1032         return;
1033     }
1034 
1035     connector = &intel_connector->base;
1036     crt->connector = intel_connector;
1037     drm_connector_init(&dev_priv->drm, &intel_connector->base,
1038                &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1039 
1040     drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1041              DRM_MODE_ENCODER_DAC, "CRT");
1042 
1043     intel_connector_attach_encoder(intel_connector, &crt->base);
1044 
1045     crt->base.type = INTEL_OUTPUT_ANALOG;
1046     crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
1047     if (IS_I830(dev_priv))
1048         crt->base.pipe_mask = BIT(PIPE_A);
1049     else
1050         crt->base.pipe_mask = ~0;
1051 
1052     if (DISPLAY_VER(dev_priv) == 2)
1053         connector->interlace_allowed = 0;
1054     else
1055         connector->interlace_allowed = 1;
1056     connector->doublescan_allowed = 0;
1057 
1058     crt->adpa_reg = adpa_reg;
1059 
1060     crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1061 
1062     if (I915_HAS_HOTPLUG(dev_priv) &&
1063         !dmi_check_system(intel_spurious_crt_detect)) {
1064         crt->base.hpd_pin = HPD_CRT;
1065         crt->base.hotplug = intel_encoder_hotplug;
1066         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1067     } else {
1068         intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1069     }
1070 
1071     if (HAS_DDI(dev_priv)) {
1072         crt->base.port = PORT_E;
1073         crt->base.get_config = hsw_crt_get_config;
1074         crt->base.get_hw_state = intel_ddi_get_hw_state;
1075         crt->base.compute_config = hsw_crt_compute_config;
1076         crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1077         crt->base.pre_enable = hsw_pre_enable_crt;
1078         crt->base.enable = hsw_enable_crt;
1079         crt->base.disable = hsw_disable_crt;
1080         crt->base.post_disable = hsw_post_disable_crt;
1081         crt->base.enable_clock = hsw_ddi_enable_clock;
1082         crt->base.disable_clock = hsw_ddi_disable_clock;
1083         crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1084 
1085         intel_ddi_buf_trans_init(&crt->base);
1086     } else {
1087         if (HAS_PCH_SPLIT(dev_priv)) {
1088             crt->base.compute_config = pch_crt_compute_config;
1089             crt->base.disable = pch_disable_crt;
1090             crt->base.post_disable = pch_post_disable_crt;
1091         } else {
1092             crt->base.compute_config = intel_crt_compute_config;
1093             crt->base.disable = intel_disable_crt;
1094         }
1095         crt->base.port = PORT_NONE;
1096         crt->base.get_config = intel_crt_get_config;
1097         crt->base.get_hw_state = intel_crt_get_hw_state;
1098         crt->base.enable = intel_enable_crt;
1099     }
1100     intel_connector->get_hw_state = intel_connector_get_hw_state;
1101 
1102     drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1103 
1104     /*
1105      * TODO: find a proper way to discover whether we need to set the the
1106      * polarity and link reversal bits or not, instead of relying on the
1107      * BIOS.
1108      */
1109     if (HAS_PCH_LPT(dev_priv)) {
1110         u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1111                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1112 
1113         dev_priv->fdi_rx_config = intel_de_read(dev_priv,
1114                             FDI_RX_CTL(PIPE_A)) & fdi_config;
1115     }
1116 
1117     intel_crt_reset(&crt->base.base);
1118 }
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