i915/display/intel_combo_phy_regs.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2022 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_COMBO_PHY_REGS__
0007 #define __INTEL_COMBO_PHY_REGS__
0008
0009 #include "i915_reg_defs.h"
0010
0011 #define _ICL_COMBOPHY_A             0x162000
0012 #define _ICL_COMBOPHY_B             0x6C000
0013 #define _EHL_COMBOPHY_C             0x160000
0014 #define _RKL_COMBOPHY_D             0x161000
0015 #define _ADL_COMBOPHY_E             0x16B000
0016
0017 #define _ICL_COMBOPHY(phy)          _PICK(phy, _ICL_COMBOPHY_A, \
0018                               _ICL_COMBOPHY_B, \
0019                               _EHL_COMBOPHY_C, \
0020                               _RKL_COMBOPHY_D, \
0021                               _ADL_COMBOPHY_E)
0022
0023 /* ICL Port CL_DW registers */
0024 #define _ICL_PORT_CL_DW(dw, phy)        (_ICL_COMBOPHY(phy) + \
0025                          4 * (dw))
0026
0027 #define ICL_PORT_CL_DW5(phy)            _MMIO(_ICL_PORT_CL_DW(5, phy))
0028 #define   CL_POWER_DOWN_ENABLE          (1 << 4)
0029 #define   SUS_CLOCK_CONFIG          (3 << 0)
0030
0031 #define ICL_PORT_CL_DW10(phy)           _MMIO(_ICL_PORT_CL_DW(10, phy))
0032 #define  PG_SEQ_DELAY_OVERRIDE_MASK     (3 << 25)
0033 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT        25
0034 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE       (1 << 24)
0035 #define  PWR_UP_ALL_LANES           (0x0 << 4)
0036 #define  PWR_DOWN_LN_3_2_1          (0xe << 4)
0037 #define  PWR_DOWN_LN_3_2            (0xc << 4)
0038 #define  PWR_DOWN_LN_3              (0x8 << 4)
0039 #define  PWR_DOWN_LN_2_1_0          (0x7 << 4)
0040 #define  PWR_DOWN_LN_1_0            (0x3 << 4)
0041 #define  PWR_DOWN_LN_3_1            (0xa << 4)
0042 #define  PWR_DOWN_LN_3_1_0          (0xb << 4)
0043 #define  PWR_DOWN_LN_MASK           (0xf << 4)
0044 #define  PWR_DOWN_LN_SHIFT          4
0045 #define  EDP4K2K_MODE_OVRD_EN           (1 << 3)
0046 #define  EDP4K2K_MODE_OVRD_OPTIMIZED        (1 << 2)
0047
0048 #define ICL_PORT_CL_DW12(phy)           _MMIO(_ICL_PORT_CL_DW(12, phy))
0049 #define   ICL_LANE_ENABLE_AUX           (1 << 0)
0050
0051 /* ICL Port COMP_DW registers */
0052 #define _ICL_PORT_COMP              0x100
0053 #define _ICL_PORT_COMP_DW(dw, phy)      (_ICL_COMBOPHY(phy) + \
0054                          _ICL_PORT_COMP + 4 * (dw))
0055
0056 #define ICL_PORT_COMP_DW0(phy)          _MMIO(_ICL_PORT_COMP_DW(0, phy))
0057 #define   COMP_INIT             (1 << 31)
0058
0059 #define ICL_PORT_COMP_DW1(phy)          _MMIO(_ICL_PORT_COMP_DW(1, phy))
0060
0061 #define ICL_PORT_COMP_DW3(phy)          _MMIO(_ICL_PORT_COMP_DW(3, phy))
0062 #define   PROCESS_INFO_DOT_0            (0 << 26)
0063 #define   PROCESS_INFO_DOT_1            (1 << 26)
0064 #define   PROCESS_INFO_DOT_4            (2 << 26)
0065 #define   PROCESS_INFO_MASK         (7 << 26)
0066 #define   PROCESS_INFO_SHIFT            26
0067 #define   VOLTAGE_INFO_0_85V            (0 << 24)
0068 #define   VOLTAGE_INFO_0_95V            (1 << 24)
0069 #define   VOLTAGE_INFO_1_05V            (2 << 24)
0070 #define   VOLTAGE_INFO_MASK         (3 << 24)
0071 #define   VOLTAGE_INFO_SHIFT            24
0072
0073 #define ICL_PORT_COMP_DW8(phy)          _MMIO(_ICL_PORT_COMP_DW(8, phy))
0074 #define   IREFGEN               (1 << 24)
0075
0076 #define ICL_PORT_COMP_DW9(phy)          _MMIO(_ICL_PORT_COMP_DW(9, phy))
0077
0078 #define ICL_PORT_COMP_DW10(phy)         _MMIO(_ICL_PORT_COMP_DW(10, phy))
0079
0080 /* ICL Port PCS registers */
0081 #define _ICL_PORT_PCS_AUX           0x300
0082 #define _ICL_PORT_PCS_GRP           0x600
0083 #define _ICL_PORT_PCS_LN(ln)            (0x800 + (ln) * 0x100)
0084 #define _ICL_PORT_PCS_DW_AUX(dw, phy)       (_ICL_COMBOPHY(phy) + \
0085                          _ICL_PORT_PCS_AUX + 4 * (dw))
0086 #define _ICL_PORT_PCS_DW_GRP(dw, phy)       (_ICL_COMBOPHY(phy) + \
0087                          _ICL_PORT_PCS_GRP + 4 * (dw))
0088 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy)     (_ICL_COMBOPHY(phy) + \
0089                           _ICL_PORT_PCS_LN(ln) + 4 * (dw))
0090 #define ICL_PORT_PCS_DW1_AUX(phy)       _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
0091 #define ICL_PORT_PCS_DW1_GRP(phy)       _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
0092 #define ICL_PORT_PCS_DW1_LN(ln, phy)        _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
0093 #define   DCC_MODE_SELECT_MASK          (0x3 << 20)
0094 #define   DCC_MODE_SELECT_CONTINUOSLY       (0x3 << 20)
0095 #define   COMMON_KEEPER_EN          (1 << 26)
0096 #define   LATENCY_OPTIM_MASK            (0x3 << 2)
0097 #define   LATENCY_OPTIM_VAL(x)          ((x) << 2)
0098
0099 /* ICL Port TX registers */
0100 #define _ICL_PORT_TX_AUX            0x380
0101 #define _ICL_PORT_TX_GRP            0x680
0102 #define _ICL_PORT_TX_LN(ln)         (0x880 + (ln) * 0x100)
0103
0104 #define _ICL_PORT_TX_DW_AUX(dw, phy)        (_ICL_COMBOPHY(phy) + \
0105                          _ICL_PORT_TX_AUX + 4 * (dw))
0106 #define _ICL_PORT_TX_DW_GRP(dw, phy)        (_ICL_COMBOPHY(phy) + \
0107                          _ICL_PORT_TX_GRP + 4 * (dw))
0108 #define _ICL_PORT_TX_DW_LN(dw, ln, phy)     (_ICL_COMBOPHY(phy) + \
0109                           _ICL_PORT_TX_LN(ln) + 4 * (dw))
0110
0111 #define ICL_PORT_TX_DW2_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
0112 #define ICL_PORT_TX_DW2_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
0113 #define ICL_PORT_TX_DW2_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
0114 #define   SWING_SEL_UPPER(x)            (((x) >> 3) << 15)
0115 #define   SWING_SEL_UPPER_MASK          (1 << 15)
0116 #define   SWING_SEL_LOWER(x)            (((x) & 0x7) << 11)
0117 #define   SWING_SEL_LOWER_MASK          (0x7 << 11)
0118 #define   FRC_LATENCY_OPTIM_MASK        (0x7 << 8)
0119 #define   FRC_LATENCY_OPTIM_VAL(x)      ((x) << 8)
0120 #define   RCOMP_SCALAR(x)           ((x) << 0)
0121 #define   RCOMP_SCALAR_MASK         (0xFF << 0)
0122
0123 #define ICL_PORT_TX_DW4_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
0124 #define ICL_PORT_TX_DW4_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
0125 #define ICL_PORT_TX_DW4_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
0126 #define   LOADGEN_SELECT            (1 << 31)
0127 #define   POST_CURSOR_1(x)          ((x) << 12)
0128 #define   POST_CURSOR_1_MASK            (0x3F << 12)
0129 #define   POST_CURSOR_2(x)          ((x) << 6)
0130 #define   POST_CURSOR_2_MASK            (0x3F << 6)
0131 #define   CURSOR_COEFF(x)           ((x) << 0)
0132 #define   CURSOR_COEFF_MASK         (0x3F << 0)
0133
0134 #define ICL_PORT_TX_DW5_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
0135 #define ICL_PORT_TX_DW5_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
0136 #define ICL_PORT_TX_DW5_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
0137 #define   TX_TRAINING_EN            (1 << 31)
0138 #define   TAP2_DISABLE              (1 << 30)
0139 #define   TAP3_DISABLE              (1 << 29)
0140 #define   SCALING_MODE_SEL(x)           ((x) << 18)
0141 #define   SCALING_MODE_SEL_MASK         (0x7 << 18)
0142 #define   RTERM_SELECT(x)           ((x) << 3)
0143 #define   RTERM_SELECT_MASK         (0x7 << 3)
0144
0145 #define ICL_PORT_TX_DW7_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
0146 #define ICL_PORT_TX_DW7_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
0147 #define ICL_PORT_TX_DW7_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
0148 #define   N_SCALAR(x)               ((x) << 24)
0149 #define   N_SCALAR_MASK             (0x7F << 24)
0150
0151 #define ICL_PORT_TX_DW8_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
0152 #define ICL_PORT_TX_DW8_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
0153 #define ICL_PORT_TX_DW8_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
0154 #define   ICL_PORT_TX_DW8_ODCC_CLK_SEL      REG_BIT(31)
0155 #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
0156 #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
0157
0158 #define _ICL_DPHY_CHKN_REG          0x194
0159 #define ICL_DPHY_CHKN(port)         _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
0160 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP  REG_BIT(7)
0161
0162 #endif /* __INTEL_COMBO_PHY_REGS__ */