i915/display/intel_cdclk.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_CDCLK_H__
0007 #define __INTEL_CDCLK_H__
0008
0009 #include <linux/types.h>
0010
0011 #include "intel_display.h"
0012 #include "intel_global_state.h"
0013
0014 struct drm_i915_private;
0015 struct intel_atomic_state;
0016 struct intel_crtc_state;
0017
0018 struct intel_cdclk_config {
0019     unsigned int cdclk, vco, ref, bypass;
0020     u8 voltage_level;
0021 };
0022
0023 struct intel_cdclk_state {
0024     struct intel_global_state base;
0025
0026     /*
0027      * Logical configuration of cdclk (used for all scaling,
0028      * watermark, etc. calculations and checks). This is
0029      * computed as if all enabled crtcs were active.
0030      */
0031     struct intel_cdclk_config logical;
0032
0033     /*
0034      * Actual configuration of cdclk, can be different from the
0035      * logical configuration only when all crtc's are DPMS off.
0036      */
0037     struct intel_cdclk_config actual;
0038
0039     /* minimum acceptable cdclk to satisfy bandwidth requirements */
0040     int bw_min_cdclk;
0041     /* minimum acceptable cdclk for each pipe */
0042     int min_cdclk[I915_MAX_PIPES];
0043     /* minimum acceptable voltage level for each pipe */
0044     u8 min_voltage_level[I915_MAX_PIPES];
0045
0046     /* pipe to which cd2x update is synchronized */
0047     enum pipe pipe;
0048
0049     /* forced minimum cdclk for glk+ audio w/a */
0050     int force_min_cdclk;
0051
0052     /* bitmask of active pipes */
0053     u8 active_pipes;
0054 };
0055
0056 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
0057 void intel_cdclk_init_hw(struct drm_i915_private *i915);
0058 void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
0059 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
0060 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
0061 void intel_update_cdclk(struct drm_i915_private *dev_priv);
0062 u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
0063 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
0064                    const struct intel_cdclk_config *b);
0065 void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
0066 void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
0067 void intel_cdclk_dump_config(struct drm_i915_private *i915,
0068                  const struct intel_cdclk_config *cdclk_config,
0069                  const char *context);
0070 int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
0071 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
0072                struct intel_cdclk_config *cdclk_config);
0073 int intel_cdclk_atomic_check(struct intel_atomic_state *state,
0074                  bool *need_cdclk_calc);
0075 struct intel_cdclk_state *
0076 intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
0077
0078 #define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
0079 #define intel_atomic_get_old_cdclk_state(state) \
0080     to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
0081 #define intel_atomic_get_new_cdclk_state(state) \
0082     to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
0083
0084 int intel_cdclk_init(struct drm_i915_private *dev_priv);
0085
0086 #endif /* __INTEL_CDCLK_H__ */