i915/display/intel_bw.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005
0006 #ifndef __INTEL_BW_H__
0007 #define __INTEL_BW_H__
0008
0009 #include <drm/drm_atomic.h>
0010
0011 #include "intel_display.h"
0012 #include "intel_display_power.h"
0013 #include "intel_global_state.h"
0014
0015 struct drm_i915_private;
0016 struct intel_atomic_state;
0017 struct intel_crtc_state;
0018
0019 struct intel_dbuf_bw {
0020     unsigned int max_bw[I915_MAX_DBUF_SLICES];
0021     u8 active_planes[I915_MAX_DBUF_SLICES];
0022 };
0023
0024 struct intel_bw_state {
0025     struct intel_global_state base;
0026     struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
0027
0028     /*
0029      * Contains a bit mask, used to determine, whether correspondent
0030      * pipe allows SAGV or not.
0031      */
0032     u8 pipe_sagv_reject;
0033
0034     /* bitmask of active pipes */
0035     u8 active_pipes;
0036
0037     /*
0038      * Current QGV points mask, which restricts
0039      * some particular SAGV states, not to confuse
0040      * with pipe_sagv_mask.
0041      */
0042     u16 qgv_points_mask;
0043
0044     int min_cdclk[I915_MAX_PIPES];
0045     unsigned int data_rate[I915_MAX_PIPES];
0046     u8 num_active_planes[I915_MAX_PIPES];
0047 };
0048
0049 #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
0050
0051 struct intel_bw_state *
0052 intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
0053
0054 struct intel_bw_state *
0055 intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
0056
0057 struct intel_bw_state *
0058 intel_atomic_get_bw_state(struct intel_atomic_state *state);
0059
0060 void intel_bw_init_hw(struct drm_i915_private *dev_priv);
0061 int intel_bw_init(struct drm_i915_private *dev_priv);
0062 int intel_bw_atomic_check(struct intel_atomic_state *state);
0063 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
0064               const struct intel_crtc_state *crtc_state);
0065 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
0066                   u32 points_mask);
0067 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
0068                 bool *need_cdclk_calc);
0069 int intel_bw_min_cdclk(struct drm_i915_private *i915,
0070                const struct intel_bw_state *bw_state);
0071
0072 #endif /* __INTEL_BW_H__ */