Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2019 Intel Corporation
0004  */
0005 
0006 #include <drm/drm_atomic_state_helper.h>
0007 
0008 #include "i915_reg.h"
0009 #include "i915_utils.h"
0010 #include "intel_atomic.h"
0011 #include "intel_bw.h"
0012 #include "intel_cdclk.h"
0013 #include "intel_display_types.h"
0014 #include "intel_mchbar_regs.h"
0015 #include "intel_pcode.h"
0016 #include "intel_pm.h"
0017 
0018 /* Parameters for Qclk Geyserville (QGV) */
0019 struct intel_qgv_point {
0020     u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
0021 };
0022 
0023 struct intel_psf_gv_point {
0024     u8 clk; /* clock in multiples of 16.6666 MHz */
0025 };
0026 
0027 struct intel_qgv_info {
0028     struct intel_qgv_point points[I915_NUM_QGV_POINTS];
0029     struct intel_psf_gv_point psf_points[I915_NUM_PSF_GV_POINTS];
0030     u8 num_points;
0031     u8 num_psf_points;
0032     u8 t_bl;
0033     u8 max_numchannels;
0034     u8 channel_width;
0035     u8 deinterleave;
0036 };
0037 
0038 static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
0039                       struct intel_qgv_point *sp,
0040                       int point)
0041 {
0042     u32 dclk_ratio, dclk_reference;
0043     u32 val;
0044 
0045     val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
0046     dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
0047     if (val & DG1_QCLK_REFERENCE)
0048         dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
0049     else
0050         dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
0051     sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
0052 
0053     val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
0054     if (val & DG1_GEAR_TYPE)
0055         sp->dclk *= 2;
0056 
0057     if (sp->dclk == 0)
0058         return -EINVAL;
0059 
0060     val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
0061     sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
0062     sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
0063 
0064     val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
0065     sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
0066     sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
0067 
0068     sp->t_rc = sp->t_rp + sp->t_ras;
0069 
0070     return 0;
0071 }
0072 
0073 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
0074                      struct intel_qgv_point *sp,
0075                      int point)
0076 {
0077     u32 val = 0, val2 = 0;
0078     u16 dclk;
0079     int ret;
0080 
0081     ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
0082                  ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
0083                  &val, &val2);
0084     if (ret)
0085         return ret;
0086 
0087     dclk = val & 0xffff;
0088     sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000);
0089     sp->t_rp = (val & 0xff0000) >> 16;
0090     sp->t_rcd = (val & 0xff000000) >> 24;
0091 
0092     sp->t_rdpre = val2 & 0xff;
0093     sp->t_ras = (val2 & 0xff00) >> 8;
0094 
0095     sp->t_rc = sp->t_rp + sp->t_ras;
0096 
0097     return 0;
0098 }
0099 
0100 static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
0101                         struct intel_psf_gv_point *points)
0102 {
0103     u32 val = 0;
0104     int ret;
0105     int i;
0106 
0107     ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
0108                  ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
0109     if (ret)
0110         return ret;
0111 
0112     for (i = 0; i < I915_NUM_PSF_GV_POINTS; i++) {
0113         points[i].clk = val & 0xff;
0114         val >>= 8;
0115     }
0116 
0117     return 0;
0118 }
0119 
0120 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
0121                   u32 points_mask)
0122 {
0123     int ret;
0124 
0125     /* bspec says to keep retrying for at least 1 ms */
0126     ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
0127                 points_mask,
0128                 ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
0129                 ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
0130                 1);
0131 
0132     if (ret < 0) {
0133         drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask);
0134         return ret;
0135     }
0136 
0137     return 0;
0138 }
0139 
0140 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
0141                   struct intel_qgv_info *qi,
0142                   bool is_y_tile)
0143 {
0144     const struct dram_info *dram_info = &dev_priv->dram_info;
0145     int i, ret;
0146 
0147     qi->num_points = dram_info->num_qgv_points;
0148     qi->num_psf_points = dram_info->num_psf_gv_points;
0149 
0150     if (DISPLAY_VER(dev_priv) >= 12)
0151         switch (dram_info->type) {
0152         case INTEL_DRAM_DDR4:
0153             qi->t_bl = is_y_tile ? 8 : 4;
0154             qi->max_numchannels = 2;
0155             qi->channel_width = 64;
0156             qi->deinterleave = is_y_tile ? 1 : 2;
0157             break;
0158         case INTEL_DRAM_DDR5:
0159             qi->t_bl = is_y_tile ? 16 : 8;
0160             qi->max_numchannels = 4;
0161             qi->channel_width = 32;
0162             qi->deinterleave = is_y_tile ? 1 : 2;
0163             break;
0164         case INTEL_DRAM_LPDDR4:
0165             if (IS_ROCKETLAKE(dev_priv)) {
0166                 qi->t_bl = 8;
0167                 qi->max_numchannels = 4;
0168                 qi->channel_width = 32;
0169                 qi->deinterleave = 2;
0170                 break;
0171             }
0172             fallthrough;
0173         case INTEL_DRAM_LPDDR5:
0174             qi->t_bl = 16;
0175             qi->max_numchannels = 8;
0176             qi->channel_width = 16;
0177             qi->deinterleave = is_y_tile ? 2 : 4;
0178             break;
0179         default:
0180             qi->t_bl = 16;
0181             qi->max_numchannels = 1;
0182             break;
0183         }
0184     else if (DISPLAY_VER(dev_priv) == 11) {
0185         qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
0186         qi->max_numchannels = 1;
0187     }
0188 
0189     if (drm_WARN_ON(&dev_priv->drm,
0190             qi->num_points > ARRAY_SIZE(qi->points)))
0191         qi->num_points = ARRAY_SIZE(qi->points);
0192 
0193     for (i = 0; i < qi->num_points; i++) {
0194         struct intel_qgv_point *sp = &qi->points[i];
0195 
0196         if (IS_DG1(dev_priv))
0197             ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
0198         else
0199             ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
0200 
0201         if (ret)
0202             return ret;
0203 
0204         drm_dbg_kms(&dev_priv->drm,
0205                 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
0206                 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
0207                 sp->t_rcd, sp->t_rc);
0208     }
0209 
0210     if (qi->num_psf_points > 0) {
0211         ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
0212         if (ret) {
0213             drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
0214             qi->num_psf_points = 0;
0215         }
0216 
0217         for (i = 0; i < qi->num_psf_points; i++)
0218             drm_dbg_kms(&dev_priv->drm,
0219                     "PSF GV %d: CLK=%d \n",
0220                     i, qi->psf_points[i].clk);
0221     }
0222 
0223     return 0;
0224 }
0225 
0226 static int adl_calc_psf_bw(int clk)
0227 {
0228     /*
0229      * clk is multiples of 16.666MHz (100/6)
0230      * According to BSpec PSF GV bandwidth is
0231      * calculated as BW = 64 * clk * 16.666Mhz
0232      */
0233     return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
0234 }
0235 
0236 static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
0237 {
0238     u16 dclk = 0;
0239     int i;
0240 
0241     for (i = 0; i < qi->num_points; i++)
0242         dclk = max(dclk, qi->points[i].dclk);
0243 
0244     return dclk;
0245 }
0246 
0247 struct intel_sa_info {
0248     u16 displayrtids;
0249     u8 deburst, deprogbwlimit, derating;
0250 };
0251 
0252 static const struct intel_sa_info icl_sa_info = {
0253     .deburst = 8,
0254     .deprogbwlimit = 25, /* GB/s */
0255     .displayrtids = 128,
0256     .derating = 10,
0257 };
0258 
0259 static const struct intel_sa_info tgl_sa_info = {
0260     .deburst = 16,
0261     .deprogbwlimit = 34, /* GB/s */
0262     .displayrtids = 256,
0263     .derating = 10,
0264 };
0265 
0266 static const struct intel_sa_info rkl_sa_info = {
0267     .deburst = 8,
0268     .deprogbwlimit = 20, /* GB/s */
0269     .displayrtids = 128,
0270     .derating = 10,
0271 };
0272 
0273 static const struct intel_sa_info adls_sa_info = {
0274     .deburst = 16,
0275     .deprogbwlimit = 38, /* GB/s */
0276     .displayrtids = 256,
0277     .derating = 10,
0278 };
0279 
0280 static const struct intel_sa_info adlp_sa_info = {
0281     .deburst = 16,
0282     .deprogbwlimit = 38, /* GB/s */
0283     .displayrtids = 256,
0284     .derating = 20,
0285 };
0286 
0287 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
0288 {
0289     struct intel_qgv_info qi = {};
0290     bool is_y_tile = true; /* assume y tile may be used */
0291     int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
0292     int ipqdepth, ipqdepthpch = 16;
0293     int dclk_max;
0294     int maxdebw;
0295     int num_groups = ARRAY_SIZE(dev_priv->max_bw);
0296     int i, ret;
0297 
0298     ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
0299     if (ret) {
0300         drm_dbg_kms(&dev_priv->drm,
0301                 "Failed to get memory subsystem information, ignoring bandwidth limits");
0302         return ret;
0303     }
0304 
0305     dclk_max = icl_sagv_max_dclk(&qi);
0306     maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
0307     ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
0308     qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
0309 
0310     for (i = 0; i < num_groups; i++) {
0311         struct intel_bw_info *bi = &dev_priv->max_bw[i];
0312         int clpchgroup;
0313         int j;
0314 
0315         clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
0316         bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
0317 
0318         bi->num_qgv_points = qi.num_points;
0319         bi->num_psf_gv_points = qi.num_psf_points;
0320 
0321         for (j = 0; j < qi.num_points; j++) {
0322             const struct intel_qgv_point *sp = &qi.points[j];
0323             int ct, bw;
0324 
0325             /*
0326              * Max row cycle time
0327              *
0328              * FIXME what is the logic behind the
0329              * assumed burst length?
0330              */
0331             ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
0332                    (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
0333             bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
0334 
0335             bi->deratedbw[j] = min(maxdebw,
0336                            bw * (100 - sa->derating) / 100);
0337 
0338             drm_dbg_kms(&dev_priv->drm,
0339                     "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
0340                     i, j, bi->num_planes, bi->deratedbw[j]);
0341         }
0342     }
0343     /*
0344      * In case if SAGV is disabled in BIOS, we always get 1
0345      * SAGV point, but we can't send PCode commands to restrict it
0346      * as it will fail and pointless anyway.
0347      */
0348     if (qi.num_points == 1)
0349         dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
0350     else
0351         dev_priv->sagv_status = I915_SAGV_ENABLED;
0352 
0353     return 0;
0354 }
0355 
0356 static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
0357 {
0358     struct intel_qgv_info qi = {};
0359     const struct dram_info *dram_info = &dev_priv->dram_info;
0360     bool is_y_tile = true; /* assume y tile may be used */
0361     int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
0362     int ipqdepth, ipqdepthpch = 16;
0363     int dclk_max;
0364     int maxdebw, peakbw;
0365     int clperchgroup;
0366     int num_groups = ARRAY_SIZE(dev_priv->max_bw);
0367     int i, ret;
0368 
0369     ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
0370     if (ret) {
0371         drm_dbg_kms(&dev_priv->drm,
0372                 "Failed to get memory subsystem information, ignoring bandwidth limits");
0373         return ret;
0374     }
0375 
0376     if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5)
0377         num_channels *= 2;
0378 
0379     qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
0380 
0381     if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
0382         qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
0383 
0384     if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)
0385         drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");
0386     if (qi.max_numchannels != 0)
0387         num_channels = min_t(u8, num_channels, qi.max_numchannels);
0388 
0389     dclk_max = icl_sagv_max_dclk(&qi);
0390 
0391     peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
0392     maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */
0393 
0394     ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
0395     /*
0396      * clperchgroup = 4kpagespermempage * clperchperblock,
0397      * clperchperblock = 8 / num_channels * interleave
0398      */
0399     clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
0400 
0401     for (i = 0; i < num_groups; i++) {
0402         struct intel_bw_info *bi = &dev_priv->max_bw[i];
0403         struct intel_bw_info *bi_next;
0404         int clpchgroup;
0405         int j;
0406 
0407         clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
0408 
0409         if (i < num_groups - 1) {
0410             bi_next = &dev_priv->max_bw[i + 1];
0411 
0412             if (clpchgroup < clperchgroup)
0413                 bi_next->num_planes = (ipqdepth - clpchgroup) /
0414                                clpchgroup + 1;
0415             else
0416                 bi_next->num_planes = 0;
0417         }
0418 
0419         bi->num_qgv_points = qi.num_points;
0420         bi->num_psf_gv_points = qi.num_psf_points;
0421 
0422         for (j = 0; j < qi.num_points; j++) {
0423             const struct intel_qgv_point *sp = &qi.points[j];
0424             int ct, bw;
0425 
0426             /*
0427              * Max row cycle time
0428              *
0429              * FIXME what is the logic behind the
0430              * assumed burst length?
0431              */
0432             ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
0433                    (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
0434             bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
0435 
0436             bi->deratedbw[j] = min(maxdebw,
0437                            bw * (100 - sa->derating) / 100);
0438 
0439             drm_dbg_kms(&dev_priv->drm,
0440                     "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
0441                     i, j, bi->num_planes, bi->deratedbw[j]);
0442         }
0443 
0444         for (j = 0; j < qi.num_psf_points; j++) {
0445             const struct intel_psf_gv_point *sp = &qi.psf_points[j];
0446 
0447             bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
0448 
0449             drm_dbg_kms(&dev_priv->drm,
0450                     "BW%d / PSF GV %d: num_planes=%d bw=%u\n",
0451                     i, j, bi->num_planes, bi->psf_bw[j]);
0452         }
0453     }
0454 
0455     /*
0456      * In case if SAGV is disabled in BIOS, we always get 1
0457      * SAGV point, but we can't send PCode commands to restrict it
0458      * as it will fail and pointless anyway.
0459      */
0460     if (qi.num_points == 1)
0461         dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
0462     else
0463         dev_priv->sagv_status = I915_SAGV_ENABLED;
0464 
0465     return 0;
0466 }
0467 
0468 static void dg2_get_bw_info(struct drm_i915_private *i915)
0469 {
0470     unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 50000;
0471     int num_groups = ARRAY_SIZE(i915->max_bw);
0472     int i;
0473 
0474     /*
0475      * DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
0476      * that doesn't depend on the number of planes enabled. So fill all the
0477      * plane group with constant bw information for uniformity with other
0478      * platforms. DG2-G10 platforms have a constant 50 GB/s bandwidth,
0479      * whereas DG2-G11 platforms have 38 GB/s.
0480      */
0481     for (i = 0; i < num_groups; i++) {
0482         struct intel_bw_info *bi = &i915->max_bw[i];
0483 
0484         bi->num_planes = 1;
0485         /* Need only one dummy QGV point per group */
0486         bi->num_qgv_points = 1;
0487         bi->deratedbw[0] = deratedbw;
0488     }
0489 
0490     i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
0491 }
0492 
0493 static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
0494                    int num_planes, int qgv_point)
0495 {
0496     int i;
0497 
0498     /*
0499      * Let's return max bw for 0 planes
0500      */
0501     num_planes = max(1, num_planes);
0502 
0503     for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
0504         const struct intel_bw_info *bi =
0505             &dev_priv->max_bw[i];
0506 
0507         /*
0508          * Pcode will not expose all QGV points when
0509          * SAGV is forced to off/min/med/max.
0510          */
0511         if (qgv_point >= bi->num_qgv_points)
0512             return UINT_MAX;
0513 
0514         if (num_planes >= bi->num_planes)
0515             return bi->deratedbw[qgv_point];
0516     }
0517 
0518     return 0;
0519 }
0520 
0521 static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
0522                    int num_planes, int qgv_point)
0523 {
0524     int i;
0525 
0526     /*
0527      * Let's return max bw for 0 planes
0528      */
0529     num_planes = max(1, num_planes);
0530 
0531     for (i = ARRAY_SIZE(dev_priv->max_bw) - 1; i >= 0; i--) {
0532         const struct intel_bw_info *bi =
0533             &dev_priv->max_bw[i];
0534 
0535         /*
0536          * Pcode will not expose all QGV points when
0537          * SAGV is forced to off/min/med/max.
0538          */
0539         if (qgv_point >= bi->num_qgv_points)
0540             return UINT_MAX;
0541 
0542         if (num_planes <= bi->num_planes)
0543             return bi->deratedbw[qgv_point];
0544     }
0545 
0546     return dev_priv->max_bw[0].deratedbw[qgv_point];
0547 }
0548 
0549 static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
0550                    int psf_gv_point)
0551 {
0552     const struct intel_bw_info *bi =
0553             &dev_priv->max_bw[0];
0554 
0555     return bi->psf_bw[psf_gv_point];
0556 }
0557 
0558 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
0559 {
0560     if (!HAS_DISPLAY(dev_priv))
0561         return;
0562 
0563     if (IS_DG2(dev_priv))
0564         dg2_get_bw_info(dev_priv);
0565     else if (IS_ALDERLAKE_P(dev_priv))
0566         tgl_get_bw_info(dev_priv, &adlp_sa_info);
0567     else if (IS_ALDERLAKE_S(dev_priv))
0568         tgl_get_bw_info(dev_priv, &adls_sa_info);
0569     else if (IS_ROCKETLAKE(dev_priv))
0570         tgl_get_bw_info(dev_priv, &rkl_sa_info);
0571     else if (DISPLAY_VER(dev_priv) == 12)
0572         tgl_get_bw_info(dev_priv, &tgl_sa_info);
0573     else if (DISPLAY_VER(dev_priv) == 11)
0574         icl_get_bw_info(dev_priv, &icl_sa_info);
0575 }
0576 
0577 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
0578 {
0579     /*
0580      * We assume cursors are small enough
0581      * to not not cause bandwidth problems.
0582      */
0583     return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
0584 }
0585 
0586 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
0587 {
0588     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0589     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0590     unsigned int data_rate = 0;
0591     enum plane_id plane_id;
0592 
0593     for_each_plane_id_on_crtc(crtc, plane_id) {
0594         /*
0595          * We assume cursors are small enough
0596          * to not not cause bandwidth problems.
0597          */
0598         if (plane_id == PLANE_CURSOR)
0599             continue;
0600 
0601         data_rate += crtc_state->data_rate[plane_id];
0602 
0603         if (DISPLAY_VER(i915) < 11)
0604             data_rate += crtc_state->data_rate_y[plane_id];
0605     }
0606 
0607     return data_rate;
0608 }
0609 
0610 /* "Maximum Pipe Read Bandwidth" */
0611 static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
0612 {
0613     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0614     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0615 
0616     if (DISPLAY_VER(i915) < 12)
0617         return 0;
0618 
0619     return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
0620 }
0621 
0622 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
0623               const struct intel_crtc_state *crtc_state)
0624 {
0625     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0626     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0627 
0628     bw_state->data_rate[crtc->pipe] =
0629         intel_bw_crtc_data_rate(crtc_state);
0630     bw_state->num_active_planes[crtc->pipe] =
0631         intel_bw_crtc_num_active_planes(crtc_state);
0632 
0633     drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
0634             pipe_name(crtc->pipe),
0635             bw_state->data_rate[crtc->pipe],
0636             bw_state->num_active_planes[crtc->pipe]);
0637 }
0638 
0639 static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
0640                            const struct intel_bw_state *bw_state)
0641 {
0642     unsigned int num_active_planes = 0;
0643     enum pipe pipe;
0644 
0645     for_each_pipe(dev_priv, pipe)
0646         num_active_planes += bw_state->num_active_planes[pipe];
0647 
0648     return num_active_planes;
0649 }
0650 
0651 static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
0652                        const struct intel_bw_state *bw_state)
0653 {
0654     unsigned int data_rate = 0;
0655     enum pipe pipe;
0656 
0657     for_each_pipe(dev_priv, pipe)
0658         data_rate += bw_state->data_rate[pipe];
0659 
0660     if (DISPLAY_VER(dev_priv) >= 13 && i915_vtd_active(dev_priv))
0661         data_rate = DIV_ROUND_UP(data_rate * 105, 100);
0662 
0663     return data_rate;
0664 }
0665 
0666 struct intel_bw_state *
0667 intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
0668 {
0669     struct drm_i915_private *dev_priv = to_i915(state->base.dev);
0670     struct intel_global_state *bw_state;
0671 
0672     bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
0673 
0674     return to_intel_bw_state(bw_state);
0675 }
0676 
0677 struct intel_bw_state *
0678 intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
0679 {
0680     struct drm_i915_private *dev_priv = to_i915(state->base.dev);
0681     struct intel_global_state *bw_state;
0682 
0683     bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
0684 
0685     return to_intel_bw_state(bw_state);
0686 }
0687 
0688 struct intel_bw_state *
0689 intel_atomic_get_bw_state(struct intel_atomic_state *state)
0690 {
0691     struct drm_i915_private *dev_priv = to_i915(state->base.dev);
0692     struct intel_global_state *bw_state;
0693 
0694     bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj);
0695     if (IS_ERR(bw_state))
0696         return ERR_CAST(bw_state);
0697 
0698     return to_intel_bw_state(bw_state);
0699 }
0700 
0701 static bool intel_bw_state_changed(struct drm_i915_private *i915,
0702                    const struct intel_bw_state *old_bw_state,
0703                    const struct intel_bw_state *new_bw_state)
0704 {
0705     enum pipe pipe;
0706 
0707     for_each_pipe(i915, pipe) {
0708         const struct intel_dbuf_bw *old_crtc_bw =
0709             &old_bw_state->dbuf_bw[pipe];
0710         const struct intel_dbuf_bw *new_crtc_bw =
0711             &new_bw_state->dbuf_bw[pipe];
0712         enum dbuf_slice slice;
0713 
0714         for_each_dbuf_slice(i915, slice) {
0715             if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
0716                 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
0717                 return true;
0718         }
0719 
0720         if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
0721             return true;
0722     }
0723 
0724     return false;
0725 }
0726 
0727 static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
0728                    struct intel_crtc *crtc,
0729                    enum plane_id plane_id,
0730                    const struct skl_ddb_entry *ddb,
0731                    unsigned int data_rate)
0732 {
0733     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0734     struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
0735     unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
0736     enum dbuf_slice slice;
0737 
0738     /*
0739      * The arbiter can only really guarantee an
0740      * equal share of the total bw to each plane.
0741      */
0742     for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
0743         crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
0744         crtc_bw->active_planes[slice] |= BIT(plane_id);
0745     }
0746 }
0747 
0748 static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
0749                   const struct intel_crtc_state *crtc_state)
0750 {
0751     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0752     struct drm_i915_private *i915 = to_i915(crtc->base.dev);
0753     struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
0754     enum plane_id plane_id;
0755 
0756     memset(crtc_bw, 0, sizeof(*crtc_bw));
0757 
0758     if (!crtc_state->hw.active)
0759         return;
0760 
0761     for_each_plane_id_on_crtc(crtc, plane_id) {
0762         /*
0763          * We assume cursors are small enough
0764          * to not cause bandwidth problems.
0765          */
0766         if (plane_id == PLANE_CURSOR)
0767             continue;
0768 
0769         skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
0770                        &crtc_state->wm.skl.plane_ddb[plane_id],
0771                        crtc_state->data_rate[plane_id]);
0772 
0773         if (DISPLAY_VER(i915) < 11)
0774             skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
0775                            &crtc_state->wm.skl.plane_ddb_y[plane_id],
0776                            crtc_state->data_rate[plane_id]);
0777     }
0778 }
0779 
0780 /* "Maximum Data Buffer Bandwidth" */
0781 static int
0782 intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
0783             const struct intel_bw_state *bw_state)
0784 {
0785     unsigned int total_max_bw = 0;
0786     enum dbuf_slice slice;
0787 
0788     for_each_dbuf_slice(i915, slice) {
0789         int num_active_planes = 0;
0790         unsigned int max_bw = 0;
0791         enum pipe pipe;
0792 
0793         /*
0794          * The arbiter can only really guarantee an
0795          * equal share of the total bw to each plane.
0796          */
0797         for_each_pipe(i915, pipe) {
0798             const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
0799 
0800             max_bw = max(crtc_bw->max_bw[slice], max_bw);
0801             num_active_planes += hweight8(crtc_bw->active_planes[slice]);
0802         }
0803         max_bw *= num_active_planes;
0804 
0805         total_max_bw = max(total_max_bw, max_bw);
0806     }
0807 
0808     return DIV_ROUND_UP(total_max_bw, 64);
0809 }
0810 
0811 int intel_bw_min_cdclk(struct drm_i915_private *i915,
0812                const struct intel_bw_state *bw_state)
0813 {
0814     enum pipe pipe;
0815     int min_cdclk;
0816 
0817     min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
0818 
0819     for_each_pipe(i915, pipe)
0820         min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
0821 
0822     return min_cdclk;
0823 }
0824 
0825 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
0826                 bool *need_cdclk_calc)
0827 {
0828     struct drm_i915_private *dev_priv = to_i915(state->base.dev);
0829     struct intel_bw_state *new_bw_state = NULL;
0830     const struct intel_bw_state *old_bw_state = NULL;
0831     const struct intel_cdclk_state *cdclk_state;
0832     const struct intel_crtc_state *crtc_state;
0833     int old_min_cdclk, new_min_cdclk;
0834     struct intel_crtc *crtc;
0835     int i;
0836 
0837     if (DISPLAY_VER(dev_priv) < 9)
0838         return 0;
0839 
0840     for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
0841         new_bw_state = intel_atomic_get_bw_state(state);
0842         if (IS_ERR(new_bw_state))
0843             return PTR_ERR(new_bw_state);
0844 
0845         old_bw_state = intel_atomic_get_old_bw_state(state);
0846 
0847         skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
0848 
0849         new_bw_state->min_cdclk[crtc->pipe] =
0850             intel_bw_crtc_min_cdclk(crtc_state);
0851     }
0852 
0853     if (!old_bw_state)
0854         return 0;
0855 
0856     if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
0857         int ret = intel_atomic_lock_global_state(&new_bw_state->base);
0858         if (ret)
0859             return ret;
0860     }
0861 
0862     old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
0863     new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
0864 
0865     /*
0866      * No need to check against the cdclk state if
0867      * the min cdclk doesn't increase.
0868      *
0869      * Ie. we only ever increase the cdclk due to bandwidth
0870      * requirements. This can reduce back and forth
0871      * display blinking due to constant cdclk changes.
0872      */
0873     if (new_min_cdclk <= old_min_cdclk)
0874         return 0;
0875 
0876     cdclk_state = intel_atomic_get_cdclk_state(state);
0877     if (IS_ERR(cdclk_state))
0878         return PTR_ERR(cdclk_state);
0879 
0880     /*
0881      * No need to recalculate the cdclk state if
0882      * the min cdclk doesn't increase.
0883      *
0884      * Ie. we only ever increase the cdclk due to bandwidth
0885      * requirements. This can reduce back and forth
0886      * display blinking due to constant cdclk changes.
0887      */
0888     if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
0889         return 0;
0890 
0891     drm_dbg_kms(&dev_priv->drm,
0892             "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
0893             new_min_cdclk, cdclk_state->bw_min_cdclk);
0894     *need_cdclk_calc = true;
0895 
0896     return 0;
0897 }
0898 
0899 static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
0900 {
0901     unsigned int num_psf_gv_points = i915->max_bw[0].num_psf_gv_points;
0902     unsigned int num_qgv_points = i915->max_bw[0].num_qgv_points;
0903     u16 qgv_points = 0, psf_points = 0;
0904 
0905     /*
0906      * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
0907      * it with failure if we try masking any unadvertised points.
0908      * So need to operate only with those returned from PCode.
0909      */
0910     if (num_qgv_points > 0)
0911         qgv_points = GENMASK(num_qgv_points - 1, 0);
0912 
0913     if (num_psf_gv_points > 0)
0914         psf_points = GENMASK(num_psf_gv_points - 1, 0);
0915 
0916     return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
0917 }
0918 
0919 static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
0920 {
0921     struct drm_i915_private *i915 = to_i915(state->base.dev);
0922     const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
0923     struct intel_crtc *crtc;
0924     int i;
0925 
0926     for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
0927                         new_crtc_state, i) {
0928         unsigned int old_data_rate =
0929             intel_bw_crtc_data_rate(old_crtc_state);
0930         unsigned int new_data_rate =
0931             intel_bw_crtc_data_rate(new_crtc_state);
0932         unsigned int old_active_planes =
0933             intel_bw_crtc_num_active_planes(old_crtc_state);
0934         unsigned int new_active_planes =
0935             intel_bw_crtc_num_active_planes(new_crtc_state);
0936         struct intel_bw_state *new_bw_state;
0937 
0938         /*
0939          * Avoid locking the bw state when
0940          * nothing significant has changed.
0941          */
0942         if (old_data_rate == new_data_rate &&
0943             old_active_planes == new_active_planes)
0944             continue;
0945 
0946         new_bw_state = intel_atomic_get_bw_state(state);
0947         if (IS_ERR(new_bw_state))
0948             return PTR_ERR(new_bw_state);
0949 
0950         new_bw_state->data_rate[crtc->pipe] = new_data_rate;
0951         new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
0952 
0953         *changed = true;
0954 
0955         drm_dbg_kms(&i915->drm,
0956                 "[CRTC:%d:%s] data rate %u num active planes %u\n",
0957                 crtc->base.base.id, crtc->base.name,
0958                 new_bw_state->data_rate[crtc->pipe],
0959                 new_bw_state->num_active_planes[crtc->pipe]);
0960     }
0961 
0962     return 0;
0963 }
0964 
0965 int intel_bw_atomic_check(struct intel_atomic_state *state)
0966 {
0967     struct drm_i915_private *dev_priv = to_i915(state->base.dev);
0968     const struct intel_bw_state *old_bw_state;
0969     struct intel_bw_state *new_bw_state;
0970     unsigned int data_rate;
0971     unsigned int num_active_planes;
0972     int i, ret;
0973     u16 qgv_points = 0, psf_points = 0;
0974     unsigned int max_bw_point = 0, max_bw = 0;
0975     unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
0976     unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
0977     bool changed = false;
0978 
0979     /* FIXME earlier gens need some checks too */
0980     if (DISPLAY_VER(dev_priv) < 11)
0981         return 0;
0982 
0983     ret = intel_bw_check_data_rate(state, &changed);
0984     if (ret)
0985         return ret;
0986 
0987     old_bw_state = intel_atomic_get_old_bw_state(state);
0988     new_bw_state = intel_atomic_get_new_bw_state(state);
0989 
0990     if (new_bw_state &&
0991         intel_can_enable_sagv(dev_priv, old_bw_state) !=
0992         intel_can_enable_sagv(dev_priv, new_bw_state))
0993         changed = true;
0994 
0995     /*
0996      * If none of our inputs (data rates, number of active
0997      * planes, SAGV yes/no) changed then nothing to do here.
0998      */
0999     if (!changed)
1000         return 0;
1001 
1002     ret = intel_atomic_lock_global_state(&new_bw_state->base);
1003     if (ret)
1004         return ret;
1005 
1006     data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
1007     data_rate = DIV_ROUND_UP(data_rate, 1000);
1008 
1009     num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
1010 
1011     for (i = 0; i < num_qgv_points; i++) {
1012         unsigned int max_data_rate;
1013 
1014         if (DISPLAY_VER(dev_priv) > 11)
1015             max_data_rate = tgl_max_bw(dev_priv, num_active_planes, i);
1016         else
1017             max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
1018         /*
1019          * We need to know which qgv point gives us
1020          * maximum bandwidth in order to disable SAGV
1021          * if we find that we exceed SAGV block time
1022          * with watermarks. By that moment we already
1023          * have those, as it is calculated earlier in
1024          * intel_atomic_check,
1025          */
1026         if (max_data_rate > max_bw) {
1027             max_bw_point = i;
1028             max_bw = max_data_rate;
1029         }
1030         if (max_data_rate >= data_rate)
1031             qgv_points |= BIT(i);
1032 
1033         drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n",
1034                 i, max_data_rate, data_rate);
1035     }
1036 
1037     for (i = 0; i < num_psf_gv_points; i++) {
1038         unsigned int max_data_rate = adl_psf_bw(dev_priv, i);
1039 
1040         if (max_data_rate >= data_rate)
1041             psf_points |= BIT(i);
1042 
1043         drm_dbg_kms(&dev_priv->drm, "PSF GV point %d: max bw %d"
1044                 " required %d\n",
1045                 i, max_data_rate, data_rate);
1046     }
1047 
1048     /*
1049      * BSpec states that we always should have at least one allowed point
1050      * left, so if we couldn't - simply reject the configuration for obvious
1051      * reasons.
1052      */
1053     if (qgv_points == 0) {
1054         drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory"
1055                 " bandwidth %d for display configuration(%d active planes).\n",
1056                 data_rate, num_active_planes);
1057         return -EINVAL;
1058     }
1059 
1060     if (num_psf_gv_points > 0 && psf_points == 0) {
1061         drm_dbg_kms(&dev_priv->drm, "No PSF GV points provide sufficient memory"
1062                 " bandwidth %d for display configuration(%d active planes).\n",
1063                 data_rate, num_active_planes);
1064         return -EINVAL;
1065     }
1066 
1067     /*
1068      * Leave only single point with highest bandwidth, if
1069      * we can't enable SAGV due to the increased memory latency it may
1070      * cause.
1071      */
1072     if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
1073         qgv_points = BIT(max_bw_point);
1074         drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
1075                 max_bw_point);
1076     }
1077 
1078     /*
1079      * We store the ones which need to be masked as that is what PCode
1080      * actually accepts as a parameter.
1081      */
1082     new_bw_state->qgv_points_mask =
1083         ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
1084           ADLS_PCODE_REQ_PSF_PT(psf_points)) &
1085         icl_qgv_points_mask(dev_priv);
1086 
1087     /*
1088      * If the actual mask had changed we need to make sure that
1089      * the commits are serialized(in case this is a nomodeset, nonblocking)
1090      */
1091     if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
1092         ret = intel_atomic_serialize_global_state(&new_bw_state->base);
1093         if (ret)
1094             return ret;
1095     }
1096 
1097     return 0;
1098 }
1099 
1100 static struct intel_global_state *
1101 intel_bw_duplicate_state(struct intel_global_obj *obj)
1102 {
1103     struct intel_bw_state *state;
1104 
1105     state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
1106     if (!state)
1107         return NULL;
1108 
1109     return &state->base;
1110 }
1111 
1112 static void intel_bw_destroy_state(struct intel_global_obj *obj,
1113                    struct intel_global_state *state)
1114 {
1115     kfree(state);
1116 }
1117 
1118 static const struct intel_global_state_funcs intel_bw_funcs = {
1119     .atomic_duplicate_state = intel_bw_duplicate_state,
1120     .atomic_destroy_state = intel_bw_destroy_state,
1121 };
1122 
1123 int intel_bw_init(struct drm_i915_private *dev_priv)
1124 {
1125     struct intel_bw_state *state;
1126 
1127     state = kzalloc(sizeof(*state), GFP_KERNEL);
1128     if (!state)
1129         return -ENOMEM;
1130 
1131     intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj,
1132                      &state->base, &intel_bw_funcs);
1133 
1134     return 0;
1135 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!