i915/display/intel_bios.h

0001 /*
0002  * Copyright © 2016-2019 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0020  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0021  * SOFTWARE.
0022  */
0023
0024 /*
0025  * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away
0026  * the VBT from the rest of the driver. Add the parsed, clean data to struct
0027  * intel_vbt_data within struct drm_i915_private.
0028  */
0029
0030 #ifndef _INTEL_BIOS_H_
0031 #define _INTEL_BIOS_H_
0032
0033 #include <linux/types.h>
0034
0035 struct drm_i915_private;
0036 struct edid;
0037 struct intel_bios_encoder_data;
0038 struct intel_crtc_state;
0039 struct intel_encoder;
0040 struct intel_panel;
0041 enum port;
0042
0043 enum intel_backlight_type {
0044     INTEL_BACKLIGHT_PMIC,
0045     INTEL_BACKLIGHT_LPSS,
0046     INTEL_BACKLIGHT_DISPLAY_DDI,
0047     INTEL_BACKLIGHT_DSI_DCS,
0048     INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
0049     INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
0050 };
0051
0052 struct edp_power_seq {
0053     u16 t1_t3;
0054     u16 t8;
0055     u16 t9;
0056     u16 t10;
0057     u16 t11_t12;
0058 } __packed;
0059
0060 /*
0061  * MIPI Sequence Block definitions
0062  *
0063  * Note the VBT spec has AssertReset / DeassertReset swapped from their
0064  * usual naming, we use the proper names here to avoid confusion when
0065  * reading the code.
0066  */
0067 enum mipi_seq {
0068     MIPI_SEQ_END = 0,
0069     MIPI_SEQ_DEASSERT_RESET,    /* Spec says MipiAssertResetPin */
0070     MIPI_SEQ_INIT_OTP,
0071     MIPI_SEQ_DISPLAY_ON,
0072     MIPI_SEQ_DISPLAY_OFF,
0073     MIPI_SEQ_ASSERT_RESET,      /* Spec says MipiDeassertResetPin */
0074     MIPI_SEQ_BACKLIGHT_ON,      /* sequence block v2+ */
0075     MIPI_SEQ_BACKLIGHT_OFF,     /* sequence block v2+ */
0076     MIPI_SEQ_TEAR_ON,       /* sequence block v2+ */
0077     MIPI_SEQ_TEAR_OFF,      /* sequence block v3+ */
0078     MIPI_SEQ_POWER_ON,      /* sequence block v3+ */
0079     MIPI_SEQ_POWER_OFF,     /* sequence block v3+ */
0080     MIPI_SEQ_MAX
0081 };
0082
0083 enum mipi_seq_element {
0084     MIPI_SEQ_ELEM_END = 0,
0085     MIPI_SEQ_ELEM_SEND_PKT,
0086     MIPI_SEQ_ELEM_DELAY,
0087     MIPI_SEQ_ELEM_GPIO,
0088     MIPI_SEQ_ELEM_I2C,      /* sequence block v2+ */
0089     MIPI_SEQ_ELEM_SPI,      /* sequence block v3+ */
0090     MIPI_SEQ_ELEM_PMIC,     /* sequence block v3+ */
0091     MIPI_SEQ_ELEM_MAX
0092 };
0093
0094 #define MIPI_DSI_UNDEFINED_PANEL_ID 0
0095 #define MIPI_DSI_GENERIC_PANEL_ID   1
0096
0097 struct mipi_config {
0098     u16 panel_id;
0099
0100     /* General Params */
0101     u32 enable_dithering:1;
0102     u32 rsvd1:1;
0103     u32 is_bridge:1;
0104
0105     u32 panel_arch_type:2;
0106     u32 is_cmd_mode:1;
0107
0108 #define NON_BURST_SYNC_PULSE    0x1
0109 #define NON_BURST_SYNC_EVENTS   0x2
0110 #define BURST_MODE      0x3
0111     u32 video_transfer_mode:2;
0112
0113     u32 cabc_supported:1;
0114 #define PPS_BLC_PMIC   0
0115 #define PPS_BLC_SOC    1
0116     u32 pwm_blc:1;
0117
0118     /* Bit 13:10 */
0119 #define PIXEL_FORMAT_RGB565         0x1
0120 #define PIXEL_FORMAT_RGB666         0x2
0121 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED  0x3
0122 #define PIXEL_FORMAT_RGB888         0x4
0123     u32 videomode_color_format:4;
0124
0125     /* Bit 15:14 */
0126 #define ENABLE_ROTATION_0   0x0
0127 #define ENABLE_ROTATION_90  0x1
0128 #define ENABLE_ROTATION_180 0x2
0129 #define ENABLE_ROTATION_270 0x3
0130     u32 rotation:2;
0131     u32 bta_enabled:1;
0132     u32 rsvd2:15;
0133
0134     /* 2 byte Port Description */
0135 #define DUAL_LINK_NOT_SUPPORTED 0
0136 #define DUAL_LINK_FRONT_BACK    1
0137 #define DUAL_LINK_PIXEL_ALT 2
0138     u16 dual_link:2;
0139     u16 lane_cnt:2;
0140     u16 pixel_overlap:3;
0141     u16 rgb_flip:1;
0142 #define DL_DCS_PORT_A           0x00
0143 #define DL_DCS_PORT_C           0x01
0144 #define DL_DCS_PORT_A_AND_C     0x02
0145     u16 dl_dcs_cabc_ports:2;
0146     u16 dl_dcs_backlight_ports:2;
0147     u16 rsvd3:4;
0148
0149     u16 rsvd4;
0150
0151     u8 rsvd5;
0152     u32 target_burst_mode_freq;
0153     u32 dsi_ddr_clk;
0154     u32 bridge_ref_clk;
0155
0156 #define  BYTE_CLK_SEL_20MHZ     0
0157 #define  BYTE_CLK_SEL_10MHZ     1
0158 #define  BYTE_CLK_SEL_5MHZ      2
0159     u8 byte_clk_sel:2;
0160
0161     u8 rsvd6:6;
0162
0163     /* DPHY Flags */
0164     u16 dphy_param_valid:1;
0165     u16 eot_pkt_disabled:1;
0166     u16 enable_clk_stop:1;
0167     u16 rsvd7:13;
0168
0169     u32 hs_tx_timeout;
0170     u32 lp_rx_timeout;
0171     u32 turn_around_timeout;
0172     u32 device_reset_timer;
0173     u32 master_init_timer;
0174     u32 dbi_bw_timer;
0175     u32 lp_byte_clk_val;
0176
0177     /*  4 byte Dphy Params */
0178     u32 prepare_cnt:6;
0179     u32 rsvd8:2;
0180     u32 clk_zero_cnt:8;
0181     u32 trail_cnt:5;
0182     u32 rsvd9:3;
0183     u32 exit_zero_cnt:6;
0184     u32 rsvd10:2;
0185
0186     u32 clk_lane_switch_cnt;
0187     u32 hl_switch_cnt;
0188
0189     u32 rsvd11[6];
0190
0191     /* timings based on dphy spec */
0192     u8 tclk_miss;
0193     u8 tclk_post;
0194     u8 rsvd12;
0195     u8 tclk_pre;
0196     u8 tclk_prepare;
0197     u8 tclk_settle;
0198     u8 tclk_term_enable;
0199     u8 tclk_trail;
0200     u16 tclk_prepare_clkzero;
0201     u8 rsvd13;
0202     u8 td_term_enable;
0203     u8 teot;
0204     u8 ths_exit;
0205     u8 ths_prepare;
0206     u16 ths_prepare_hszero;
0207     u8 rsvd14;
0208     u8 ths_settle;
0209     u8 ths_skip;
0210     u8 ths_trail;
0211     u8 tinit;
0212     u8 tlpx;
0213     u8 rsvd15[3];
0214
0215     /* GPIOs */
0216     u8 panel_enable;
0217     u8 bl_enable;
0218     u8 pwm_enable;
0219     u8 reset_r_n;
0220     u8 pwr_down_r;
0221     u8 stdby_r_n;
0222
0223 } __packed;
0224
0225 /* all delays have a unit of 100us */
0226 struct mipi_pps_data {
0227     u16 panel_on_delay;
0228     u16 bl_enable_delay;
0229     u16 bl_disable_delay;
0230     u16 panel_off_delay;
0231     u16 panel_power_cycle_delay;
0232 } __packed;
0233
0234 void intel_bios_init(struct drm_i915_private *dev_priv);
0235 void intel_bios_init_panel(struct drm_i915_private *dev_priv,
0236                struct intel_panel *panel,
0237                const struct intel_bios_encoder_data *devdata,
0238                const struct edid *edid);
0239 void intel_bios_fini_panel(struct intel_panel *panel);
0240 void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
0241 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
0242 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
0243 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
0244 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
0245 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
0246 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
0247 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
0248 bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
0249                      enum port port);
0250 bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
0251                   enum port port);
0252 bool intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915,
0253                     enum port port);
0254 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
0255 bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
0256                    struct intel_crtc_state *crtc_state,
0257                    int dsc_max_bpc);
0258 int intel_bios_max_tmds_clock(struct intel_encoder *encoder);
0259 int intel_bios_hdmi_level_shift(struct intel_encoder *encoder);
0260 int intel_bios_dp_max_link_rate(struct intel_encoder *encoder);
0261 int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder);
0262 bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port);
0263 bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port);
0264
0265 const struct intel_bios_encoder_data *
0266 intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port);
0267
0268 bool intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata);
0269 bool intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata);
0270 bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata);
0271 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
0272 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
0273 int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata);
0274 int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata);
0275
0276 #endif /* _INTEL_BIOS_H_ */