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0028 #include <drm/drm_edid.h>
0029 #include <drm/display/drm_dp_helper.h>
0030 #include <drm/display/drm_dsc_helper.h>
0031
0032 #include "display/intel_display.h"
0033 #include "display/intel_display_types.h"
0034 #include "display/intel_gmbus.h"
0035
0036 #include "i915_drv.h"
0037 #include "i915_reg.h"
0038
0039 #define _INTEL_BIOS_PRIVATE
0040 #include "intel_vbt_defs.h"
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065 struct intel_bios_encoder_data {
0066 struct drm_i915_private *i915;
0067
0068 struct child_device_config child;
0069 struct dsc_compression_parameters_entry *dsc;
0070 struct list_head node;
0071 };
0072
0073 #define SLAVE_ADDR1 0x70
0074 #define SLAVE_ADDR2 0x72
0075
0076
0077 static u32 _get_blocksize(const u8 *block_base)
0078 {
0079
0080 if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3)
0081 return *((const u32 *)(block_base + 4));
0082 else
0083 return *((const u16 *)(block_base + 1));
0084 }
0085
0086
0087 static u32 get_blocksize(const void *block_data)
0088 {
0089 return _get_blocksize(block_data - 3);
0090 }
0091
0092 static const void *
0093 find_raw_section(const void *_bdb, enum bdb_block_id section_id)
0094 {
0095 const struct bdb_header *bdb = _bdb;
0096 const u8 *base = _bdb;
0097 int index = 0;
0098 u32 total, current_size;
0099 enum bdb_block_id current_id;
0100
0101
0102 index += bdb->header_size;
0103 total = bdb->bdb_size;
0104
0105
0106 while (index + 3 < total) {
0107 current_id = *(base + index);
0108 current_size = _get_blocksize(base + index);
0109 index += 3;
0110
0111 if (index + current_size > total)
0112 return NULL;
0113
0114 if (current_id == section_id)
0115 return base + index;
0116
0117 index += current_size;
0118 }
0119
0120 return NULL;
0121 }
0122
0123
0124
0125
0126
0127 static u32 raw_block_offset(const void *bdb, enum bdb_block_id section_id)
0128 {
0129 const void *block;
0130
0131 block = find_raw_section(bdb, section_id);
0132 if (!block)
0133 return 0;
0134
0135 return block - bdb;
0136 }
0137
0138
0139 static u32 raw_block_size(const void *bdb, enum bdb_block_id section_id)
0140 {
0141 const void *block;
0142
0143 block = find_raw_section(bdb, section_id);
0144 if (!block)
0145 return 0;
0146
0147 return get_blocksize(block);
0148 }
0149
0150 struct bdb_block_entry {
0151 struct list_head node;
0152 enum bdb_block_id section_id;
0153 u8 data[];
0154 };
0155
0156 static const void *
0157 find_section(struct drm_i915_private *i915,
0158 enum bdb_block_id section_id)
0159 {
0160 struct bdb_block_entry *entry;
0161
0162 list_for_each_entry(entry, &i915->vbt.bdb_blocks, node) {
0163 if (entry->section_id == section_id)
0164 return entry->data + 3;
0165 }
0166
0167 return NULL;
0168 }
0169
0170 static const struct {
0171 enum bdb_block_id section_id;
0172 size_t min_size;
0173 } bdb_blocks[] = {
0174 { .section_id = BDB_GENERAL_FEATURES,
0175 .min_size = sizeof(struct bdb_general_features), },
0176 { .section_id = BDB_GENERAL_DEFINITIONS,
0177 .min_size = sizeof(struct bdb_general_definitions), },
0178 { .section_id = BDB_PSR,
0179 .min_size = sizeof(struct bdb_psr), },
0180 { .section_id = BDB_DRIVER_FEATURES,
0181 .min_size = sizeof(struct bdb_driver_features), },
0182 { .section_id = BDB_SDVO_LVDS_OPTIONS,
0183 .min_size = sizeof(struct bdb_sdvo_lvds_options), },
0184 { .section_id = BDB_SDVO_PANEL_DTDS,
0185 .min_size = sizeof(struct bdb_sdvo_panel_dtds), },
0186 { .section_id = BDB_EDP,
0187 .min_size = sizeof(struct bdb_edp), },
0188 { .section_id = BDB_LVDS_OPTIONS,
0189 .min_size = sizeof(struct bdb_lvds_options), },
0190
0191
0192
0193
0194 { .section_id = BDB_LVDS_LFP_DATA_PTRS,
0195 .min_size = sizeof(struct bdb_lvds_lfp_data_ptrs), },
0196 { .section_id = BDB_LVDS_LFP_DATA,
0197 .min_size = 0, },
0198 { .section_id = BDB_LVDS_BACKLIGHT,
0199 .min_size = sizeof(struct bdb_lfp_backlight_data), },
0200 { .section_id = BDB_LFP_POWER,
0201 .min_size = sizeof(struct bdb_lfp_power), },
0202 { .section_id = BDB_MIPI_CONFIG,
0203 .min_size = sizeof(struct bdb_mipi_config), },
0204 { .section_id = BDB_MIPI_SEQUENCE,
0205 .min_size = sizeof(struct bdb_mipi_sequence) },
0206 { .section_id = BDB_COMPRESSION_PARAMETERS,
0207 .min_size = sizeof(struct bdb_compression_parameters), },
0208 { .section_id = BDB_GENERIC_DTD,
0209 .min_size = sizeof(struct bdb_generic_dtd), },
0210 };
0211
0212 static size_t lfp_data_min_size(struct drm_i915_private *i915)
0213 {
0214 const struct bdb_lvds_lfp_data_ptrs *ptrs;
0215 size_t size;
0216
0217 ptrs = find_section(i915, BDB_LVDS_LFP_DATA_PTRS);
0218 if (!ptrs)
0219 return 0;
0220
0221 size = sizeof(struct bdb_lvds_lfp_data);
0222 if (ptrs->panel_name.table_size)
0223 size = max(size, ptrs->panel_name.offset +
0224 sizeof(struct bdb_lvds_lfp_data_tail));
0225
0226 return size;
0227 }
0228
0229 static bool validate_lfp_data_ptrs(const void *bdb,
0230 const struct bdb_lvds_lfp_data_ptrs *ptrs)
0231 {
0232 int fp_timing_size, dvo_timing_size, panel_pnp_id_size, panel_name_size;
0233 int data_block_size, lfp_data_size;
0234 int i;
0235
0236 data_block_size = raw_block_size(bdb, BDB_LVDS_LFP_DATA);
0237 if (data_block_size == 0)
0238 return false;
0239
0240
0241 if (ptrs->lvds_entries != 3)
0242 return false;
0243
0244 fp_timing_size = ptrs->ptr[0].fp_timing.table_size;
0245 dvo_timing_size = ptrs->ptr[0].dvo_timing.table_size;
0246 panel_pnp_id_size = ptrs->ptr[0].panel_pnp_id.table_size;
0247 panel_name_size = ptrs->panel_name.table_size;
0248
0249
0250 if (fp_timing_size < 32 ||
0251 dvo_timing_size != sizeof(struct lvds_dvo_timing) ||
0252 panel_pnp_id_size != sizeof(struct lvds_pnp_id))
0253 return false;
0254
0255
0256 if (panel_name_size != 0 &&
0257 panel_name_size != sizeof(struct lvds_lfp_panel_name))
0258 return false;
0259
0260 lfp_data_size = ptrs->ptr[1].fp_timing.offset - ptrs->ptr[0].fp_timing.offset;
0261 if (16 * lfp_data_size > data_block_size)
0262 return false;
0263
0264
0265
0266
0267
0268
0269
0270 if (fp_timing_size + dvo_timing_size + panel_pnp_id_size != lfp_data_size &&
0271 fp_timing_size + 6 + dvo_timing_size + panel_pnp_id_size != lfp_data_size)
0272 return false;
0273
0274 if (ptrs->ptr[0].fp_timing.offset + fp_timing_size > ptrs->ptr[0].dvo_timing.offset ||
0275 ptrs->ptr[0].dvo_timing.offset + dvo_timing_size != ptrs->ptr[0].panel_pnp_id.offset ||
0276 ptrs->ptr[0].panel_pnp_id.offset + panel_pnp_id_size != lfp_data_size)
0277 return false;
0278
0279
0280 for (i = 1; i < 16; i++) {
0281 if (ptrs->ptr[i].fp_timing.table_size != fp_timing_size ||
0282 ptrs->ptr[i].dvo_timing.table_size != dvo_timing_size ||
0283 ptrs->ptr[i].panel_pnp_id.table_size != panel_pnp_id_size)
0284 return false;
0285
0286 if (ptrs->ptr[i].fp_timing.offset - ptrs->ptr[i-1].fp_timing.offset != lfp_data_size ||
0287 ptrs->ptr[i].dvo_timing.offset - ptrs->ptr[i-1].dvo_timing.offset != lfp_data_size ||
0288 ptrs->ptr[i].panel_pnp_id.offset - ptrs->ptr[i-1].panel_pnp_id.offset != lfp_data_size)
0289 return false;
0290 }
0291
0292
0293 for (i = 0; i < 16; i++) {
0294 if (ptrs->ptr[i].fp_timing.offset + fp_timing_size > data_block_size ||
0295 ptrs->ptr[i].dvo_timing.offset + dvo_timing_size > data_block_size ||
0296 ptrs->ptr[i].panel_pnp_id.offset + panel_pnp_id_size > data_block_size)
0297 return false;
0298 }
0299
0300 if (ptrs->panel_name.offset + 16 * panel_name_size > data_block_size)
0301 return false;
0302
0303 return true;
0304 }
0305
0306
0307 static bool fixup_lfp_data_ptrs(const void *bdb, void *ptrs_block)
0308 {
0309 struct bdb_lvds_lfp_data_ptrs *ptrs = ptrs_block;
0310 u32 offset;
0311 int i;
0312
0313 offset = raw_block_offset(bdb, BDB_LVDS_LFP_DATA);
0314
0315 for (i = 0; i < 16; i++) {
0316 if (ptrs->ptr[i].fp_timing.offset < offset ||
0317 ptrs->ptr[i].dvo_timing.offset < offset ||
0318 ptrs->ptr[i].panel_pnp_id.offset < offset)
0319 return false;
0320
0321 ptrs->ptr[i].fp_timing.offset -= offset;
0322 ptrs->ptr[i].dvo_timing.offset -= offset;
0323 ptrs->ptr[i].panel_pnp_id.offset -= offset;
0324 }
0325
0326 if (ptrs->panel_name.table_size) {
0327 if (ptrs->panel_name.offset < offset)
0328 return false;
0329
0330 ptrs->panel_name.offset -= offset;
0331 }
0332
0333 return validate_lfp_data_ptrs(bdb, ptrs);
0334 }
0335
0336 static const void *find_fp_timing_terminator(const u8 *data, int size)
0337 {
0338 int i;
0339
0340 for (i = 0; i < size - 1; i++) {
0341 if (data[i] == 0xff && data[i+1] == 0xff)
0342 return &data[i];
0343 }
0344
0345 return NULL;
0346 }
0347
0348 static int make_lfp_data_ptr(struct lvds_lfp_data_ptr_table *table,
0349 int table_size, int total_size)
0350 {
0351 if (total_size < table_size)
0352 return total_size;
0353
0354 table->table_size = table_size;
0355 table->offset = total_size - table_size;
0356
0357 return total_size - table_size;
0358 }
0359
0360 static void next_lfp_data_ptr(struct lvds_lfp_data_ptr_table *next,
0361 const struct lvds_lfp_data_ptr_table *prev,
0362 int size)
0363 {
0364 next->table_size = prev->table_size;
0365 next->offset = prev->offset + size;
0366 }
0367
0368 static void *generate_lfp_data_ptrs(struct drm_i915_private *i915,
0369 const void *bdb)
0370 {
0371 int i, size, table_size, block_size, offset;
0372 const void *t0, *t1, *block;
0373 struct bdb_lvds_lfp_data_ptrs *ptrs;
0374 void *ptrs_block;
0375
0376 block = find_raw_section(bdb, BDB_LVDS_LFP_DATA);
0377 if (!block)
0378 return NULL;
0379
0380 drm_dbg_kms(&i915->drm, "Generating LFP data table pointers\n");
0381
0382 block_size = get_blocksize(block);
0383
0384 size = block_size;
0385 t0 = find_fp_timing_terminator(block, size);
0386 if (!t0)
0387 return NULL;
0388
0389 size -= t0 - block - 2;
0390 t1 = find_fp_timing_terminator(t0 + 2, size);
0391 if (!t1)
0392 return NULL;
0393
0394 size = t1 - t0;
0395 if (size * 16 > block_size)
0396 return NULL;
0397
0398 ptrs_block = kzalloc(sizeof(*ptrs) + 3, GFP_KERNEL);
0399 if (!ptrs_block)
0400 return NULL;
0401
0402 *(u8 *)(ptrs_block + 0) = BDB_LVDS_LFP_DATA_PTRS;
0403 *(u16 *)(ptrs_block + 1) = sizeof(*ptrs);
0404 ptrs = ptrs_block + 3;
0405
0406 table_size = sizeof(struct lvds_pnp_id);
0407 size = make_lfp_data_ptr(&ptrs->ptr[0].panel_pnp_id, table_size, size);
0408
0409 table_size = sizeof(struct lvds_dvo_timing);
0410 size = make_lfp_data_ptr(&ptrs->ptr[0].dvo_timing, table_size, size);
0411
0412 table_size = t0 - block + 2;
0413 size = make_lfp_data_ptr(&ptrs->ptr[0].fp_timing, table_size, size);
0414
0415 if (ptrs->ptr[0].fp_timing.table_size)
0416 ptrs->lvds_entries++;
0417 if (ptrs->ptr[0].dvo_timing.table_size)
0418 ptrs->lvds_entries++;
0419 if (ptrs->ptr[0].panel_pnp_id.table_size)
0420 ptrs->lvds_entries++;
0421
0422 if (size != 0 || ptrs->lvds_entries != 3) {
0423 kfree(ptrs);
0424 return NULL;
0425 }
0426
0427 size = t1 - t0;
0428 for (i = 1; i < 16; i++) {
0429 next_lfp_data_ptr(&ptrs->ptr[i].fp_timing, &ptrs->ptr[i-1].fp_timing, size);
0430 next_lfp_data_ptr(&ptrs->ptr[i].dvo_timing, &ptrs->ptr[i-1].dvo_timing, size);
0431 next_lfp_data_ptr(&ptrs->ptr[i].panel_pnp_id, &ptrs->ptr[i-1].panel_pnp_id, size);
0432 }
0433
0434 size = t1 - t0;
0435 table_size = sizeof(struct lvds_lfp_panel_name);
0436
0437 if (16 * (size + table_size) <= block_size) {
0438 ptrs->panel_name.table_size = table_size;
0439 ptrs->panel_name.offset = size * 16;
0440 }
0441
0442 offset = block - bdb;
0443
0444 for (i = 0; i < 16; i++) {
0445 ptrs->ptr[i].fp_timing.offset += offset;
0446 ptrs->ptr[i].dvo_timing.offset += offset;
0447 ptrs->ptr[i].panel_pnp_id.offset += offset;
0448 }
0449
0450 if (ptrs->panel_name.table_size)
0451 ptrs->panel_name.offset += offset;
0452
0453 return ptrs_block;
0454 }
0455
0456 static void
0457 init_bdb_block(struct drm_i915_private *i915,
0458 const void *bdb, enum bdb_block_id section_id,
0459 size_t min_size)
0460 {
0461 struct bdb_block_entry *entry;
0462 void *temp_block = NULL;
0463 const void *block;
0464 size_t block_size;
0465
0466 block = find_raw_section(bdb, section_id);
0467
0468
0469 if (!block && section_id == BDB_LVDS_LFP_DATA_PTRS) {
0470 temp_block = generate_lfp_data_ptrs(i915, bdb);
0471 if (temp_block)
0472 block = temp_block + 3;
0473 }
0474 if (!block)
0475 return;
0476
0477 drm_WARN(&i915->drm, min_size == 0,
0478 "Block %d min_size is zero\n", section_id);
0479
0480 block_size = get_blocksize(block);
0481
0482
0483
0484
0485
0486 if (section_id == BDB_MIPI_SEQUENCE && *(const u8 *)block >= 3)
0487 block_size += 5;
0488
0489 entry = kzalloc(struct_size(entry, data, max(min_size, block_size) + 3),
0490 GFP_KERNEL);
0491 if (!entry) {
0492 kfree(temp_block);
0493 return;
0494 }
0495
0496 entry->section_id = section_id;
0497 memcpy(entry->data, block - 3, block_size + 3);
0498
0499 kfree(temp_block);
0500
0501 drm_dbg_kms(&i915->drm, "Found BDB block %d (size %zu, min size %zu)\n",
0502 section_id, block_size, min_size);
0503
0504 if (section_id == BDB_LVDS_LFP_DATA_PTRS &&
0505 !fixup_lfp_data_ptrs(bdb, entry->data + 3)) {
0506 drm_err(&i915->drm, "VBT has malformed LFP data table pointers\n");
0507 kfree(entry);
0508 return;
0509 }
0510
0511 list_add_tail(&entry->node, &i915->vbt.bdb_blocks);
0512 }
0513
0514 static void init_bdb_blocks(struct drm_i915_private *i915,
0515 const void *bdb)
0516 {
0517 int i;
0518
0519 for (i = 0; i < ARRAY_SIZE(bdb_blocks); i++) {
0520 enum bdb_block_id section_id = bdb_blocks[i].section_id;
0521 size_t min_size = bdb_blocks[i].min_size;
0522
0523 if (section_id == BDB_LVDS_LFP_DATA)
0524 min_size = lfp_data_min_size(i915);
0525
0526 init_bdb_block(i915, bdb, section_id, min_size);
0527 }
0528 }
0529
0530 static void
0531 fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
0532 const struct lvds_dvo_timing *dvo_timing)
0533 {
0534 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
0535 dvo_timing->hactive_lo;
0536 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
0537 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
0538 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
0539 ((dvo_timing->hsync_pulse_width_hi << 8) |
0540 dvo_timing->hsync_pulse_width_lo);
0541 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
0542 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
0543
0544 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
0545 dvo_timing->vactive_lo;
0546 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
0547 ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
0548 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
0549 ((dvo_timing->vsync_pulse_width_hi << 4) |
0550 dvo_timing->vsync_pulse_width_lo);
0551 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
0552 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
0553 panel_fixed_mode->clock = dvo_timing->clock * 10;
0554 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
0555
0556 if (dvo_timing->hsync_positive)
0557 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
0558 else
0559 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
0560
0561 if (dvo_timing->vsync_positive)
0562 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
0563 else
0564 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
0565
0566 panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) |
0567 dvo_timing->himage_lo;
0568 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |
0569 dvo_timing->vimage_lo;
0570
0571
0572 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
0573 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
0574 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
0575 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
0576
0577 drm_mode_set_name(panel_fixed_mode);
0578 }
0579
0580 static const struct lvds_dvo_timing *
0581 get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *data,
0582 const struct bdb_lvds_lfp_data_ptrs *ptrs,
0583 int index)
0584 {
0585 return (const void *)data + ptrs->ptr[index].dvo_timing.offset;
0586 }
0587
0588 static const struct lvds_fp_timing *
0589 get_lvds_fp_timing(const struct bdb_lvds_lfp_data *data,
0590 const struct bdb_lvds_lfp_data_ptrs *ptrs,
0591 int index)
0592 {
0593 return (const void *)data + ptrs->ptr[index].fp_timing.offset;
0594 }
0595
0596 static const struct lvds_pnp_id *
0597 get_lvds_pnp_id(const struct bdb_lvds_lfp_data *data,
0598 const struct bdb_lvds_lfp_data_ptrs *ptrs,
0599 int index)
0600 {
0601 return (const void *)data + ptrs->ptr[index].panel_pnp_id.offset;
0602 }
0603
0604 static const struct bdb_lvds_lfp_data_tail *
0605 get_lfp_data_tail(const struct bdb_lvds_lfp_data *data,
0606 const struct bdb_lvds_lfp_data_ptrs *ptrs)
0607 {
0608 if (ptrs->panel_name.table_size)
0609 return (const void *)data + ptrs->panel_name.offset;
0610 else
0611 return NULL;
0612 }
0613
0614 static int opregion_get_panel_type(struct drm_i915_private *i915,
0615 const struct intel_bios_encoder_data *devdata,
0616 const struct edid *edid)
0617 {
0618 return intel_opregion_get_panel_type(i915);
0619 }
0620
0621 static int vbt_get_panel_type(struct drm_i915_private *i915,
0622 const struct intel_bios_encoder_data *devdata,
0623 const struct edid *edid)
0624 {
0625 const struct bdb_lvds_options *lvds_options;
0626
0627 lvds_options = find_section(i915, BDB_LVDS_OPTIONS);
0628 if (!lvds_options)
0629 return -1;
0630
0631 if (lvds_options->panel_type > 0xf &&
0632 lvds_options->panel_type != 0xff) {
0633 drm_dbg_kms(&i915->drm, "Invalid VBT panel type 0x%x\n",
0634 lvds_options->panel_type);
0635 return -1;
0636 }
0637
0638 if (devdata && devdata->child.handle == DEVICE_HANDLE_LFP2)
0639 return lvds_options->panel_type2;
0640
0641 drm_WARN_ON(&i915->drm, devdata && devdata->child.handle != DEVICE_HANDLE_LFP1);
0642
0643 return lvds_options->panel_type;
0644 }
0645
0646 static int pnpid_get_panel_type(struct drm_i915_private *i915,
0647 const struct intel_bios_encoder_data *devdata,
0648 const struct edid *edid)
0649 {
0650 const struct bdb_lvds_lfp_data *data;
0651 const struct bdb_lvds_lfp_data_ptrs *ptrs;
0652 const struct lvds_pnp_id *edid_id;
0653 struct lvds_pnp_id edid_id_nodate;
0654 int i, best = -1;
0655
0656 if (!edid)
0657 return -1;
0658
0659 edid_id = (const void *)&edid->mfg_id[0];
0660
0661 edid_id_nodate = *edid_id;
0662 edid_id_nodate.mfg_week = 0;
0663 edid_id_nodate.mfg_year = 0;
0664
0665 ptrs = find_section(i915, BDB_LVDS_LFP_DATA_PTRS);
0666 if (!ptrs)
0667 return -1;
0668
0669 data = find_section(i915, BDB_LVDS_LFP_DATA);
0670 if (!data)
0671 return -1;
0672
0673 for (i = 0; i < 16; i++) {
0674 const struct lvds_pnp_id *vbt_id =
0675 get_lvds_pnp_id(data, ptrs, i);
0676
0677
0678 if (!memcmp(vbt_id, edid_id, sizeof(*vbt_id)))
0679 return i;
0680
0681
0682
0683
0684
0685 if (best < 0 &&
0686 !memcmp(vbt_id, &edid_id_nodate, sizeof(*vbt_id)))
0687 best = i;
0688 }
0689
0690 return best;
0691 }
0692
0693 static int fallback_get_panel_type(struct drm_i915_private *i915,
0694 const struct intel_bios_encoder_data *devdata,
0695 const struct edid *edid)
0696 {
0697 return 0;
0698 }
0699
0700 enum panel_type {
0701 PANEL_TYPE_OPREGION,
0702 PANEL_TYPE_VBT,
0703 PANEL_TYPE_PNPID,
0704 PANEL_TYPE_FALLBACK,
0705 };
0706
0707 static int get_panel_type(struct drm_i915_private *i915,
0708 const struct intel_bios_encoder_data *devdata,
0709 const struct edid *edid)
0710 {
0711 struct {
0712 const char *name;
0713 int (*get_panel_type)(struct drm_i915_private *i915,
0714 const struct intel_bios_encoder_data *devdata,
0715 const struct edid *edid);
0716 int panel_type;
0717 } panel_types[] = {
0718 [PANEL_TYPE_OPREGION] = {
0719 .name = "OpRegion",
0720 .get_panel_type = opregion_get_panel_type,
0721 },
0722 [PANEL_TYPE_VBT] = {
0723 .name = "VBT",
0724 .get_panel_type = vbt_get_panel_type,
0725 },
0726 [PANEL_TYPE_PNPID] = {
0727 .name = "PNPID",
0728 .get_panel_type = pnpid_get_panel_type,
0729 },
0730 [PANEL_TYPE_FALLBACK] = {
0731 .name = "fallback",
0732 .get_panel_type = fallback_get_panel_type,
0733 },
0734 };
0735 int i;
0736
0737 for (i = 0; i < ARRAY_SIZE(panel_types); i++) {
0738 panel_types[i].panel_type = panel_types[i].get_panel_type(i915, devdata, edid);
0739
0740 drm_WARN_ON(&i915->drm, panel_types[i].panel_type > 0xf &&
0741 panel_types[i].panel_type != 0xff);
0742
0743 if (panel_types[i].panel_type >= 0)
0744 drm_dbg_kms(&i915->drm, "Panel type (%s): %d\n",
0745 panel_types[i].name, panel_types[i].panel_type);
0746 }
0747
0748 if (panel_types[PANEL_TYPE_OPREGION].panel_type >= 0)
0749 i = PANEL_TYPE_OPREGION;
0750 else if (panel_types[PANEL_TYPE_VBT].panel_type == 0xff &&
0751 panel_types[PANEL_TYPE_PNPID].panel_type >= 0)
0752 i = PANEL_TYPE_PNPID;
0753 else if (panel_types[PANEL_TYPE_VBT].panel_type != 0xff &&
0754 panel_types[PANEL_TYPE_VBT].panel_type >= 0)
0755 i = PANEL_TYPE_VBT;
0756 else
0757 i = PANEL_TYPE_FALLBACK;
0758
0759 drm_dbg_kms(&i915->drm, "Selected panel type (%s): %d\n",
0760 panel_types[i].name, panel_types[i].panel_type);
0761
0762 return panel_types[i].panel_type;
0763 }
0764
0765 static unsigned int panel_bits(unsigned int value, int panel_type, int num_bits)
0766 {
0767 return (value >> (panel_type * num_bits)) & (BIT(num_bits) - 1);
0768 }
0769
0770 static bool panel_bool(unsigned int value, int panel_type)
0771 {
0772 return panel_bits(value, panel_type, 1);
0773 }
0774
0775
0776 static void
0777 parse_panel_options(struct drm_i915_private *i915,
0778 struct intel_panel *panel)
0779 {
0780 const struct bdb_lvds_options *lvds_options;
0781 int panel_type = panel->vbt.panel_type;
0782 int drrs_mode;
0783
0784 lvds_options = find_section(i915, BDB_LVDS_OPTIONS);
0785 if (!lvds_options)
0786 return;
0787
0788 panel->vbt.lvds_dither = lvds_options->pixel_dither;
0789
0790
0791
0792
0793
0794
0795 if (get_blocksize(lvds_options) < 16)
0796 return;
0797
0798 drrs_mode = panel_bits(lvds_options->dps_panel_type_bits,
0799 panel_type, 2);
0800
0801
0802
0803
0804
0805 switch (drrs_mode) {
0806 case 0:
0807 panel->vbt.drrs_type = DRRS_TYPE_STATIC;
0808 drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n");
0809 break;
0810 case 2:
0811 panel->vbt.drrs_type = DRRS_TYPE_SEAMLESS;
0812 drm_dbg_kms(&i915->drm,
0813 "DRRS supported mode is seamless\n");
0814 break;
0815 default:
0816 panel->vbt.drrs_type = DRRS_TYPE_NONE;
0817 drm_dbg_kms(&i915->drm,
0818 "DRRS not supported (VBT input)\n");
0819 break;
0820 }
0821 }
0822
0823 static void
0824 parse_lfp_panel_dtd(struct drm_i915_private *i915,
0825 struct intel_panel *panel,
0826 const struct bdb_lvds_lfp_data *lvds_lfp_data,
0827 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs)
0828 {
0829 const struct lvds_dvo_timing *panel_dvo_timing;
0830 const struct lvds_fp_timing *fp_timing;
0831 struct drm_display_mode *panel_fixed_mode;
0832 int panel_type = panel->vbt.panel_type;
0833
0834 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
0835 lvds_lfp_data_ptrs,
0836 panel_type);
0837
0838 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
0839 if (!panel_fixed_mode)
0840 return;
0841
0842 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
0843
0844 panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
0845
0846 drm_dbg_kms(&i915->drm,
0847 "Found panel mode in BIOS VBT legacy lfp table: " DRM_MODE_FMT "\n",
0848 DRM_MODE_ARG(panel_fixed_mode));
0849
0850 fp_timing = get_lvds_fp_timing(lvds_lfp_data,
0851 lvds_lfp_data_ptrs,
0852 panel_type);
0853
0854
0855 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
0856 fp_timing->y_res == panel_fixed_mode->vdisplay) {
0857 panel->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
0858 drm_dbg_kms(&i915->drm,
0859 "VBT initial LVDS value %x\n",
0860 panel->vbt.bios_lvds_val);
0861 }
0862 }
0863
0864 static void
0865 parse_lfp_data(struct drm_i915_private *i915,
0866 struct intel_panel *panel)
0867 {
0868 const struct bdb_lvds_lfp_data *data;
0869 const struct bdb_lvds_lfp_data_tail *tail;
0870 const struct bdb_lvds_lfp_data_ptrs *ptrs;
0871 int panel_type = panel->vbt.panel_type;
0872
0873 ptrs = find_section(i915, BDB_LVDS_LFP_DATA_PTRS);
0874 if (!ptrs)
0875 return;
0876
0877 data = find_section(i915, BDB_LVDS_LFP_DATA);
0878 if (!data)
0879 return;
0880
0881 if (!panel->vbt.lfp_lvds_vbt_mode)
0882 parse_lfp_panel_dtd(i915, panel, data, ptrs);
0883
0884 tail = get_lfp_data_tail(data, ptrs);
0885 if (!tail)
0886 return;
0887
0888 if (i915->vbt.version >= 188) {
0889 panel->vbt.seamless_drrs_min_refresh_rate =
0890 tail->seamless_drrs_min_refresh_rate[panel_type];
0891 drm_dbg_kms(&i915->drm,
0892 "Seamless DRRS min refresh rate: %d Hz\n",
0893 panel->vbt.seamless_drrs_min_refresh_rate);
0894 }
0895 }
0896
0897 static void
0898 parse_generic_dtd(struct drm_i915_private *i915,
0899 struct intel_panel *panel)
0900 {
0901 const struct bdb_generic_dtd *generic_dtd;
0902 const struct generic_dtd_entry *dtd;
0903 struct drm_display_mode *panel_fixed_mode;
0904 int num_dtd;
0905
0906
0907
0908
0909
0910
0911
0912
0913
0914 if (i915->vbt.version < 229)
0915 return;
0916
0917 generic_dtd = find_section(i915, BDB_GENERIC_DTD);
0918 if (!generic_dtd)
0919 return;
0920
0921 if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) {
0922 drm_err(&i915->drm, "GDTD size %u is too small.\n",
0923 generic_dtd->gdtd_size);
0924 return;
0925 } else if (generic_dtd->gdtd_size !=
0926 sizeof(struct generic_dtd_entry)) {
0927 drm_err(&i915->drm, "Unexpected GDTD size %u\n",
0928 generic_dtd->gdtd_size);
0929
0930 }
0931
0932 num_dtd = (get_blocksize(generic_dtd) -
0933 sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;
0934 if (panel->vbt.panel_type >= num_dtd) {
0935 drm_err(&i915->drm,
0936 "Panel type %d not found in table of %d DTD's\n",
0937 panel->vbt.panel_type, num_dtd);
0938 return;
0939 }
0940
0941 dtd = &generic_dtd->dtd[panel->vbt.panel_type];
0942
0943 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
0944 if (!panel_fixed_mode)
0945 return;
0946
0947 panel_fixed_mode->hdisplay = dtd->hactive;
0948 panel_fixed_mode->hsync_start =
0949 panel_fixed_mode->hdisplay + dtd->hfront_porch;
0950 panel_fixed_mode->hsync_end =
0951 panel_fixed_mode->hsync_start + dtd->hsync;
0952 panel_fixed_mode->htotal =
0953 panel_fixed_mode->hdisplay + dtd->hblank;
0954
0955 panel_fixed_mode->vdisplay = dtd->vactive;
0956 panel_fixed_mode->vsync_start =
0957 panel_fixed_mode->vdisplay + dtd->vfront_porch;
0958 panel_fixed_mode->vsync_end =
0959 panel_fixed_mode->vsync_start + dtd->vsync;
0960 panel_fixed_mode->vtotal =
0961 panel_fixed_mode->vdisplay + dtd->vblank;
0962
0963 panel_fixed_mode->clock = dtd->pixel_clock;
0964 panel_fixed_mode->width_mm = dtd->width_mm;
0965 panel_fixed_mode->height_mm = dtd->height_mm;
0966
0967 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
0968 drm_mode_set_name(panel_fixed_mode);
0969
0970 if (dtd->hsync_positive_polarity)
0971 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
0972 else
0973 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
0974
0975 if (dtd->vsync_positive_polarity)
0976 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
0977 else
0978 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
0979
0980 drm_dbg_kms(&i915->drm,
0981 "Found panel mode in BIOS VBT generic dtd table: " DRM_MODE_FMT "\n",
0982 DRM_MODE_ARG(panel_fixed_mode));
0983
0984 panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
0985 }
0986
0987 static void
0988 parse_lfp_backlight(struct drm_i915_private *i915,
0989 struct intel_panel *panel)
0990 {
0991 const struct bdb_lfp_backlight_data *backlight_data;
0992 const struct lfp_backlight_data_entry *entry;
0993 int panel_type = panel->vbt.panel_type;
0994 u16 level;
0995
0996 backlight_data = find_section(i915, BDB_LVDS_BACKLIGHT);
0997 if (!backlight_data)
0998 return;
0999
1000 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
1001 drm_dbg_kms(&i915->drm,
1002 "Unsupported backlight data entry size %u\n",
1003 backlight_data->entry_size);
1004 return;
1005 }
1006
1007 entry = &backlight_data->data[panel_type];
1008
1009 panel->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
1010 if (!panel->vbt.backlight.present) {
1011 drm_dbg_kms(&i915->drm,
1012 "PWM backlight not present in VBT (type %u)\n",
1013 entry->type);
1014 return;
1015 }
1016
1017 panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
1018 if (i915->vbt.version >= 191) {
1019 size_t exp_size;
1020
1021 if (i915->vbt.version >= 236)
1022 exp_size = sizeof(struct bdb_lfp_backlight_data);
1023 else if (i915->vbt.version >= 234)
1024 exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;
1025 else
1026 exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;
1027
1028 if (get_blocksize(backlight_data) >= exp_size) {
1029 const struct lfp_backlight_control_method *method;
1030
1031 method = &backlight_data->backlight_control[panel_type];
1032 panel->vbt.backlight.type = method->type;
1033 panel->vbt.backlight.controller = method->controller;
1034 }
1035 }
1036
1037 panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
1038 panel->vbt.backlight.active_low_pwm = entry->active_low_pwm;
1039
1040 if (i915->vbt.version >= 234) {
1041 u16 min_level;
1042 bool scale;
1043
1044 level = backlight_data->brightness_level[panel_type].level;
1045 min_level = backlight_data->brightness_min_level[panel_type].level;
1046
1047 if (i915->vbt.version >= 236)
1048 scale = backlight_data->brightness_precision_bits[panel_type] == 16;
1049 else
1050 scale = level > 255;
1051
1052 if (scale)
1053 min_level = min_level / 255;
1054
1055 if (min_level > 255) {
1056 drm_warn(&i915->drm, "Brightness min level > 255\n");
1057 level = 255;
1058 }
1059 panel->vbt.backlight.min_brightness = min_level;
1060
1061 panel->vbt.backlight.brightness_precision_bits =
1062 backlight_data->brightness_precision_bits[panel_type];
1063 } else {
1064 level = backlight_data->level[panel_type];
1065 panel->vbt.backlight.min_brightness = entry->min_brightness;
1066 }
1067
1068 drm_dbg_kms(&i915->drm,
1069 "VBT backlight PWM modulation frequency %u Hz, "
1070 "active %s, min brightness %u, level %u, controller %u\n",
1071 panel->vbt.backlight.pwm_freq_hz,
1072 panel->vbt.backlight.active_low_pwm ? "low" : "high",
1073 panel->vbt.backlight.min_brightness,
1074 level,
1075 panel->vbt.backlight.controller);
1076 }
1077
1078
1079 static void
1080 parse_sdvo_panel_data(struct drm_i915_private *i915,
1081 struct intel_panel *panel)
1082 {
1083 const struct bdb_sdvo_panel_dtds *dtds;
1084 struct drm_display_mode *panel_fixed_mode;
1085 int index;
1086
1087 index = i915->params.vbt_sdvo_panel_type;
1088 if (index == -2) {
1089 drm_dbg_kms(&i915->drm,
1090 "Ignore SDVO panel mode from BIOS VBT tables.\n");
1091 return;
1092 }
1093
1094 if (index == -1) {
1095 const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
1096
1097 sdvo_lvds_options = find_section(i915, BDB_SDVO_LVDS_OPTIONS);
1098 if (!sdvo_lvds_options)
1099 return;
1100
1101 index = sdvo_lvds_options->panel_type;
1102 }
1103
1104 dtds = find_section(i915, BDB_SDVO_PANEL_DTDS);
1105 if (!dtds)
1106 return;
1107
1108 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
1109 if (!panel_fixed_mode)
1110 return;
1111
1112 fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]);
1113
1114 panel->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
1115
1116 drm_dbg_kms(&i915->drm,
1117 "Found SDVO panel mode in BIOS VBT tables: " DRM_MODE_FMT "\n",
1118 DRM_MODE_ARG(panel_fixed_mode));
1119 }
1120
1121 static int intel_bios_ssc_frequency(struct drm_i915_private *i915,
1122 bool alternate)
1123 {
1124 switch (DISPLAY_VER(i915)) {
1125 case 2:
1126 return alternate ? 66667 : 48000;
1127 case 3:
1128 case 4:
1129 return alternate ? 100000 : 96000;
1130 default:
1131 return alternate ? 100000 : 120000;
1132 }
1133 }
1134
1135 static void
1136 parse_general_features(struct drm_i915_private *i915)
1137 {
1138 const struct bdb_general_features *general;
1139
1140 general = find_section(i915, BDB_GENERAL_FEATURES);
1141 if (!general)
1142 return;
1143
1144 i915->vbt.int_tv_support = general->int_tv_support;
1145
1146 if (i915->vbt.version >= 155 &&
1147 (HAS_DDI(i915) || IS_VALLEYVIEW(i915)))
1148 i915->vbt.int_crt_support = general->int_crt_support;
1149 i915->vbt.lvds_use_ssc = general->enable_ssc;
1150 i915->vbt.lvds_ssc_freq =
1151 intel_bios_ssc_frequency(i915, general->ssc_freq);
1152 i915->vbt.display_clock_mode = general->display_clock_mode;
1153 i915->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
1154 if (i915->vbt.version >= 181) {
1155 i915->vbt.orientation = general->rotate_180 ?
1156 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP :
1157 DRM_MODE_PANEL_ORIENTATION_NORMAL;
1158 } else {
1159 i915->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1160 }
1161
1162 if (i915->vbt.version >= 249 && general->afc_startup_config) {
1163 i915->vbt.override_afc_startup = true;
1164 i915->vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7;
1165 }
1166
1167 drm_dbg_kms(&i915->drm,
1168 "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
1169 i915->vbt.int_tv_support,
1170 i915->vbt.int_crt_support,
1171 i915->vbt.lvds_use_ssc,
1172 i915->vbt.lvds_ssc_freq,
1173 i915->vbt.display_clock_mode,
1174 i915->vbt.fdi_rx_polarity_inverted);
1175 }
1176
1177 static const struct child_device_config *
1178 child_device_ptr(const struct bdb_general_definitions *defs, int i)
1179 {
1180 return (const void *) &defs->devices[i * defs->child_dev_size];
1181 }
1182
1183 static void
1184 parse_sdvo_device_mapping(struct drm_i915_private *i915)
1185 {
1186 struct sdvo_device_mapping *mapping;
1187 const struct intel_bios_encoder_data *devdata;
1188 const struct child_device_config *child;
1189 int count = 0;
1190
1191
1192
1193
1194
1195 if (!IS_DISPLAY_VER(i915, 3, 7)) {
1196 drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n");
1197 return;
1198 }
1199
1200 list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
1201 child = &devdata->child;
1202
1203 if (child->slave_addr != SLAVE_ADDR1 &&
1204 child->slave_addr != SLAVE_ADDR2) {
1205
1206
1207
1208
1209 continue;
1210 }
1211 if (child->dvo_port != DEVICE_PORT_DVOB &&
1212 child->dvo_port != DEVICE_PORT_DVOC) {
1213
1214 drm_dbg_kms(&i915->drm,
1215 "Incorrect SDVO port. Skip it\n");
1216 continue;
1217 }
1218 drm_dbg_kms(&i915->drm,
1219 "the SDVO device with slave addr %2x is found on"
1220 " %s port\n",
1221 child->slave_addr,
1222 (child->dvo_port == DEVICE_PORT_DVOB) ?
1223 "SDVOB" : "SDVOC");
1224 mapping = &i915->vbt.sdvo_mappings[child->dvo_port - 1];
1225 if (!mapping->initialized) {
1226 mapping->dvo_port = child->dvo_port;
1227 mapping->slave_addr = child->slave_addr;
1228 mapping->dvo_wiring = child->dvo_wiring;
1229 mapping->ddc_pin = child->ddc_pin;
1230 mapping->i2c_pin = child->i2c_pin;
1231 mapping->initialized = 1;
1232 drm_dbg_kms(&i915->drm,
1233 "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
1234 mapping->dvo_port, mapping->slave_addr,
1235 mapping->dvo_wiring, mapping->ddc_pin,
1236 mapping->i2c_pin);
1237 } else {
1238 drm_dbg_kms(&i915->drm,
1239 "Maybe one SDVO port is shared by "
1240 "two SDVO device.\n");
1241 }
1242 if (child->slave2_addr) {
1243
1244
1245 drm_dbg_kms(&i915->drm,
1246 "there exists the slave2_addr. Maybe this"
1247 " is a SDVO device with multiple inputs.\n");
1248 }
1249 count++;
1250 }
1251
1252 if (!count) {
1253
1254 drm_dbg_kms(&i915->drm,
1255 "No SDVO device info is found in VBT\n");
1256 }
1257 }
1258
1259 static void
1260 parse_driver_features(struct drm_i915_private *i915)
1261 {
1262 const struct bdb_driver_features *driver;
1263
1264 driver = find_section(i915, BDB_DRIVER_FEATURES);
1265 if (!driver)
1266 return;
1267
1268 if (DISPLAY_VER(i915) >= 5) {
1269
1270
1271
1272
1273
1274 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS)
1275 i915->vbt.int_lvds_support = 0;
1276 } else {
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288 if (i915->vbt.version >= 134 &&
1289 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS &&
1290 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
1291 i915->vbt.int_lvds_support = 0;
1292 }
1293 }
1294
1295 static void
1296 parse_panel_driver_features(struct drm_i915_private *i915,
1297 struct intel_panel *panel)
1298 {
1299 const struct bdb_driver_features *driver;
1300
1301 driver = find_section(i915, BDB_DRIVER_FEATURES);
1302 if (!driver)
1303 return;
1304
1305 if (i915->vbt.version < 228) {
1306 drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n",
1307 driver->drrs_enabled);
1308
1309
1310
1311
1312
1313
1314 if (!driver->drrs_enabled && panel->vbt.drrs_type != DRRS_TYPE_NONE) {
1315
1316
1317
1318
1319 if (driver->dmrrs_enabled)
1320 panel->vbt.drrs_type = DRRS_TYPE_STATIC;
1321 else
1322 panel->vbt.drrs_type = DRRS_TYPE_NONE;
1323 }
1324
1325 panel->vbt.psr.enable = driver->psr_enabled;
1326 }
1327 }
1328
1329 static void
1330 parse_power_conservation_features(struct drm_i915_private *i915,
1331 struct intel_panel *panel)
1332 {
1333 const struct bdb_lfp_power *power;
1334 u8 panel_type = panel->vbt.panel_type;
1335
1336 panel->vbt.vrr = true;
1337
1338 if (i915->vbt.version < 228)
1339 return;
1340
1341 power = find_section(i915, BDB_LFP_POWER);
1342 if (!power)
1343 return;
1344
1345 panel->vbt.psr.enable = panel_bool(power->psr, panel_type);
1346
1347
1348
1349
1350
1351
1352
1353 if (!panel_bool(power->drrs, panel_type) && panel->vbt.drrs_type != DRRS_TYPE_NONE) {
1354
1355
1356
1357
1358 if (panel_bool(power->dmrrs, panel_type))
1359 panel->vbt.drrs_type = DRRS_TYPE_STATIC;
1360 else
1361 panel->vbt.drrs_type = DRRS_TYPE_NONE;
1362 }
1363
1364 if (i915->vbt.version >= 232)
1365 panel->vbt.edp.hobl = panel_bool(power->hobl, panel_type);
1366
1367 if (i915->vbt.version >= 233)
1368 panel->vbt.vrr = panel_bool(power->vrr_feature_enabled,
1369 panel_type);
1370 }
1371
1372 static void
1373 parse_edp(struct drm_i915_private *i915,
1374 struct intel_panel *panel)
1375 {
1376 const struct bdb_edp *edp;
1377 const struct edp_power_seq *edp_pps;
1378 const struct edp_fast_link_params *edp_link_params;
1379 int panel_type = panel->vbt.panel_type;
1380
1381 edp = find_section(i915, BDB_EDP);
1382 if (!edp)
1383 return;
1384
1385 switch (panel_bits(edp->color_depth, panel_type, 2)) {
1386 case EDP_18BPP:
1387 panel->vbt.edp.bpp = 18;
1388 break;
1389 case EDP_24BPP:
1390 panel->vbt.edp.bpp = 24;
1391 break;
1392 case EDP_30BPP:
1393 panel->vbt.edp.bpp = 30;
1394 break;
1395 }
1396
1397
1398 edp_pps = &edp->power_seqs[panel_type];
1399 edp_link_params = &edp->fast_link_params[panel_type];
1400
1401 panel->vbt.edp.pps = *edp_pps;
1402
1403 if (i915->vbt.version >= 224) {
1404 panel->vbt.edp.rate =
1405 edp->edp_fast_link_training_rate[panel_type] * 20;
1406 } else {
1407 switch (edp_link_params->rate) {
1408 case EDP_RATE_1_62:
1409 panel->vbt.edp.rate = 162000;
1410 break;
1411 case EDP_RATE_2_7:
1412 panel->vbt.edp.rate = 270000;
1413 break;
1414 case EDP_RATE_5_4:
1415 panel->vbt.edp.rate = 540000;
1416 break;
1417 default:
1418 drm_dbg_kms(&i915->drm,
1419 "VBT has unknown eDP link rate value %u\n",
1420 edp_link_params->rate);
1421 break;
1422 }
1423 }
1424
1425 switch (edp_link_params->lanes) {
1426 case EDP_LANE_1:
1427 panel->vbt.edp.lanes = 1;
1428 break;
1429 case EDP_LANE_2:
1430 panel->vbt.edp.lanes = 2;
1431 break;
1432 case EDP_LANE_4:
1433 panel->vbt.edp.lanes = 4;
1434 break;
1435 default:
1436 drm_dbg_kms(&i915->drm,
1437 "VBT has unknown eDP lane count value %u\n",
1438 edp_link_params->lanes);
1439 break;
1440 }
1441
1442 switch (edp_link_params->preemphasis) {
1443 case EDP_PREEMPHASIS_NONE:
1444 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
1445 break;
1446 case EDP_PREEMPHASIS_3_5dB:
1447 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
1448 break;
1449 case EDP_PREEMPHASIS_6dB:
1450 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
1451 break;
1452 case EDP_PREEMPHASIS_9_5dB:
1453 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
1454 break;
1455 default:
1456 drm_dbg_kms(&i915->drm,
1457 "VBT has unknown eDP pre-emphasis value %u\n",
1458 edp_link_params->preemphasis);
1459 break;
1460 }
1461
1462 switch (edp_link_params->vswing) {
1463 case EDP_VSWING_0_4V:
1464 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
1465 break;
1466 case EDP_VSWING_0_6V:
1467 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
1468 break;
1469 case EDP_VSWING_0_8V:
1470 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1471 break;
1472 case EDP_VSWING_1_2V:
1473 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1474 break;
1475 default:
1476 drm_dbg_kms(&i915->drm,
1477 "VBT has unknown eDP voltage swing value %u\n",
1478 edp_link_params->vswing);
1479 break;
1480 }
1481
1482 if (i915->vbt.version >= 173) {
1483 u8 vswing;
1484
1485
1486 if (i915->params.edp_vswing) {
1487 panel->vbt.edp.low_vswing =
1488 i915->params.edp_vswing == 1;
1489 } else {
1490 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
1491 panel->vbt.edp.low_vswing = vswing == 0;
1492 }
1493 }
1494
1495 panel->vbt.edp.drrs_msa_timing_delay =
1496 panel_bits(edp->sdrrs_msa_timing_delay, panel_type, 2);
1497
1498 if (i915->vbt.version >= 244)
1499 panel->vbt.edp.max_link_rate =
1500 edp->edp_max_port_link_rate[panel_type] * 20;
1501 }
1502
1503 static void
1504 parse_psr(struct drm_i915_private *i915,
1505 struct intel_panel *panel)
1506 {
1507 const struct bdb_psr *psr;
1508 const struct psr_table *psr_table;
1509 int panel_type = panel->vbt.panel_type;
1510
1511 psr = find_section(i915, BDB_PSR);
1512 if (!psr) {
1513 drm_dbg_kms(&i915->drm, "No PSR BDB found.\n");
1514 return;
1515 }
1516
1517 psr_table = &psr->psr_table[panel_type];
1518
1519 panel->vbt.psr.full_link = psr_table->full_link;
1520 panel->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
1521
1522
1523 panel->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
1524 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
1525
1526
1527
1528
1529
1530 if (i915->vbt.version >= 205 &&
1531 (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
1532 switch (psr_table->tp1_wakeup_time) {
1533 case 0:
1534 panel->vbt.psr.tp1_wakeup_time_us = 500;
1535 break;
1536 case 1:
1537 panel->vbt.psr.tp1_wakeup_time_us = 100;
1538 break;
1539 case 3:
1540 panel->vbt.psr.tp1_wakeup_time_us = 0;
1541 break;
1542 default:
1543 drm_dbg_kms(&i915->drm,
1544 "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
1545 psr_table->tp1_wakeup_time);
1546 fallthrough;
1547 case 2:
1548 panel->vbt.psr.tp1_wakeup_time_us = 2500;
1549 break;
1550 }
1551
1552 switch (psr_table->tp2_tp3_wakeup_time) {
1553 case 0:
1554 panel->vbt.psr.tp2_tp3_wakeup_time_us = 500;
1555 break;
1556 case 1:
1557 panel->vbt.psr.tp2_tp3_wakeup_time_us = 100;
1558 break;
1559 case 3:
1560 panel->vbt.psr.tp2_tp3_wakeup_time_us = 0;
1561 break;
1562 default:
1563 drm_dbg_kms(&i915->drm,
1564 "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
1565 psr_table->tp2_tp3_wakeup_time);
1566 fallthrough;
1567 case 2:
1568 panel->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
1569 break;
1570 }
1571 } else {
1572 panel->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
1573 panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
1574 }
1575
1576 if (i915->vbt.version >= 226) {
1577 u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
1578
1579 wakeup_time = panel_bits(wakeup_time, panel_type, 2);
1580 switch (wakeup_time) {
1581 case 0:
1582 wakeup_time = 500;
1583 break;
1584 case 1:
1585 wakeup_time = 100;
1586 break;
1587 case 3:
1588 wakeup_time = 50;
1589 break;
1590 default:
1591 case 2:
1592 wakeup_time = 2500;
1593 break;
1594 }
1595 panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
1596 } else {
1597
1598 panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = panel->vbt.psr.tp2_tp3_wakeup_time_us;
1599 }
1600 }
1601
1602 static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
1603 struct intel_panel *panel,
1604 enum port port)
1605 {
1606 enum port port_bc = DISPLAY_VER(i915) >= 11 ? PORT_B : PORT_C;
1607
1608 if (!panel->vbt.dsi.config->dual_link || i915->vbt.version < 197) {
1609 panel->vbt.dsi.bl_ports = BIT(port);
1610 if (panel->vbt.dsi.config->cabc_supported)
1611 panel->vbt.dsi.cabc_ports = BIT(port);
1612
1613 return;
1614 }
1615
1616 switch (panel->vbt.dsi.config->dl_dcs_backlight_ports) {
1617 case DL_DCS_PORT_A:
1618 panel->vbt.dsi.bl_ports = BIT(PORT_A);
1619 break;
1620 case DL_DCS_PORT_C:
1621 panel->vbt.dsi.bl_ports = BIT(port_bc);
1622 break;
1623 default:
1624 case DL_DCS_PORT_A_AND_C:
1625 panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(port_bc);
1626 break;
1627 }
1628
1629 if (!panel->vbt.dsi.config->cabc_supported)
1630 return;
1631
1632 switch (panel->vbt.dsi.config->dl_dcs_cabc_ports) {
1633 case DL_DCS_PORT_A:
1634 panel->vbt.dsi.cabc_ports = BIT(PORT_A);
1635 break;
1636 case DL_DCS_PORT_C:
1637 panel->vbt.dsi.cabc_ports = BIT(port_bc);
1638 break;
1639 default:
1640 case DL_DCS_PORT_A_AND_C:
1641 panel->vbt.dsi.cabc_ports =
1642 BIT(PORT_A) | BIT(port_bc);
1643 break;
1644 }
1645 }
1646
1647 static void
1648 parse_mipi_config(struct drm_i915_private *i915,
1649 struct intel_panel *panel)
1650 {
1651 const struct bdb_mipi_config *start;
1652 const struct mipi_config *config;
1653 const struct mipi_pps_data *pps;
1654 int panel_type = panel->vbt.panel_type;
1655 enum port port;
1656
1657
1658 if (!intel_bios_is_dsi_present(i915, &port))
1659 return;
1660
1661
1662 panel->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672 start = find_section(i915, BDB_MIPI_CONFIG);
1673 if (!start) {
1674 drm_dbg_kms(&i915->drm, "No MIPI config BDB found");
1675 return;
1676 }
1677
1678 drm_dbg(&i915->drm, "Found MIPI Config block, panel index = %d\n",
1679 panel_type);
1680
1681
1682
1683
1684
1685 config = &start->config[panel_type];
1686 pps = &start->pps[panel_type];
1687
1688
1689 panel->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
1690 if (!panel->vbt.dsi.config)
1691 return;
1692
1693 panel->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
1694 if (!panel->vbt.dsi.pps) {
1695 kfree(panel->vbt.dsi.config);
1696 return;
1697 }
1698
1699 parse_dsi_backlight_ports(i915, panel, port);
1700
1701
1702 switch (config->rotation) {
1703 case ENABLE_ROTATION_0:
1704
1705
1706
1707
1708 panel->vbt.dsi.orientation =
1709 DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1710 break;
1711 case ENABLE_ROTATION_90:
1712 panel->vbt.dsi.orientation =
1713 DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
1714 break;
1715 case ENABLE_ROTATION_180:
1716 panel->vbt.dsi.orientation =
1717 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1718 break;
1719 case ENABLE_ROTATION_270:
1720 panel->vbt.dsi.orientation =
1721 DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
1722 break;
1723 }
1724
1725
1726 panel->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
1727 }
1728
1729
1730 static const u8 *
1731 find_panel_sequence_block(const struct bdb_mipi_sequence *sequence,
1732 u16 panel_id, u32 *seq_size)
1733 {
1734 u32 total = get_blocksize(sequence);
1735 const u8 *data = &sequence->data[0];
1736 u8 current_id;
1737 u32 current_size;
1738 int header_size = sequence->version >= 3 ? 5 : 3;
1739 int index = 0;
1740 int i;
1741
1742
1743 if (sequence->version >= 3)
1744 data += 4;
1745
1746 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) {
1747 if (index + header_size > total) {
1748 DRM_ERROR("Invalid sequence block (header)\n");
1749 return NULL;
1750 }
1751
1752 current_id = *(data + index);
1753 if (sequence->version >= 3)
1754 current_size = *((const u32 *)(data + index + 1));
1755 else
1756 current_size = *((const u16 *)(data + index + 1));
1757
1758 index += header_size;
1759
1760 if (index + current_size > total) {
1761 DRM_ERROR("Invalid sequence block\n");
1762 return NULL;
1763 }
1764
1765 if (current_id == panel_id) {
1766 *seq_size = current_size;
1767 return data + index;
1768 }
1769
1770 index += current_size;
1771 }
1772
1773 DRM_ERROR("Sequence block detected but no valid configuration\n");
1774
1775 return NULL;
1776 }
1777
1778 static int goto_next_sequence(const u8 *data, int index, int total)
1779 {
1780 u16 len;
1781
1782
1783 for (index = index + 1; index < total; index += len) {
1784 u8 operation_byte = *(data + index);
1785 index++;
1786
1787 switch (operation_byte) {
1788 case MIPI_SEQ_ELEM_END:
1789 return index;
1790 case MIPI_SEQ_ELEM_SEND_PKT:
1791 if (index + 4 > total)
1792 return 0;
1793
1794 len = *((const u16 *)(data + index + 2)) + 4;
1795 break;
1796 case MIPI_SEQ_ELEM_DELAY:
1797 len = 4;
1798 break;
1799 case MIPI_SEQ_ELEM_GPIO:
1800 len = 2;
1801 break;
1802 case MIPI_SEQ_ELEM_I2C:
1803 if (index + 7 > total)
1804 return 0;
1805 len = *(data + index + 6) + 7;
1806 break;
1807 default:
1808 DRM_ERROR("Unknown operation byte\n");
1809 return 0;
1810 }
1811 }
1812
1813 return 0;
1814 }
1815
1816 static int goto_next_sequence_v3(const u8 *data, int index, int total)
1817 {
1818 int seq_end;
1819 u16 len;
1820 u32 size_of_sequence;
1821
1822
1823
1824
1825
1826 if (total < 5) {
1827 DRM_ERROR("Too small sequence size\n");
1828 return 0;
1829 }
1830
1831
1832 index++;
1833
1834
1835
1836
1837
1838
1839 size_of_sequence = *((const u32 *)(data + index));
1840 index += 4;
1841
1842 seq_end = index + size_of_sequence;
1843 if (seq_end > total) {
1844 DRM_ERROR("Invalid sequence size\n");
1845 return 0;
1846 }
1847
1848 for (; index < total; index += len) {
1849 u8 operation_byte = *(data + index);
1850 index++;
1851
1852 if (operation_byte == MIPI_SEQ_ELEM_END) {
1853 if (index != seq_end) {
1854 DRM_ERROR("Invalid element structure\n");
1855 return 0;
1856 }
1857 return index;
1858 }
1859
1860 len = *(data + index);
1861 index++;
1862
1863
1864
1865
1866
1867 switch (operation_byte) {
1868 case MIPI_SEQ_ELEM_SEND_PKT:
1869 case MIPI_SEQ_ELEM_DELAY:
1870 case MIPI_SEQ_ELEM_GPIO:
1871 case MIPI_SEQ_ELEM_I2C:
1872 case MIPI_SEQ_ELEM_SPI:
1873 case MIPI_SEQ_ELEM_PMIC:
1874 break;
1875 default:
1876 DRM_ERROR("Unknown operation byte %u\n",
1877 operation_byte);
1878 break;
1879 }
1880 }
1881
1882 return 0;
1883 }
1884
1885
1886
1887
1888
1889 static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915,
1890 struct intel_panel *panel)
1891 {
1892 const u8 *data = panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1893 int index, len;
1894
1895 if (drm_WARN_ON(&i915->drm,
1896 !data || panel->vbt.dsi.seq_version != 1))
1897 return 0;
1898
1899
1900 for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) {
1901 switch (data[index]) {
1902 case MIPI_SEQ_ELEM_SEND_PKT:
1903 return index == 1 ? 0 : index;
1904 case MIPI_SEQ_ELEM_DELAY:
1905 len = 5;
1906 break;
1907 case MIPI_SEQ_ELEM_GPIO:
1908 len = 3;
1909 break;
1910 default:
1911 return 0;
1912 }
1913 }
1914
1915 return 0;
1916 }
1917
1918
1919
1920
1921
1922
1923
1924 static void fixup_mipi_sequences(struct drm_i915_private *i915,
1925 struct intel_panel *panel)
1926 {
1927 u8 *init_otp;
1928 int len;
1929
1930
1931 if (!IS_VALLEYVIEW(i915))
1932 return;
1933
1934
1935 if (panel->vbt.dsi.config->is_cmd_mode ||
1936 panel->vbt.dsi.seq_version != 1)
1937 return;
1938
1939
1940 if (!panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
1941 !panel->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
1942 panel->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
1943 return;
1944
1945
1946 len = get_init_otp_deassert_fragment_len(i915, panel);
1947 if (!len)
1948 return;
1949
1950 drm_dbg_kms(&i915->drm,
1951 "Using init OTP fragment to deassert reset\n");
1952
1953
1954 init_otp = (u8 *)panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1955 panel->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
1956 if (!panel->vbt.dsi.deassert_seq)
1957 return;
1958 panel->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
1959 panel->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
1960
1961 panel->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
1962 panel->vbt.dsi.deassert_seq;
1963
1964 init_otp[len - 1] = MIPI_SEQ_INIT_OTP;
1965
1966 panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
1967 }
1968
1969 static void
1970 parse_mipi_sequence(struct drm_i915_private *i915,
1971 struct intel_panel *panel)
1972 {
1973 int panel_type = panel->vbt.panel_type;
1974 const struct bdb_mipi_sequence *sequence;
1975 const u8 *seq_data;
1976 u32 seq_size;
1977 u8 *data;
1978 int index = 0;
1979
1980
1981 if (panel->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
1982 return;
1983
1984 sequence = find_section(i915, BDB_MIPI_SEQUENCE);
1985 if (!sequence) {
1986 drm_dbg_kms(&i915->drm,
1987 "No MIPI Sequence found, parsing complete\n");
1988 return;
1989 }
1990
1991
1992 if (sequence->version >= 4) {
1993 drm_err(&i915->drm,
1994 "Unable to parse MIPI Sequence Block v%u\n",
1995 sequence->version);
1996 return;
1997 }
1998
1999 drm_dbg(&i915->drm, "Found MIPI sequence block v%u\n",
2000 sequence->version);
2001
2002 seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size);
2003 if (!seq_data)
2004 return;
2005
2006 data = kmemdup(seq_data, seq_size, GFP_KERNEL);
2007 if (!data)
2008 return;
2009
2010
2011 for (;;) {
2012 u8 seq_id = *(data + index);
2013 if (seq_id == MIPI_SEQ_END)
2014 break;
2015
2016 if (seq_id >= MIPI_SEQ_MAX) {
2017 drm_err(&i915->drm, "Unknown sequence %u\n",
2018 seq_id);
2019 goto err;
2020 }
2021
2022
2023 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF)
2024 drm_dbg_kms(&i915->drm,
2025 "Unsupported sequence %u\n", seq_id);
2026
2027 panel->vbt.dsi.sequence[seq_id] = data + index;
2028
2029 if (sequence->version >= 3)
2030 index = goto_next_sequence_v3(data, index, seq_size);
2031 else
2032 index = goto_next_sequence(data, index, seq_size);
2033 if (!index) {
2034 drm_err(&i915->drm, "Invalid sequence %u\n",
2035 seq_id);
2036 goto err;
2037 }
2038 }
2039
2040 panel->vbt.dsi.data = data;
2041 panel->vbt.dsi.size = seq_size;
2042 panel->vbt.dsi.seq_version = sequence->version;
2043
2044 fixup_mipi_sequences(i915, panel);
2045
2046 drm_dbg(&i915->drm, "MIPI related VBT parsing complete\n");
2047 return;
2048
2049 err:
2050 kfree(data);
2051 memset(panel->vbt.dsi.sequence, 0, sizeof(panel->vbt.dsi.sequence));
2052 }
2053
2054 static void
2055 parse_compression_parameters(struct drm_i915_private *i915)
2056 {
2057 const struct bdb_compression_parameters *params;
2058 struct intel_bios_encoder_data *devdata;
2059 const struct child_device_config *child;
2060 u16 block_size;
2061 int index;
2062
2063 if (i915->vbt.version < 198)
2064 return;
2065
2066 params = find_section(i915, BDB_COMPRESSION_PARAMETERS);
2067 if (params) {
2068
2069 if (params->entry_size != sizeof(params->data[0])) {
2070 drm_dbg_kms(&i915->drm,
2071 "VBT: unsupported compression param entry size\n");
2072 return;
2073 }
2074
2075 block_size = get_blocksize(params);
2076 if (block_size < sizeof(*params)) {
2077 drm_dbg_kms(&i915->drm,
2078 "VBT: expected 16 compression param entries\n");
2079 return;
2080 }
2081 }
2082
2083 list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
2084 child = &devdata->child;
2085
2086 if (!child->compression_enable)
2087 continue;
2088
2089 if (!params) {
2090 drm_dbg_kms(&i915->drm,
2091 "VBT: compression params not available\n");
2092 continue;
2093 }
2094
2095 if (child->compression_method_cps) {
2096 drm_dbg_kms(&i915->drm,
2097 "VBT: CPS compression not supported\n");
2098 continue;
2099 }
2100
2101 index = child->compression_structure_index;
2102
2103 devdata->dsc = kmemdup(¶ms->data[index],
2104 sizeof(*devdata->dsc), GFP_KERNEL);
2105 }
2106 }
2107
2108 static u8 translate_iboost(u8 val)
2109 {
2110 static const u8 mapping[] = { 1, 3, 7 };
2111
2112 if (val >= ARRAY_SIZE(mapping)) {
2113 DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
2114 return 0;
2115 }
2116 return mapping[val];
2117 }
2118
2119 static const u8 cnp_ddc_pin_map[] = {
2120 [0] = 0,
2121 [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT,
2122 [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT,
2123 [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP,
2124 [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT,
2125 };
2126
2127 static const u8 icp_ddc_pin_map[] = {
2128 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
2129 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
2130 [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
2131 [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
2132 [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
2133 [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
2134 [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
2135 [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
2136 [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
2137 };
2138
2139 static const u8 rkl_pch_tgp_ddc_pin_map[] = {
2140 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
2141 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
2142 [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
2143 [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
2144 };
2145
2146 static const u8 adls_ddc_pin_map[] = {
2147 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
2148 [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
2149 [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
2150 [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
2151 [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
2152 };
2153
2154 static const u8 gen9bc_tgp_ddc_pin_map[] = {
2155 [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
2156 [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
2157 [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP,
2158 };
2159
2160 static const u8 adlp_ddc_pin_map[] = {
2161 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
2162 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
2163 [ADLP_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
2164 [ADLP_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
2165 [ADLP_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
2166 [ADLP_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
2167 };
2168
2169 static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
2170 {
2171 const u8 *ddc_pin_map;
2172 int n_entries;
2173
2174 if (IS_ALDERLAKE_P(i915)) {
2175 ddc_pin_map = adlp_ddc_pin_map;
2176 n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
2177 } else if (IS_ALDERLAKE_S(i915)) {
2178 ddc_pin_map = adls_ddc_pin_map;
2179 n_entries = ARRAY_SIZE(adls_ddc_pin_map);
2180 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
2181 return vbt_pin;
2182 } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
2183 ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
2184 n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
2185 } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) {
2186 ddc_pin_map = gen9bc_tgp_ddc_pin_map;
2187 n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);
2188 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
2189 ddc_pin_map = icp_ddc_pin_map;
2190 n_entries = ARRAY_SIZE(icp_ddc_pin_map);
2191 } else if (HAS_PCH_CNP(i915)) {
2192 ddc_pin_map = cnp_ddc_pin_map;
2193 n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
2194 } else {
2195
2196 return vbt_pin;
2197 }
2198
2199 if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
2200 return ddc_pin_map[vbt_pin];
2201
2202 drm_dbg_kms(&i915->drm,
2203 "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n",
2204 vbt_pin);
2205 return 0;
2206 }
2207
2208 static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin)
2209 {
2210 const struct intel_bios_encoder_data *devdata;
2211 enum port port;
2212
2213 if (!ddc_pin)
2214 return PORT_NONE;
2215
2216 for_each_port(port) {
2217 devdata = i915->vbt.ports[port];
2218
2219 if (devdata && ddc_pin == devdata->child.ddc_pin)
2220 return port;
2221 }
2222
2223 return PORT_NONE;
2224 }
2225
2226 static void sanitize_ddc_pin(struct intel_bios_encoder_data *devdata,
2227 enum port port)
2228 {
2229 struct drm_i915_private *i915 = devdata->i915;
2230 struct child_device_config *child;
2231 u8 mapped_ddc_pin;
2232 enum port p;
2233
2234 if (!devdata->child.ddc_pin)
2235 return;
2236
2237 mapped_ddc_pin = map_ddc_pin(i915, devdata->child.ddc_pin);
2238 if (!intel_gmbus_is_valid_pin(i915, mapped_ddc_pin)) {
2239 drm_dbg_kms(&i915->drm,
2240 "Port %c has invalid DDC pin %d, "
2241 "sticking to defaults\n",
2242 port_name(port), mapped_ddc_pin);
2243 devdata->child.ddc_pin = 0;
2244 return;
2245 }
2246
2247 p = get_port_by_ddc_pin(i915, devdata->child.ddc_pin);
2248 if (p == PORT_NONE)
2249 return;
2250
2251 drm_dbg_kms(&i915->drm,
2252 "port %c trying to use the same DDC pin (0x%x) as port %c, "
2253 "disabling port %c DVI/HDMI support\n",
2254 port_name(port), mapped_ddc_pin,
2255 port_name(p), port_name(p));
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266 child = &i915->vbt.ports[p]->child;
2267
2268 child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;
2269 child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;
2270
2271 child->ddc_pin = 0;
2272 }
2273
2274 static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
2275 {
2276 const struct intel_bios_encoder_data *devdata;
2277 enum port port;
2278
2279 if (!aux_ch)
2280 return PORT_NONE;
2281
2282 for_each_port(port) {
2283 devdata = i915->vbt.ports[port];
2284
2285 if (devdata && aux_ch == devdata->child.aux_channel)
2286 return port;
2287 }
2288
2289 return PORT_NONE;
2290 }
2291
2292 static void sanitize_aux_ch(struct intel_bios_encoder_data *devdata,
2293 enum port port)
2294 {
2295 struct drm_i915_private *i915 = devdata->i915;
2296 struct child_device_config *child;
2297 enum port p;
2298
2299 p = get_port_by_aux_ch(i915, devdata->child.aux_channel);
2300 if (p == PORT_NONE)
2301 return;
2302
2303 drm_dbg_kms(&i915->drm,
2304 "port %c trying to use the same AUX CH (0x%x) as port %c, "
2305 "disabling port %c DP support\n",
2306 port_name(port), devdata->child.aux_channel,
2307 port_name(p), port_name(p));
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318 child = &i915->vbt.ports[p]->child;
2319
2320 child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT;
2321 child->aux_channel = 0;
2322 }
2323
2324 static u8 dvo_port_type(u8 dvo_port)
2325 {
2326 switch (dvo_port) {
2327 case DVO_PORT_HDMIA:
2328 case DVO_PORT_HDMIB:
2329 case DVO_PORT_HDMIC:
2330 case DVO_PORT_HDMID:
2331 case DVO_PORT_HDMIE:
2332 case DVO_PORT_HDMIF:
2333 case DVO_PORT_HDMIG:
2334 case DVO_PORT_HDMIH:
2335 case DVO_PORT_HDMII:
2336 return DVO_PORT_HDMIA;
2337 case DVO_PORT_DPA:
2338 case DVO_PORT_DPB:
2339 case DVO_PORT_DPC:
2340 case DVO_PORT_DPD:
2341 case DVO_PORT_DPE:
2342 case DVO_PORT_DPF:
2343 case DVO_PORT_DPG:
2344 case DVO_PORT_DPH:
2345 case DVO_PORT_DPI:
2346 return DVO_PORT_DPA;
2347 case DVO_PORT_MIPIA:
2348 case DVO_PORT_MIPIB:
2349 case DVO_PORT_MIPIC:
2350 case DVO_PORT_MIPID:
2351 return DVO_PORT_MIPIA;
2352 default:
2353 return dvo_port;
2354 }
2355 }
2356
2357 static enum port __dvo_port_to_port(int n_ports, int n_dvo,
2358 const int port_mapping[][3], u8 dvo_port)
2359 {
2360 enum port port;
2361 int i;
2362
2363 for (port = PORT_A; port < n_ports; port++) {
2364 for (i = 0; i < n_dvo; i++) {
2365 if (port_mapping[port][i] == -1)
2366 break;
2367
2368 if (dvo_port == port_mapping[port][i])
2369 return port;
2370 }
2371 }
2372
2373 return PORT_NONE;
2374 }
2375
2376 static enum port dvo_port_to_port(struct drm_i915_private *i915,
2377 u8 dvo_port)
2378 {
2379
2380
2381
2382
2383 static const int port_mapping[][3] = {
2384 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
2385 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
2386 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
2387 [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
2388 [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT },
2389 [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
2390 [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
2391 [PORT_H] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 },
2392 [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
2393 };
2394
2395
2396
2397
2398 static const int rkl_port_mapping[][3] = {
2399 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
2400 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
2401 [PORT_C] = { -1 },
2402 [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
2403 [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
2404 };
2405
2406
2407
2408
2409 static const int adls_port_mapping[][3] = {
2410 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
2411 [PORT_B] = { -1 },
2412 [PORT_C] = { -1 },
2413 [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
2414 [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
2415 [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
2416 [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
2417 };
2418 static const int xelpd_port_mapping[][3] = {
2419 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
2420 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
2421 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
2422 [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
2423 [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
2424 [PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
2425 [PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
2426 [PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 },
2427 [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
2428 };
2429
2430 if (DISPLAY_VER(i915) == 13)
2431 return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping),
2432 ARRAY_SIZE(xelpd_port_mapping[0]),
2433 xelpd_port_mapping,
2434 dvo_port);
2435 else if (IS_ALDERLAKE_S(i915))
2436 return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
2437 ARRAY_SIZE(adls_port_mapping[0]),
2438 adls_port_mapping,
2439 dvo_port);
2440 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))
2441 return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
2442 ARRAY_SIZE(rkl_port_mapping[0]),
2443 rkl_port_mapping,
2444 dvo_port);
2445 else
2446 return __dvo_port_to_port(ARRAY_SIZE(port_mapping),
2447 ARRAY_SIZE(port_mapping[0]),
2448 port_mapping,
2449 dvo_port);
2450 }
2451
2452 static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate)
2453 {
2454 switch (vbt_max_link_rate) {
2455 default:
2456 case BDB_230_VBT_DP_MAX_LINK_RATE_DEF:
2457 return 0;
2458 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20:
2459 return 2000000;
2460 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5:
2461 return 1350000;
2462 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10:
2463 return 1000000;
2464 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR3:
2465 return 810000;
2466 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR2:
2467 return 540000;
2468 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR:
2469 return 270000;
2470 case BDB_230_VBT_DP_MAX_LINK_RATE_LBR:
2471 return 162000;
2472 }
2473 }
2474
2475 static int parse_bdb_216_dp_max_link_rate(const int vbt_max_link_rate)
2476 {
2477 switch (vbt_max_link_rate) {
2478 default:
2479 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR3:
2480 return 810000;
2481 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR2:
2482 return 540000;
2483 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR:
2484 return 270000;
2485 case BDB_216_VBT_DP_MAX_LINK_RATE_LBR:
2486 return 162000;
2487 }
2488 }
2489
2490 static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata)
2491 {
2492 if (!devdata || devdata->i915->vbt.version < 216)
2493 return 0;
2494
2495 if (devdata->i915->vbt.version >= 230)
2496 return parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate);
2497 else
2498 return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);
2499 }
2500
2501 static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
2502 enum port port)
2503 {
2504 struct drm_i915_private *i915 = devdata->i915;
2505 bool is_hdmi;
2506
2507 if (port != PORT_A || DISPLAY_VER(i915) >= 12)
2508 return;
2509
2510 if (!intel_bios_encoder_supports_dvi(devdata))
2511 return;
2512
2513 is_hdmi = intel_bios_encoder_supports_hdmi(devdata);
2514
2515 drm_dbg_kms(&i915->drm, "VBT claims port A supports DVI%s, ignoring\n",
2516 is_hdmi ? "/HDMI" : "");
2517
2518 devdata->child.device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;
2519 devdata->child.device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;
2520 }
2521
2522 static bool
2523 intel_bios_encoder_supports_crt(const struct intel_bios_encoder_data *devdata)
2524 {
2525 return devdata->child.device_type & DEVICE_TYPE_ANALOG_OUTPUT;
2526 }
2527
2528 bool
2529 intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata)
2530 {
2531 return devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
2532 }
2533
2534 bool
2535 intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata)
2536 {
2537 return intel_bios_encoder_supports_dvi(devdata) &&
2538 (devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
2539 }
2540
2541 bool
2542 intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata)
2543 {
2544 return devdata->child.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
2545 }
2546
2547 static bool
2548 intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata)
2549 {
2550 return intel_bios_encoder_supports_dp(devdata) &&
2551 devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;
2552 }
2553
2554 static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata)
2555 {
2556 if (!devdata || devdata->i915->vbt.version < 158)
2557 return -1;
2558
2559 return devdata->child.hdmi_level_shifter_value;
2560 }
2561
2562 static int _intel_bios_max_tmds_clock(const struct intel_bios_encoder_data *devdata)
2563 {
2564 if (!devdata || devdata->i915->vbt.version < 204)
2565 return 0;
2566
2567 switch (devdata->child.hdmi_max_data_rate) {
2568 default:
2569 MISSING_CASE(devdata->child.hdmi_max_data_rate);
2570 fallthrough;
2571 case HDMI_MAX_DATA_RATE_PLATFORM:
2572 return 0;
2573 case HDMI_MAX_DATA_RATE_594:
2574 return 594000;
2575 case HDMI_MAX_DATA_RATE_340:
2576 return 340000;
2577 case HDMI_MAX_DATA_RATE_300:
2578 return 300000;
2579 case HDMI_MAX_DATA_RATE_297:
2580 return 297000;
2581 case HDMI_MAX_DATA_RATE_165:
2582 return 165000;
2583 }
2584 }
2585
2586 static bool is_port_valid(struct drm_i915_private *i915, enum port port)
2587 {
2588
2589
2590
2591
2592
2593 if (port == PORT_F && IS_ICELAKE(i915))
2594 return IS_ICL_WITH_PORT_F(i915);
2595
2596 return true;
2597 }
2598
2599 static void print_ddi_port(const struct intel_bios_encoder_data *devdata,
2600 enum port port)
2601 {
2602 struct drm_i915_private *i915 = devdata->i915;
2603 const struct child_device_config *child = &devdata->child;
2604 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, supports_tbt;
2605 int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;
2606
2607 is_dvi = intel_bios_encoder_supports_dvi(devdata);
2608 is_dp = intel_bios_encoder_supports_dp(devdata);
2609 is_crt = intel_bios_encoder_supports_crt(devdata);
2610 is_hdmi = intel_bios_encoder_supports_hdmi(devdata);
2611 is_edp = intel_bios_encoder_supports_edp(devdata);
2612
2613 supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata);
2614 supports_tbt = intel_bios_encoder_supports_tbt(devdata);
2615
2616 drm_dbg_kms(&i915->drm,
2617 "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
2618 port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
2619 HAS_LSPCON(i915) && child->lspcon,
2620 supports_typec_usb, supports_tbt,
2621 devdata->dsc != NULL);
2622
2623 hdmi_level_shift = _intel_bios_hdmi_level_shift(devdata);
2624 if (hdmi_level_shift >= 0) {
2625 drm_dbg_kms(&i915->drm,
2626 "Port %c VBT HDMI level shift: %d\n",
2627 port_name(port), hdmi_level_shift);
2628 }
2629
2630 max_tmds_clock = _intel_bios_max_tmds_clock(devdata);
2631 if (max_tmds_clock)
2632 drm_dbg_kms(&i915->drm,
2633 "Port %c VBT HDMI max TMDS clock: %d kHz\n",
2634 port_name(port), max_tmds_clock);
2635
2636
2637 dp_boost_level = intel_bios_encoder_dp_boost_level(devdata);
2638 if (dp_boost_level)
2639 drm_dbg_kms(&i915->drm,
2640 "Port %c VBT (e)DP boost level: %d\n",
2641 port_name(port), dp_boost_level);
2642
2643 hdmi_boost_level = intel_bios_encoder_hdmi_boost_level(devdata);
2644 if (hdmi_boost_level)
2645 drm_dbg_kms(&i915->drm,
2646 "Port %c VBT HDMI boost level: %d\n",
2647 port_name(port), hdmi_boost_level);
2648
2649 dp_max_link_rate = _intel_bios_dp_max_link_rate(devdata);
2650 if (dp_max_link_rate)
2651 drm_dbg_kms(&i915->drm,
2652 "Port %c VBT DP max link rate: %d\n",
2653 port_name(port), dp_max_link_rate);
2654 }
2655
2656 static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
2657 {
2658 struct drm_i915_private *i915 = devdata->i915;
2659 const struct child_device_config *child = &devdata->child;
2660 enum port port;
2661
2662 port = dvo_port_to_port(i915, child->dvo_port);
2663 if (port == PORT_NONE)
2664 return;
2665
2666 if (!is_port_valid(i915, port)) {
2667 drm_dbg_kms(&i915->drm,
2668 "VBT reports port %c as supported, but that can't be true: skipping\n",
2669 port_name(port));
2670 return;
2671 }
2672
2673 if (i915->vbt.ports[port]) {
2674 drm_dbg_kms(&i915->drm,
2675 "More than one child device for port %c in VBT, using the first.\n",
2676 port_name(port));
2677 return;
2678 }
2679
2680 sanitize_device_type(devdata, port);
2681
2682 if (intel_bios_encoder_supports_dvi(devdata))
2683 sanitize_ddc_pin(devdata, port);
2684
2685 if (intel_bios_encoder_supports_dp(devdata))
2686 sanitize_aux_ch(devdata, port);
2687
2688 i915->vbt.ports[port] = devdata;
2689 }
2690
2691 static bool has_ddi_port_info(struct drm_i915_private *i915)
2692 {
2693 return DISPLAY_VER(i915) >= 5 || IS_G4X(i915);
2694 }
2695
2696 static void parse_ddi_ports(struct drm_i915_private *i915)
2697 {
2698 struct intel_bios_encoder_data *devdata;
2699 enum port port;
2700
2701 if (!has_ddi_port_info(i915))
2702 return;
2703
2704 list_for_each_entry(devdata, &i915->vbt.display_devices, node)
2705 parse_ddi_port(devdata);
2706
2707 for_each_port(port) {
2708 if (i915->vbt.ports[port])
2709 print_ddi_port(i915->vbt.ports[port], port);
2710 }
2711 }
2712
2713 static void
2714 parse_general_definitions(struct drm_i915_private *i915)
2715 {
2716 const struct bdb_general_definitions *defs;
2717 struct intel_bios_encoder_data *devdata;
2718 const struct child_device_config *child;
2719 int i, child_device_num;
2720 u8 expected_size;
2721 u16 block_size;
2722 int bus_pin;
2723
2724 defs = find_section(i915, BDB_GENERAL_DEFINITIONS);
2725 if (!defs) {
2726 drm_dbg_kms(&i915->drm,
2727 "No general definition block is found, no devices defined.\n");
2728 return;
2729 }
2730
2731 block_size = get_blocksize(defs);
2732 if (block_size < sizeof(*defs)) {
2733 drm_dbg_kms(&i915->drm,
2734 "General definitions block too small (%u)\n",
2735 block_size);
2736 return;
2737 }
2738
2739 bus_pin = defs->crt_ddc_gmbus_pin;
2740 drm_dbg_kms(&i915->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
2741 if (intel_gmbus_is_valid_pin(i915, bus_pin))
2742 i915->vbt.crt_ddc_pin = bus_pin;
2743
2744 if (i915->vbt.version < 106) {
2745 expected_size = 22;
2746 } else if (i915->vbt.version < 111) {
2747 expected_size = 27;
2748 } else if (i915->vbt.version < 195) {
2749 expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
2750 } else if (i915->vbt.version == 195) {
2751 expected_size = 37;
2752 } else if (i915->vbt.version <= 215) {
2753 expected_size = 38;
2754 } else if (i915->vbt.version <= 237) {
2755 expected_size = 39;
2756 } else {
2757 expected_size = sizeof(*child);
2758 BUILD_BUG_ON(sizeof(*child) < 39);
2759 drm_dbg(&i915->drm,
2760 "Expected child device config size for VBT version %u not known; assuming %u\n",
2761 i915->vbt.version, expected_size);
2762 }
2763
2764
2765 if (defs->child_dev_size != expected_size)
2766 drm_err(&i915->drm,
2767 "Unexpected child device config size %u (expected %u for VBT version %u)\n",
2768 defs->child_dev_size, expected_size, i915->vbt.version);
2769
2770
2771 if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
2772 drm_dbg_kms(&i915->drm,
2773 "Child device config size %u is too small.\n",
2774 defs->child_dev_size);
2775 return;
2776 }
2777
2778
2779 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
2780
2781 for (i = 0; i < child_device_num; i++) {
2782 child = child_device_ptr(defs, i);
2783 if (!child->device_type)
2784 continue;
2785
2786 drm_dbg_kms(&i915->drm,
2787 "Found VBT child device with type 0x%x\n",
2788 child->device_type);
2789
2790 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL);
2791 if (!devdata)
2792 break;
2793
2794 devdata->i915 = i915;
2795
2796
2797
2798
2799
2800
2801 memcpy(&devdata->child, child,
2802 min_t(size_t, defs->child_dev_size, sizeof(*child)));
2803
2804 list_add_tail(&devdata->node, &i915->vbt.display_devices);
2805 }
2806
2807 if (list_empty(&i915->vbt.display_devices))
2808 drm_dbg_kms(&i915->drm,
2809 "no child dev is parsed from VBT\n");
2810 }
2811
2812
2813 static void
2814 init_vbt_defaults(struct drm_i915_private *i915)
2815 {
2816 i915->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
2817
2818
2819 i915->vbt.int_tv_support = 1;
2820 i915->vbt.int_crt_support = 1;
2821
2822
2823 i915->vbt.int_lvds_support = 1;
2824
2825
2826 i915->vbt.lvds_use_ssc = 1;
2827
2828
2829
2830
2831 i915->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915,
2832 !HAS_PCH_SPLIT(i915));
2833 drm_dbg_kms(&i915->drm, "Set default to SSC at %d kHz\n",
2834 i915->vbt.lvds_ssc_freq);
2835 }
2836
2837
2838 static void
2839 init_vbt_panel_defaults(struct intel_panel *panel)
2840 {
2841
2842 panel->vbt.backlight.present = true;
2843
2844
2845 panel->vbt.lvds_dither = true;
2846 }
2847
2848
2849 static void
2850 init_vbt_missing_defaults(struct drm_i915_private *i915)
2851 {
2852 enum port port;
2853 int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) |
2854 BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
2855
2856 if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
2857 return;
2858
2859 for_each_port_masked(port, ports) {
2860 struct intel_bios_encoder_data *devdata;
2861 struct child_device_config *child;
2862 enum phy phy = intel_port_to_phy(i915, port);
2863
2864
2865
2866
2867
2868 if (intel_phy_is_tc(i915, phy))
2869 continue;
2870
2871
2872 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL);
2873 if (!devdata)
2874 break;
2875
2876 devdata->i915 = i915;
2877 child = &devdata->child;
2878
2879 if (port == PORT_F)
2880 child->dvo_port = DVO_PORT_HDMIF;
2881 else if (port == PORT_E)
2882 child->dvo_port = DVO_PORT_HDMIE;
2883 else
2884 child->dvo_port = DVO_PORT_HDMIA + port;
2885
2886 if (port != PORT_A && port != PORT_E)
2887 child->device_type |= DEVICE_TYPE_TMDS_DVI_SIGNALING;
2888
2889 if (port != PORT_E)
2890 child->device_type |= DEVICE_TYPE_DISPLAYPORT_OUTPUT;
2891
2892 if (port == PORT_A)
2893 child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR;
2894
2895 list_add_tail(&devdata->node, &i915->vbt.display_devices);
2896
2897 drm_dbg_kms(&i915->drm,
2898 "Generating default VBT child device with type 0x04%x on port %c\n",
2899 child->device_type, port_name(port));
2900 }
2901
2902
2903 i915->vbt.version = 155;
2904 }
2905
2906 static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
2907 {
2908 const void *_vbt = vbt;
2909
2910 return _vbt + vbt->bdb_offset;
2911 }
2912
2913
2914
2915
2916
2917
2918
2919
2920 bool intel_bios_is_valid_vbt(const void *buf, size_t size)
2921 {
2922 const struct vbt_header *vbt = buf;
2923 const struct bdb_header *bdb;
2924
2925 if (!vbt)
2926 return false;
2927
2928 if (sizeof(struct vbt_header) > size) {
2929 DRM_DEBUG_DRIVER("VBT header incomplete\n");
2930 return false;
2931 }
2932
2933 if (memcmp(vbt->signature, "$VBT", 4)) {
2934 DRM_DEBUG_DRIVER("VBT invalid signature\n");
2935 return false;
2936 }
2937
2938 if (vbt->vbt_size > size) {
2939 DRM_DEBUG_DRIVER("VBT incomplete (vbt_size overflows)\n");
2940 return false;
2941 }
2942
2943 size = vbt->vbt_size;
2944
2945 if (range_overflows_t(size_t,
2946 vbt->bdb_offset,
2947 sizeof(struct bdb_header),
2948 size)) {
2949 DRM_DEBUG_DRIVER("BDB header incomplete\n");
2950 return false;
2951 }
2952
2953 bdb = get_bdb_header(vbt);
2954 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
2955 DRM_DEBUG_DRIVER("BDB incomplete\n");
2956 return false;
2957 }
2958
2959 return vbt;
2960 }
2961
2962 static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
2963 {
2964 u32 count, data, found, store = 0;
2965 u32 static_region, oprom_offset;
2966 u32 oprom_size = 0x200000;
2967 u16 vbt_size;
2968 u32 *vbt;
2969
2970 static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS);
2971 static_region &= OPTIONROM_SPI_REGIONID_MASK;
2972 intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region);
2973
2974 oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET);
2975 oprom_offset &= OROM_OFFSET_MASK;
2976
2977 for (count = 0; count < oprom_size; count += 4) {
2978 intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, oprom_offset + count);
2979 data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
2980
2981 if (data == *((const u32 *)"$VBT")) {
2982 found = oprom_offset + count;
2983 break;
2984 }
2985 }
2986
2987 if (count >= oprom_size)
2988 goto err_not_found;
2989
2990
2991 intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found +
2992 offsetof(struct vbt_header, vbt_size));
2993 vbt_size = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
2994 vbt_size &= 0xffff;
2995
2996 vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL);
2997 if (!vbt)
2998 goto err_not_found;
2999
3000 for (count = 0; count < vbt_size; count += 4) {
3001 intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found + count);
3002 data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
3003 *(vbt + store++) = data;
3004 }
3005
3006 if (!intel_bios_is_valid_vbt(vbt, vbt_size))
3007 goto err_free_vbt;
3008
3009 drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n");
3010
3011 return (struct vbt_header *)vbt;
3012
3013 err_free_vbt:
3014 kfree(vbt);
3015 err_not_found:
3016 return NULL;
3017 }
3018
3019 static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
3020 {
3021 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
3022 void __iomem *p = NULL, *oprom;
3023 struct vbt_header *vbt;
3024 u16 vbt_size;
3025 size_t i, size;
3026
3027 oprom = pci_map_rom(pdev, &size);
3028 if (!oprom)
3029 return NULL;
3030
3031
3032 for (i = 0; i + 4 < size; i += 4) {
3033 if (ioread32(oprom + i) != *((const u32 *)"$VBT"))
3034 continue;
3035
3036 p = oprom + i;
3037 size -= i;
3038 break;
3039 }
3040
3041 if (!p)
3042 goto err_unmap_oprom;
3043
3044 if (sizeof(struct vbt_header) > size) {
3045 drm_dbg(&i915->drm, "VBT header incomplete\n");
3046 goto err_unmap_oprom;
3047 }
3048
3049 vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size));
3050 if (vbt_size > size) {
3051 drm_dbg(&i915->drm,
3052 "VBT incomplete (vbt_size overflows)\n");
3053 goto err_unmap_oprom;
3054 }
3055
3056
3057 vbt = kmalloc(vbt_size, GFP_KERNEL);
3058 if (!vbt)
3059 goto err_unmap_oprom;
3060
3061 memcpy_fromio(vbt, p, vbt_size);
3062
3063 if (!intel_bios_is_valid_vbt(vbt, vbt_size))
3064 goto err_free_vbt;
3065
3066 pci_unmap_rom(pdev, oprom);
3067
3068 drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n");
3069
3070 return vbt;
3071
3072 err_free_vbt:
3073 kfree(vbt);
3074 err_unmap_oprom:
3075 pci_unmap_rom(pdev, oprom);
3076
3077 return NULL;
3078 }
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088 void intel_bios_init(struct drm_i915_private *i915)
3089 {
3090 const struct vbt_header *vbt = i915->opregion.vbt;
3091 struct vbt_header *oprom_vbt = NULL;
3092 const struct bdb_header *bdb;
3093
3094 INIT_LIST_HEAD(&i915->vbt.display_devices);
3095 INIT_LIST_HEAD(&i915->vbt.bdb_blocks);
3096
3097 if (!HAS_DISPLAY(i915)) {
3098 drm_dbg_kms(&i915->drm,
3099 "Skipping VBT init due to disabled display.\n");
3100 return;
3101 }
3102
3103 init_vbt_defaults(i915);
3104
3105
3106
3107
3108
3109 if (!vbt && IS_DGFX(i915)) {
3110 oprom_vbt = spi_oprom_get_vbt(i915);
3111 vbt = oprom_vbt;
3112 }
3113
3114 if (!vbt) {
3115 oprom_vbt = oprom_get_vbt(i915);
3116 vbt = oprom_vbt;
3117 }
3118
3119 if (!vbt)
3120 goto out;
3121
3122 bdb = get_bdb_header(vbt);
3123 i915->vbt.version = bdb->version;
3124
3125 drm_dbg_kms(&i915->drm,
3126 "VBT signature \"%.*s\", BDB version %d\n",
3127 (int)sizeof(vbt->signature), vbt->signature, i915->vbt.version);
3128
3129 init_bdb_blocks(i915, bdb);
3130
3131
3132 parse_general_features(i915);
3133 parse_general_definitions(i915);
3134 parse_driver_features(i915);
3135
3136
3137 parse_compression_parameters(i915);
3138
3139 out:
3140 if (!vbt) {
3141 drm_info(&i915->drm,
3142 "Failed to find VBIOS tables (VBT)\n");
3143 init_vbt_missing_defaults(i915);
3144 }
3145
3146
3147 parse_sdvo_device_mapping(i915);
3148 parse_ddi_ports(i915);
3149
3150 kfree(oprom_vbt);
3151 }
3152
3153 void intel_bios_init_panel(struct drm_i915_private *i915,
3154 struct intel_panel *panel,
3155 const struct intel_bios_encoder_data *devdata,
3156 const struct edid *edid)
3157 {
3158 init_vbt_panel_defaults(panel);
3159
3160 panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
3161
3162 parse_panel_options(i915, panel);
3163 parse_generic_dtd(i915, panel);
3164 parse_lfp_data(i915, panel);
3165 parse_lfp_backlight(i915, panel);
3166 parse_sdvo_panel_data(i915, panel);
3167 parse_panel_driver_features(i915, panel);
3168 parse_power_conservation_features(i915, panel);
3169 parse_edp(i915, panel);
3170 parse_psr(i915, panel);
3171 parse_mipi_config(i915, panel);
3172 parse_mipi_sequence(i915, panel);
3173 }
3174
3175
3176
3177
3178
3179 void intel_bios_driver_remove(struct drm_i915_private *i915)
3180 {
3181 struct intel_bios_encoder_data *devdata, *nd;
3182 struct bdb_block_entry *entry, *ne;
3183
3184 list_for_each_entry_safe(devdata, nd, &i915->vbt.display_devices, node) {
3185 list_del(&devdata->node);
3186 kfree(devdata->dsc);
3187 kfree(devdata);
3188 }
3189
3190 list_for_each_entry_safe(entry, ne, &i915->vbt.bdb_blocks, node) {
3191 list_del(&entry->node);
3192 kfree(entry);
3193 }
3194 }
3195
3196 void intel_bios_fini_panel(struct intel_panel *panel)
3197 {
3198 kfree(panel->vbt.sdvo_lvds_vbt_mode);
3199 panel->vbt.sdvo_lvds_vbt_mode = NULL;
3200 kfree(panel->vbt.lfp_lvds_vbt_mode);
3201 panel->vbt.lfp_lvds_vbt_mode = NULL;
3202 kfree(panel->vbt.dsi.data);
3203 panel->vbt.dsi.data = NULL;
3204 kfree(panel->vbt.dsi.pps);
3205 panel->vbt.dsi.pps = NULL;
3206 kfree(panel->vbt.dsi.config);
3207 panel->vbt.dsi.config = NULL;
3208 kfree(panel->vbt.dsi.deassert_seq);
3209 panel->vbt.dsi.deassert_seq = NULL;
3210 }
3211
3212
3213
3214
3215
3216
3217
3218
3219 bool intel_bios_is_tv_present(struct drm_i915_private *i915)
3220 {
3221 const struct intel_bios_encoder_data *devdata;
3222 const struct child_device_config *child;
3223
3224 if (!i915->vbt.int_tv_support)
3225 return false;
3226
3227 if (list_empty(&i915->vbt.display_devices))
3228 return true;
3229
3230 list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
3231 child = &devdata->child;
3232
3233
3234
3235
3236 switch (child->device_type) {
3237 case DEVICE_TYPE_INT_TV:
3238 case DEVICE_TYPE_TV:
3239 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
3240 break;
3241 default:
3242 continue;
3243 }
3244
3245
3246
3247 if (child->addin_offset)
3248 return true;
3249 }
3250
3251 return false;
3252 }
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262 bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin)
3263 {
3264 const struct intel_bios_encoder_data *devdata;
3265 const struct child_device_config *child;
3266
3267 if (list_empty(&i915->vbt.display_devices))
3268 return true;
3269
3270 list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
3271 child = &devdata->child;
3272
3273
3274
3275
3276
3277 if (child->device_type != DEVICE_TYPE_INT_LFP &&
3278 child->device_type != DEVICE_TYPE_LFP)
3279 continue;
3280
3281 if (intel_gmbus_is_valid_pin(i915, child->i2c_pin))
3282 *i2c_pin = child->i2c_pin;
3283
3284
3285
3286
3287
3288
3289 if (child->addin_offset)
3290 return true;
3291
3292
3293
3294
3295
3296
3297 if (i915->opregion.vbt)
3298 return true;
3299 }
3300
3301 return false;
3302 }
3303
3304
3305
3306
3307
3308
3309
3310
3311 bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port)
3312 {
3313 if (WARN_ON(!has_ddi_port_info(i915)))
3314 return true;
3315
3316 return i915->vbt.ports[port];
3317 }
3318
3319
3320
3321
3322
3323
3324
3325
3326 bool intel_bios_is_port_edp(struct drm_i915_private *i915, enum port port)
3327 {
3328 const struct intel_bios_encoder_data *devdata =
3329 intel_bios_encoder_data_lookup(i915, port);
3330
3331 return devdata && intel_bios_encoder_supports_edp(devdata);
3332 }
3333
3334 static bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata)
3335 {
3336 const struct child_device_config *child = &devdata->child;
3337
3338 if (!intel_bios_encoder_supports_dp(devdata) ||
3339 !intel_bios_encoder_supports_hdmi(devdata))
3340 return false;
3341
3342 if (dvo_port_type(child->dvo_port) == DVO_PORT_DPA)
3343 return true;
3344
3345
3346 if (dvo_port_type(child->dvo_port) == DVO_PORT_HDMIA &&
3347 child->aux_channel != 0)
3348 return true;
3349
3350 return false;
3351 }
3352
3353 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *i915,
3354 enum port port)
3355 {
3356 const struct intel_bios_encoder_data *devdata =
3357 intel_bios_encoder_data_lookup(i915, port);
3358
3359 return devdata && intel_bios_encoder_supports_dp_dual_mode(devdata);
3360 }
3361
3362
3363
3364
3365
3366
3367
3368
3369 bool intel_bios_is_dsi_present(struct drm_i915_private *i915,
3370 enum port *port)
3371 {
3372 const struct intel_bios_encoder_data *devdata;
3373 const struct child_device_config *child;
3374 u8 dvo_port;
3375
3376 list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
3377 child = &devdata->child;
3378
3379 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
3380 continue;
3381
3382 dvo_port = child->dvo_port;
3383
3384 if (dvo_port == DVO_PORT_MIPIA ||
3385 (dvo_port == DVO_PORT_MIPIB && DISPLAY_VER(i915) >= 11) ||
3386 (dvo_port == DVO_PORT_MIPIC && DISPLAY_VER(i915) < 11)) {
3387 if (port)
3388 *port = dvo_port - DVO_PORT_MIPIA;
3389 return true;
3390 } else if (dvo_port == DVO_PORT_MIPIB ||
3391 dvo_port == DVO_PORT_MIPIC ||
3392 dvo_port == DVO_PORT_MIPID) {
3393 drm_dbg_kms(&i915->drm,
3394 "VBT has unsupported DSI port %c\n",
3395 port_name(dvo_port - DVO_PORT_MIPIA));
3396 }
3397 }
3398
3399 return false;
3400 }
3401
3402 static void fill_dsc(struct intel_crtc_state *crtc_state,
3403 struct dsc_compression_parameters_entry *dsc,
3404 int dsc_max_bpc)
3405 {
3406 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
3407 int bpc = 8;
3408
3409 vdsc_cfg->dsc_version_major = dsc->version_major;
3410 vdsc_cfg->dsc_version_minor = dsc->version_minor;
3411
3412 if (dsc->support_12bpc && dsc_max_bpc >= 12)
3413 bpc = 12;
3414 else if (dsc->support_10bpc && dsc_max_bpc >= 10)
3415 bpc = 10;
3416 else if (dsc->support_8bpc && dsc_max_bpc >= 8)
3417 bpc = 8;
3418 else
3419 DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n",
3420 dsc_max_bpc);
3421
3422 crtc_state->pipe_bpp = bpc * 3;
3423
3424 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
3425 VBT_DSC_MAX_BPP(dsc->max_bpp));
3426
3427
3428
3429
3430
3431
3432
3433 if (dsc->slices_per_line & BIT(2)) {
3434 crtc_state->dsc.slice_count = 4;
3435 } else if (dsc->slices_per_line & BIT(1)) {
3436 crtc_state->dsc.slice_count = 2;
3437 } else {
3438
3439 if (!(dsc->slices_per_line & BIT(0)))
3440 DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n");
3441
3442 crtc_state->dsc.slice_count = 1;
3443 }
3444
3445 if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
3446 crtc_state->dsc.slice_count != 0)
3447 DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n",
3448 crtc_state->hw.adjusted_mode.crtc_hdisplay,
3449 crtc_state->dsc.slice_count);
3450
3451
3452
3453
3454
3455 vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
3456 dsc->rc_buffer_size);
3457
3458
3459 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
3460
3461 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;
3462
3463 vdsc_cfg->slice_height = dsc->slice_height;
3464 }
3465
3466
3467 bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
3468 struct intel_crtc_state *crtc_state,
3469 int dsc_max_bpc)
3470 {
3471 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3472 const struct intel_bios_encoder_data *devdata;
3473 const struct child_device_config *child;
3474
3475 list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
3476 child = &devdata->child;
3477
3478 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
3479 continue;
3480
3481 if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) {
3482 if (!devdata->dsc)
3483 return false;
3484
3485 if (crtc_state)
3486 fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);
3487
3488 return true;
3489 }
3490 }
3491
3492 return false;
3493 }
3494
3495
3496
3497
3498
3499
3500
3501
3502 bool
3503 intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
3504 enum port port)
3505 {
3506 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
3507
3508 if (drm_WARN_ON_ONCE(&i915->drm,
3509 !IS_GEMINILAKE(i915) && !IS_BROXTON(i915)))
3510 return false;
3511
3512 return devdata && devdata->child.hpd_invert;
3513 }
3514
3515
3516
3517
3518
3519
3520
3521
3522 bool
3523 intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
3524 enum port port)
3525 {
3526 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
3527
3528 return HAS_LSPCON(i915) && devdata && devdata->child.lspcon;
3529 }
3530
3531
3532
3533
3534
3535
3536
3537
3538 bool
3539 intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915,
3540 enum port port)
3541 {
3542 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
3543
3544 return devdata && devdata->child.lane_reversal;
3545 }
3546
3547 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
3548 enum port port)
3549 {
3550 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
3551 enum aux_ch aux_ch;
3552
3553 if (!devdata || !devdata->child.aux_channel) {
3554 aux_ch = (enum aux_ch)port;
3555
3556 drm_dbg_kms(&i915->drm,
3557 "using AUX %c for port %c (platform default)\n",
3558 aux_ch_name(aux_ch), port_name(port));
3559 return aux_ch;
3560 }
3561
3562
3563
3564
3565
3566
3567
3568
3569 switch (devdata->child.aux_channel) {
3570 case DP_AUX_A:
3571 aux_ch = AUX_CH_A;
3572 break;
3573 case DP_AUX_B:
3574 if (IS_ALDERLAKE_S(i915))
3575 aux_ch = AUX_CH_USBC1;
3576 else
3577 aux_ch = AUX_CH_B;
3578 break;
3579 case DP_AUX_C:
3580 if (IS_ALDERLAKE_S(i915))
3581 aux_ch = AUX_CH_USBC2;
3582 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))
3583 aux_ch = AUX_CH_USBC1;
3584 else
3585 aux_ch = AUX_CH_C;
3586 break;
3587 case DP_AUX_D:
3588 if (DISPLAY_VER(i915) == 13)
3589 aux_ch = AUX_CH_D_XELPD;
3590 else if (IS_ALDERLAKE_S(i915))
3591 aux_ch = AUX_CH_USBC3;
3592 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))
3593 aux_ch = AUX_CH_USBC2;
3594 else
3595 aux_ch = AUX_CH_D;
3596 break;
3597 case DP_AUX_E:
3598 if (DISPLAY_VER(i915) == 13)
3599 aux_ch = AUX_CH_E_XELPD;
3600 else if (IS_ALDERLAKE_S(i915))
3601 aux_ch = AUX_CH_USBC4;
3602 else
3603 aux_ch = AUX_CH_E;
3604 break;
3605 case DP_AUX_F:
3606 if (DISPLAY_VER(i915) == 13)
3607 aux_ch = AUX_CH_USBC1;
3608 else
3609 aux_ch = AUX_CH_F;
3610 break;
3611 case DP_AUX_G:
3612 if (DISPLAY_VER(i915) == 13)
3613 aux_ch = AUX_CH_USBC2;
3614 else
3615 aux_ch = AUX_CH_G;
3616 break;
3617 case DP_AUX_H:
3618 if (DISPLAY_VER(i915) == 13)
3619 aux_ch = AUX_CH_USBC3;
3620 else
3621 aux_ch = AUX_CH_H;
3622 break;
3623 case DP_AUX_I:
3624 if (DISPLAY_VER(i915) == 13)
3625 aux_ch = AUX_CH_USBC4;
3626 else
3627 aux_ch = AUX_CH_I;
3628 break;
3629 default:
3630 MISSING_CASE(devdata->child.aux_channel);
3631 aux_ch = AUX_CH_A;
3632 break;
3633 }
3634
3635 drm_dbg_kms(&i915->drm, "using AUX %c for port %c (VBT)\n",
3636 aux_ch_name(aux_ch), port_name(port));
3637
3638 return aux_ch;
3639 }
3640
3641 int intel_bios_max_tmds_clock(struct intel_encoder *encoder)
3642 {
3643 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3644 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
3645
3646 return _intel_bios_max_tmds_clock(devdata);
3647 }
3648
3649
3650 int intel_bios_hdmi_level_shift(struct intel_encoder *encoder)
3651 {
3652 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3653 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
3654
3655 return _intel_bios_hdmi_level_shift(devdata);
3656 }
3657
3658 int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata)
3659 {
3660 if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost)
3661 return 0;
3662
3663 return translate_iboost(devdata->child.dp_iboost_level);
3664 }
3665
3666 int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata)
3667 {
3668 if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost)
3669 return 0;
3670
3671 return translate_iboost(devdata->child.hdmi_iboost_level);
3672 }
3673
3674 int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
3675 {
3676 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3677 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
3678
3679 return _intel_bios_dp_max_link_rate(devdata);
3680 }
3681
3682 int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
3683 {
3684 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3685 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
3686
3687 if (!devdata || !devdata->child.ddc_pin)
3688 return 0;
3689
3690 return map_ddc_pin(i915, devdata->child.ddc_pin);
3691 }
3692
3693 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
3694 {
3695 return devdata->i915->vbt.version >= 195 && devdata->child.dp_usb_type_c;
3696 }
3697
3698 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
3699 {
3700 return devdata->i915->vbt.version >= 209 && devdata->child.tbt;
3701 }
3702
3703 const struct intel_bios_encoder_data *
3704 intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port)
3705 {
3706 return i915->vbt.ports[port];
3707 }