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0006 #ifndef __INTEL_AUDIO_REGS_H__
0007 #define __INTEL_AUDIO_REGS_H__
0008
0009 #include "i915_reg_defs.h"
0010
0011 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
0012 #define INTEL_AUDIO_DEVCL 0x808629FB
0013 #define INTEL_AUDIO_DEVBLC 0x80862801
0014 #define INTEL_AUDIO_DEVCTG 0x80862802
0015
0016 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
0017 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
0018 #define G4X_ELDV_DEVCTG (1 << 14)
0019 #define G4X_ELD_ADDR_MASK (0xf << 5)
0020 #define G4X_ELD_ACK (1 << 4)
0021 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
0022
0023 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
0024 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
0025 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
0026 _IBX_HDMIW_HDMIEDID_B)
0027 #define _IBX_AUD_CNTL_ST_A 0xE20B4
0028 #define _IBX_AUD_CNTL_ST_B 0xE21B4
0029 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
0030 _IBX_AUD_CNTL_ST_B)
0031 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
0032 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
0033 #define IBX_ELD_ACK (1 << 4)
0034 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
0035 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
0036 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
0037
0038 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
0039 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
0040 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
0041 #define _CPT_AUD_CNTL_ST_A 0xE50B4
0042 #define _CPT_AUD_CNTL_ST_B 0xE51B4
0043 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
0044 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
0045
0046 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
0047 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
0048 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
0049 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
0050 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
0051 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
0052 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
0053
0054 #define _IBX_AUD_CONFIG_A 0xe2000
0055 #define _IBX_AUD_CONFIG_B 0xe2100
0056 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
0057 #define _CPT_AUD_CONFIG_A 0xe5000
0058 #define _CPT_AUD_CONFIG_B 0xe5100
0059 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
0060 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
0061 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
0062 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
0063
0064 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
0065 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
0066 #define AUD_CONFIG_UPPER_N_SHIFT 20
0067 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
0068 #define AUD_CONFIG_LOWER_N_SHIFT 4
0069 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
0070 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
0071 #define AUD_CONFIG_N(n) \
0072 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
0073 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
0074 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
0075 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
0076 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
0077 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
0078 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
0079 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
0080 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
0081 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
0082 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
0083 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
0084 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
0085 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
0086 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16)
0087 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16)
0088 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16)
0089 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16)
0090 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
0091
0092 #define _HSW_AUD_CONFIG_A 0x65000
0093 #define _HSW_AUD_CONFIG_B 0x65100
0094 #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
0095
0096 #define _HSW_AUD_MISC_CTRL_A 0x65010
0097 #define _HSW_AUD_MISC_CTRL_B 0x65110
0098 #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
0099
0100 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028
0101 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128
0102 #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
0103 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
0104 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
0105 #define AUD_CONFIG_M_MASK 0xfffff
0106
0107 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
0108 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
0109 #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
0110
0111
0112 #define _HSW_AUD_DIG_CNVT_1 0x65080
0113 #define _HSW_AUD_DIG_CNVT_2 0x65180
0114 #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
0115 #define DIP_PORT_SEL_MASK 0x3
0116
0117 #define _HSW_AUD_EDID_DATA_A 0x65050
0118 #define _HSW_AUD_EDID_DATA_B 0x65150
0119 #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
0120
0121 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
0122 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
0123 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
0124 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
0125 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
0126 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
0127
0128 #define _AUD_TCA_DP_2DOT0_CTRL 0x650bc
0129 #define _AUD_TCB_DP_2DOT0_CTRL 0x651bc
0130 #define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)
0131 #define AUD_ENABLE_SDP_SPLIT REG_BIT(31)
0132
0133 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
0134 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
0135
0136 #define AUD_FREQ_CNTRL _MMIO(0x65900)
0137 #define AUD_PIN_BUF_CTL _MMIO(0x48414)
0138 #define AUD_PIN_BUF_ENABLE REG_BIT(31)
0139
0140 #define AUD_TS_CDCLK_M _MMIO(0x65ea0)
0141 #define AUD_TS_CDCLK_M_EN REG_BIT(31)
0142 #define AUD_TS_CDCLK_N _MMIO(0x65ea4)
0143
0144
0145 #define AUD_CONFIG_BE _MMIO(0x65ef0)
0146 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
0147 #define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
0148 #define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
0149 #define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
0150 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
0151 #define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
0152
0153 #define HBLANK_START_COUNT_8 0
0154 #define HBLANK_START_COUNT_16 1
0155 #define HBLANK_START_COUNT_32 2
0156 #define HBLANK_START_COUNT_64 3
0157 #define HBLANK_START_COUNT_96 4
0158 #define HBLANK_START_COUNT_128 5
0159
0160 #endif
