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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2020 Intel Corporation
0004  */
0005 #include <linux/kernel.h>
0006 
0007 #include <drm/drm_atomic_helper.h>
0008 #include <drm/drm_blend.h>
0009 #include <drm/drm_fourcc.h>
0010 #include <drm/drm_plane_helper.h>
0011 
0012 #include "intel_atomic.h"
0013 #include "intel_atomic_plane.h"
0014 #include "intel_de.h"
0015 #include "intel_display_types.h"
0016 #include "intel_fb.h"
0017 #include "intel_fbc.h"
0018 #include "intel_sprite.h"
0019 #include "i9xx_plane.h"
0020 
0021 /* Primary plane formats for gen <= 3 */
0022 static const u32 i8xx_primary_formats[] = {
0023     DRM_FORMAT_C8,
0024     DRM_FORMAT_XRGB1555,
0025     DRM_FORMAT_RGB565,
0026     DRM_FORMAT_XRGB8888,
0027 };
0028 
0029 /* Primary plane formats for ivb (no fp16 due to hw issue) */
0030 static const u32 ivb_primary_formats[] = {
0031     DRM_FORMAT_C8,
0032     DRM_FORMAT_RGB565,
0033     DRM_FORMAT_XRGB8888,
0034     DRM_FORMAT_XBGR8888,
0035     DRM_FORMAT_XRGB2101010,
0036     DRM_FORMAT_XBGR2101010,
0037 };
0038 
0039 /* Primary plane formats for gen >= 4, except ivb */
0040 static const u32 i965_primary_formats[] = {
0041     DRM_FORMAT_C8,
0042     DRM_FORMAT_RGB565,
0043     DRM_FORMAT_XRGB8888,
0044     DRM_FORMAT_XBGR8888,
0045     DRM_FORMAT_XRGB2101010,
0046     DRM_FORMAT_XBGR2101010,
0047     DRM_FORMAT_XBGR16161616F,
0048 };
0049 
0050 /* Primary plane formats for vlv/chv */
0051 static const u32 vlv_primary_formats[] = {
0052     DRM_FORMAT_C8,
0053     DRM_FORMAT_RGB565,
0054     DRM_FORMAT_XRGB8888,
0055     DRM_FORMAT_XBGR8888,
0056     DRM_FORMAT_ARGB8888,
0057     DRM_FORMAT_ABGR8888,
0058     DRM_FORMAT_XRGB2101010,
0059     DRM_FORMAT_XBGR2101010,
0060     DRM_FORMAT_ARGB2101010,
0061     DRM_FORMAT_ABGR2101010,
0062     DRM_FORMAT_XBGR16161616F,
0063 };
0064 
0065 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
0066                         u32 format, u64 modifier)
0067 {
0068     if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
0069         return false;
0070 
0071     switch (format) {
0072     case DRM_FORMAT_C8:
0073     case DRM_FORMAT_RGB565:
0074     case DRM_FORMAT_XRGB1555:
0075     case DRM_FORMAT_XRGB8888:
0076         return modifier == DRM_FORMAT_MOD_LINEAR ||
0077             modifier == I915_FORMAT_MOD_X_TILED;
0078     default:
0079         return false;
0080     }
0081 }
0082 
0083 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
0084                         u32 format, u64 modifier)
0085 {
0086     if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
0087         return false;
0088 
0089     switch (format) {
0090     case DRM_FORMAT_C8:
0091     case DRM_FORMAT_RGB565:
0092     case DRM_FORMAT_XRGB8888:
0093     case DRM_FORMAT_XBGR8888:
0094     case DRM_FORMAT_ARGB8888:
0095     case DRM_FORMAT_ABGR8888:
0096     case DRM_FORMAT_XRGB2101010:
0097     case DRM_FORMAT_XBGR2101010:
0098     case DRM_FORMAT_ARGB2101010:
0099     case DRM_FORMAT_ABGR2101010:
0100     case DRM_FORMAT_XBGR16161616F:
0101         return modifier == DRM_FORMAT_MOD_LINEAR ||
0102             modifier == I915_FORMAT_MOD_X_TILED;
0103     default:
0104         return false;
0105     }
0106 }
0107 
0108 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
0109                    enum i9xx_plane_id i9xx_plane)
0110 {
0111     if (!HAS_FBC(dev_priv))
0112         return false;
0113 
0114     if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
0115         return i9xx_plane == PLANE_A; /* tied to pipe A */
0116     else if (IS_IVYBRIDGE(dev_priv))
0117         return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
0118             i9xx_plane == PLANE_C;
0119     else if (DISPLAY_VER(dev_priv) >= 4)
0120         return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
0121     else
0122         return i9xx_plane == PLANE_A;
0123 }
0124 
0125 static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
0126                     enum i9xx_plane_id i9xx_plane)
0127 {
0128     if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
0129         return dev_priv->fbc[INTEL_FBC_A];
0130     else
0131         return NULL;
0132 }
0133 
0134 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
0135 {
0136     struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
0137     enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
0138 
0139     if (IS_CHERRYVIEW(dev_priv))
0140         return i9xx_plane == PLANE_B;
0141     else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
0142         return false;
0143     else if (DISPLAY_VER(dev_priv) == 4)
0144         return i9xx_plane == PLANE_C;
0145     else
0146         return i9xx_plane == PLANE_B ||
0147             i9xx_plane == PLANE_C;
0148 }
0149 
0150 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
0151               const struct intel_plane_state *plane_state)
0152 {
0153     struct drm_i915_private *dev_priv =
0154         to_i915(plane_state->uapi.plane->dev);
0155     const struct drm_framebuffer *fb = plane_state->hw.fb;
0156     unsigned int rotation = plane_state->hw.rotation;
0157     u32 dspcntr;
0158 
0159     dspcntr = DISP_ENABLE;
0160 
0161     if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
0162         IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
0163         dspcntr |= DISP_TRICKLE_FEED_DISABLE;
0164 
0165     switch (fb->format->format) {
0166     case DRM_FORMAT_C8:
0167         dspcntr |= DISP_FORMAT_8BPP;
0168         break;
0169     case DRM_FORMAT_XRGB1555:
0170         dspcntr |= DISP_FORMAT_BGRX555;
0171         break;
0172     case DRM_FORMAT_ARGB1555:
0173         dspcntr |= DISP_FORMAT_BGRA555;
0174         break;
0175     case DRM_FORMAT_RGB565:
0176         dspcntr |= DISP_FORMAT_BGRX565;
0177         break;
0178     case DRM_FORMAT_XRGB8888:
0179         dspcntr |= DISP_FORMAT_BGRX888;
0180         break;
0181     case DRM_FORMAT_XBGR8888:
0182         dspcntr |= DISP_FORMAT_RGBX888;
0183         break;
0184     case DRM_FORMAT_ARGB8888:
0185         dspcntr |= DISP_FORMAT_BGRA888;
0186         break;
0187     case DRM_FORMAT_ABGR8888:
0188         dspcntr |= DISP_FORMAT_RGBA888;
0189         break;
0190     case DRM_FORMAT_XRGB2101010:
0191         dspcntr |= DISP_FORMAT_BGRX101010;
0192         break;
0193     case DRM_FORMAT_XBGR2101010:
0194         dspcntr |= DISP_FORMAT_RGBX101010;
0195         break;
0196     case DRM_FORMAT_ARGB2101010:
0197         dspcntr |= DISP_FORMAT_BGRA101010;
0198         break;
0199     case DRM_FORMAT_ABGR2101010:
0200         dspcntr |= DISP_FORMAT_RGBA101010;
0201         break;
0202     case DRM_FORMAT_XBGR16161616F:
0203         dspcntr |= DISP_FORMAT_RGBX161616;
0204         break;
0205     default:
0206         MISSING_CASE(fb->format->format);
0207         return 0;
0208     }
0209 
0210     if (DISPLAY_VER(dev_priv) >= 4 &&
0211         fb->modifier == I915_FORMAT_MOD_X_TILED)
0212         dspcntr |= DISP_TILED;
0213 
0214     if (rotation & DRM_MODE_ROTATE_180)
0215         dspcntr |= DISP_ROTATE_180;
0216 
0217     if (rotation & DRM_MODE_REFLECT_X)
0218         dspcntr |= DISP_MIRROR;
0219 
0220     return dspcntr;
0221 }
0222 
0223 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
0224 {
0225     struct drm_i915_private *dev_priv =
0226         to_i915(plane_state->uapi.plane->dev);
0227     const struct drm_framebuffer *fb = plane_state->hw.fb;
0228     int src_x, src_y, src_w;
0229     u32 offset;
0230     int ret;
0231 
0232     ret = intel_plane_compute_gtt(plane_state);
0233     if (ret)
0234         return ret;
0235 
0236     if (!plane_state->uapi.visible)
0237         return 0;
0238 
0239     src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
0240     src_x = plane_state->uapi.src.x1 >> 16;
0241     src_y = plane_state->uapi.src.y1 >> 16;
0242 
0243     /* Undocumented hardware limit on i965/g4x/vlv/chv */
0244     if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
0245         return -EINVAL;
0246 
0247     intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
0248 
0249     if (DISPLAY_VER(dev_priv) >= 4)
0250         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
0251                                 plane_state, 0);
0252     else
0253         offset = 0;
0254 
0255     /*
0256      * When using an X-tiled surface the plane starts to
0257      * misbehave if the x offset + width exceeds the stride.
0258      * hsw/bdw: underrun galore
0259      * ilk/snb/ivb: wrap to the next tile row mid scanout
0260      * i965/g4x: so far appear immune to this
0261      * vlv/chv: TODO check
0262      *
0263      * Linear surfaces seem to work just fine, even on hsw/bdw
0264      * despite them not using the linear offset anymore.
0265      */
0266     if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {
0267         u32 alignment = intel_surf_alignment(fb, 0);
0268         int cpp = fb->format->cpp[0];
0269 
0270         while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) {
0271             if (offset == 0) {
0272                 drm_dbg_kms(&dev_priv->drm,
0273                         "Unable to find suitable display surface offset due to X-tiling\n");
0274                 return -EINVAL;
0275             }
0276 
0277             offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0,
0278                                    offset, offset - alignment);
0279         }
0280     }
0281 
0282     /*
0283      * Put the final coordinates back so that the src
0284      * coordinate checks will see the right values.
0285      */
0286     drm_rect_translate_to(&plane_state->uapi.src,
0287                   src_x << 16, src_y << 16);
0288 
0289     /* HSW/BDW do this automagically in hardware */
0290     if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
0291         unsigned int rotation = plane_state->hw.rotation;
0292         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
0293         int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
0294 
0295         if (rotation & DRM_MODE_ROTATE_180) {
0296             src_x += src_w - 1;
0297             src_y += src_h - 1;
0298         } else if (rotation & DRM_MODE_REFLECT_X) {
0299             src_x += src_w - 1;
0300         }
0301     }
0302 
0303     if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0304         drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095);
0305     } else if (DISPLAY_VER(dev_priv) >= 4 &&
0306            fb->modifier == I915_FORMAT_MOD_X_TILED) {
0307         drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095);
0308     }
0309 
0310     plane_state->view.color_plane[0].offset = offset;
0311     plane_state->view.color_plane[0].x = src_x;
0312     plane_state->view.color_plane[0].y = src_y;
0313 
0314     return 0;
0315 }
0316 
0317 static int
0318 i9xx_plane_check(struct intel_crtc_state *crtc_state,
0319          struct intel_plane_state *plane_state)
0320 {
0321     struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
0322     int ret;
0323 
0324     ret = chv_plane_check_rotation(plane_state);
0325     if (ret)
0326         return ret;
0327 
0328     ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
0329                         DRM_PLANE_HELPER_NO_SCALING,
0330                         DRM_PLANE_HELPER_NO_SCALING,
0331                         i9xx_plane_has_windowing(plane));
0332     if (ret)
0333         return ret;
0334 
0335     ret = i9xx_check_plane_surface(plane_state);
0336     if (ret)
0337         return ret;
0338 
0339     if (!plane_state->uapi.visible)
0340         return 0;
0341 
0342     ret = intel_plane_check_src_coordinates(plane_state);
0343     if (ret)
0344         return ret;
0345 
0346     plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
0347 
0348     return 0;
0349 }
0350 
0351 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
0352 {
0353     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0354     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0355     u32 dspcntr = 0;
0356 
0357     if (crtc_state->gamma_enable)
0358         dspcntr |= DISP_PIPE_GAMMA_ENABLE;
0359 
0360     if (crtc_state->csc_enable)
0361         dspcntr |= DISP_PIPE_CSC_ENABLE;
0362 
0363     if (DISPLAY_VER(dev_priv) < 5)
0364         dspcntr |= DISP_PIPE_SEL(crtc->pipe);
0365 
0366     return dspcntr;
0367 }
0368 
0369 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
0370                  const struct intel_plane_state *plane_state,
0371                  unsigned int *num, unsigned int *den)
0372 {
0373     const struct drm_framebuffer *fb = plane_state->hw.fb;
0374     unsigned int cpp = fb->format->cpp[0];
0375 
0376     /*
0377      * g4x bspec says 64bpp pixel rate can't exceed 80%
0378      * of cdclk when the sprite plane is enabled on the
0379      * same pipe. ilk/snb bspec says 64bpp pixel rate is
0380      * never allowed to exceed 80% of cdclk. Let's just go
0381      * with the ilk/snb limit always.
0382      */
0383     if (cpp == 8) {
0384         *num = 10;
0385         *den = 8;
0386     } else {
0387         *num = 1;
0388         *den = 1;
0389     }
0390 }
0391 
0392 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
0393                 const struct intel_plane_state *plane_state)
0394 {
0395     unsigned int pixel_rate;
0396     unsigned int num, den;
0397 
0398     /*
0399      * Note that crtc_state->pixel_rate accounts for both
0400      * horizontal and vertical panel fitter downscaling factors.
0401      * Pre-HSW bspec tells us to only consider the horizontal
0402      * downscaling factor here. We ignore that and just consider
0403      * both for simplicity.
0404      */
0405     pixel_rate = crtc_state->pixel_rate;
0406 
0407     i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
0408 
0409     /* two pixels per clock with double wide pipe */
0410     if (crtc_state->double_wide)
0411         den *= 2;
0412 
0413     return DIV_ROUND_UP(pixel_rate * num, den);
0414 }
0415 
0416 static void i9xx_plane_update_noarm(struct intel_plane *plane,
0417                     const struct intel_crtc_state *crtc_state,
0418                     const struct intel_plane_state *plane_state)
0419 {
0420     struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
0421     enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
0422 
0423     intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
0424               plane_state->view.color_plane[0].mapping_stride);
0425 
0426     if (DISPLAY_VER(dev_priv) < 4) {
0427         int crtc_x = plane_state->uapi.dst.x1;
0428         int crtc_y = plane_state->uapi.dst.y1;
0429         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
0430         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
0431 
0432         /*
0433          * PLANE_A doesn't actually have a full window
0434          * generator but let's assume we still need to
0435          * program whatever is there.
0436          */
0437         intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
0438                   DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
0439         intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
0440                   DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));
0441     }
0442 }
0443 
0444 static void i9xx_plane_update_arm(struct intel_plane *plane,
0445                   const struct intel_crtc_state *crtc_state,
0446                   const struct intel_plane_state *plane_state)
0447 {
0448     struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
0449     enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
0450     int x = plane_state->view.color_plane[0].x;
0451     int y = plane_state->view.color_plane[0].y;
0452     u32 dspcntr, dspaddr_offset, linear_offset;
0453 
0454     dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
0455 
0456     linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
0457 
0458     if (DISPLAY_VER(dev_priv) >= 4)
0459         dspaddr_offset = plane_state->view.color_plane[0].offset;
0460     else
0461         dspaddr_offset = linear_offset;
0462 
0463     if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
0464         int crtc_x = plane_state->uapi.dst.x1;
0465         int crtc_y = plane_state->uapi.dst.y1;
0466         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
0467         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
0468 
0469         intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
0470                   PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
0471         intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
0472                   PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
0473         intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
0474     }
0475 
0476     if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
0477         intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
0478                   DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
0479     } else if (DISPLAY_VER(dev_priv) >= 4) {
0480         intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
0481                   linear_offset);
0482         intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
0483                   DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
0484     }
0485 
0486     /*
0487      * The control register self-arms if the plane was previously
0488      * disabled. Try to make the plane enable atomic by writing
0489      * the control register just before the surface register.
0490      */
0491     intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
0492 
0493     if (DISPLAY_VER(dev_priv) >= 4)
0494         intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
0495                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
0496     else
0497         intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
0498                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
0499 }
0500 
0501 static void i830_plane_update_arm(struct intel_plane *plane,
0502                   const struct intel_crtc_state *crtc_state,
0503                   const struct intel_plane_state *plane_state)
0504 {
0505     /*
0506      * On i830/i845 all registers are self-arming [ALM040].
0507      *
0508      * Additional breakage on i830 causes register reads to return
0509      * the last latched value instead of the last written value [ALM026].
0510      */
0511     i9xx_plane_update_noarm(plane, crtc_state, plane_state);
0512     i9xx_plane_update_arm(plane, crtc_state, plane_state);
0513 }
0514 
0515 static void i9xx_plane_disable_arm(struct intel_plane *plane,
0516                    const struct intel_crtc_state *crtc_state)
0517 {
0518     struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
0519     enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
0520     u32 dspcntr;
0521 
0522     /*
0523      * DSPCNTR pipe gamma enable on g4x+ and pipe csc
0524      * enable on ilk+ affect the pipe bottom color as
0525      * well, so we must configure them even if the plane
0526      * is disabled.
0527      *
0528      * On pre-g4x there is no way to gamma correct the
0529      * pipe bottom color but we'll keep on doing this
0530      * anyway so that the crtc state readout works correctly.
0531      */
0532     dspcntr = i9xx_plane_ctl_crtc(crtc_state);
0533 
0534     intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
0535 
0536     if (DISPLAY_VER(dev_priv) >= 4)
0537         intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
0538     else
0539         intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
0540 }
0541 
0542 static void
0543 g4x_primary_async_flip(struct intel_plane *plane,
0544                const struct intel_crtc_state *crtc_state,
0545                const struct intel_plane_state *plane_state,
0546                bool async_flip)
0547 {
0548     struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
0549     u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
0550     u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
0551     enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
0552 
0553     if (async_flip)
0554         dspcntr |= DISP_ASYNC_FLIP;
0555 
0556     intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
0557 
0558     intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
0559               intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
0560 }
0561 
0562 static void
0563 vlv_primary_async_flip(struct intel_plane *plane,
0564                const struct intel_crtc_state *crtc_state,
0565                const struct intel_plane_state *plane_state,
0566                bool async_flip)
0567 {
0568     struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
0569     u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
0570     enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
0571 
0572     intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
0573               intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
0574 }
0575 
0576 static void
0577 bdw_primary_enable_flip_done(struct intel_plane *plane)
0578 {
0579     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0580     enum pipe pipe = plane->pipe;
0581 
0582     spin_lock_irq(&i915->irq_lock);
0583     bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
0584     spin_unlock_irq(&i915->irq_lock);
0585 }
0586 
0587 static void
0588 bdw_primary_disable_flip_done(struct intel_plane *plane)
0589 {
0590     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0591     enum pipe pipe = plane->pipe;
0592 
0593     spin_lock_irq(&i915->irq_lock);
0594     bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
0595     spin_unlock_irq(&i915->irq_lock);
0596 }
0597 
0598 static void
0599 ivb_primary_enable_flip_done(struct intel_plane *plane)
0600 {
0601     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0602 
0603     spin_lock_irq(&i915->irq_lock);
0604     ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
0605     spin_unlock_irq(&i915->irq_lock);
0606 }
0607 
0608 static void
0609 ivb_primary_disable_flip_done(struct intel_plane *plane)
0610 {
0611     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0612 
0613     spin_lock_irq(&i915->irq_lock);
0614     ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
0615     spin_unlock_irq(&i915->irq_lock);
0616 }
0617 
0618 static void
0619 ilk_primary_enable_flip_done(struct intel_plane *plane)
0620 {
0621     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0622 
0623     spin_lock_irq(&i915->irq_lock);
0624     ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
0625     spin_unlock_irq(&i915->irq_lock);
0626 }
0627 
0628 static void
0629 ilk_primary_disable_flip_done(struct intel_plane *plane)
0630 {
0631     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0632 
0633     spin_lock_irq(&i915->irq_lock);
0634     ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
0635     spin_unlock_irq(&i915->irq_lock);
0636 }
0637 
0638 static void
0639 vlv_primary_enable_flip_done(struct intel_plane *plane)
0640 {
0641     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0642     enum pipe pipe = plane->pipe;
0643 
0644     spin_lock_irq(&i915->irq_lock);
0645     i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
0646     spin_unlock_irq(&i915->irq_lock);
0647 }
0648 
0649 static void
0650 vlv_primary_disable_flip_done(struct intel_plane *plane)
0651 {
0652     struct drm_i915_private *i915 = to_i915(plane->base.dev);
0653     enum pipe pipe = plane->pipe;
0654 
0655     spin_lock_irq(&i915->irq_lock);
0656     i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
0657     spin_unlock_irq(&i915->irq_lock);
0658 }
0659 
0660 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
0661                     enum pipe *pipe)
0662 {
0663     struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
0664     enum intel_display_power_domain power_domain;
0665     enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
0666     intel_wakeref_t wakeref;
0667     bool ret;
0668     u32 val;
0669 
0670     /*
0671      * Not 100% correct for planes that can move between pipes,
0672      * but that's only the case for gen2-4 which don't have any
0673      * display power wells.
0674      */
0675     power_domain = POWER_DOMAIN_PIPE(plane->pipe);
0676     wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
0677     if (!wakeref)
0678         return false;
0679 
0680     val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
0681 
0682     ret = val & DISP_ENABLE;
0683 
0684     if (DISPLAY_VER(dev_priv) >= 5)
0685         *pipe = plane->pipe;
0686     else
0687         *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);
0688 
0689     intel_display_power_put(dev_priv, power_domain, wakeref);
0690 
0691     return ret;
0692 }
0693 
0694 static unsigned int
0695 hsw_primary_max_stride(struct intel_plane *plane,
0696                u32 pixel_format, u64 modifier,
0697                unsigned int rotation)
0698 {
0699     const struct drm_format_info *info = drm_format_info(pixel_format);
0700     int cpp = info->cpp[0];
0701 
0702     /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */
0703     return min(8192 * cpp, 32 * 1024);
0704 }
0705 
0706 static unsigned int
0707 ilk_primary_max_stride(struct intel_plane *plane,
0708                u32 pixel_format, u64 modifier,
0709                unsigned int rotation)
0710 {
0711     const struct drm_format_info *info = drm_format_info(pixel_format);
0712     int cpp = info->cpp[0];
0713 
0714     /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
0715     if (modifier == I915_FORMAT_MOD_X_TILED)
0716         return min(4096 * cpp, 32 * 1024);
0717     else
0718         return 32 * 1024;
0719 }
0720 
0721 unsigned int
0722 i965_plane_max_stride(struct intel_plane *plane,
0723               u32 pixel_format, u64 modifier,
0724               unsigned int rotation)
0725 {
0726     const struct drm_format_info *info = drm_format_info(pixel_format);
0727     int cpp = info->cpp[0];
0728 
0729     /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
0730     if (modifier == I915_FORMAT_MOD_X_TILED)
0731         return min(4096 * cpp, 16 * 1024);
0732     else
0733         return 32 * 1024;
0734 }
0735 
0736 static unsigned int
0737 i9xx_plane_max_stride(struct intel_plane *plane,
0738               u32 pixel_format, u64 modifier,
0739               unsigned int rotation)
0740 {
0741     struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
0742 
0743     if (DISPLAY_VER(dev_priv) >= 3) {
0744         if (modifier == I915_FORMAT_MOD_X_TILED)
0745             return 8*1024;
0746         else
0747             return 16*1024;
0748     } else {
0749         if (plane->i9xx_plane == PLANE_C)
0750             return 4*1024;
0751         else
0752             return 8*1024;
0753     }
0754 }
0755 
0756 static const struct drm_plane_funcs i965_plane_funcs = {
0757     .update_plane = drm_atomic_helper_update_plane,
0758     .disable_plane = drm_atomic_helper_disable_plane,
0759     .destroy = intel_plane_destroy,
0760     .atomic_duplicate_state = intel_plane_duplicate_state,
0761     .atomic_destroy_state = intel_plane_destroy_state,
0762     .format_mod_supported = i965_plane_format_mod_supported,
0763 };
0764 
0765 static const struct drm_plane_funcs i8xx_plane_funcs = {
0766     .update_plane = drm_atomic_helper_update_plane,
0767     .disable_plane = drm_atomic_helper_disable_plane,
0768     .destroy = intel_plane_destroy,
0769     .atomic_duplicate_state = intel_plane_duplicate_state,
0770     .atomic_destroy_state = intel_plane_destroy_state,
0771     .format_mod_supported = i8xx_plane_format_mod_supported,
0772 };
0773 
0774 struct intel_plane *
0775 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
0776 {
0777     struct intel_plane *plane;
0778     const struct drm_plane_funcs *plane_funcs;
0779     unsigned int supported_rotations;
0780     const u64 *modifiers;
0781     const u32 *formats;
0782     int num_formats;
0783     int ret, zpos;
0784 
0785     plane = intel_plane_alloc();
0786     if (IS_ERR(plane))
0787         return plane;
0788 
0789     plane->pipe = pipe;
0790     /*
0791      * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
0792      * port is hooked to pipe B. Hence we want plane A feeding pipe B.
0793      */
0794     if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 &&
0795         INTEL_NUM_PIPES(dev_priv) == 2)
0796         plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
0797     else
0798         plane->i9xx_plane = (enum i9xx_plane_id) pipe;
0799     plane->id = PLANE_PRIMARY;
0800     plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
0801 
0802     intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane);
0803 
0804     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
0805         formats = vlv_primary_formats;
0806         num_formats = ARRAY_SIZE(vlv_primary_formats);
0807     } else if (DISPLAY_VER(dev_priv) >= 4) {
0808         /*
0809          * WaFP16GammaEnabling:ivb
0810          * "Workaround : When using the 64-bit format, the plane
0811          *  output on each color channel has one quarter amplitude.
0812          *  It can be brought up to full amplitude by using pipe
0813          *  gamma correction or pipe color space conversion to
0814          *  multiply the plane output by four."
0815          *
0816          * There is no dedicated plane gamma for the primary plane,
0817          * and using the pipe gamma/csc could conflict with other
0818          * planes, so we choose not to expose fp16 on IVB primary
0819          * planes. HSW primary planes no longer have this problem.
0820          */
0821         if (IS_IVYBRIDGE(dev_priv)) {
0822             formats = ivb_primary_formats;
0823             num_formats = ARRAY_SIZE(ivb_primary_formats);
0824         } else {
0825             formats = i965_primary_formats;
0826             num_formats = ARRAY_SIZE(i965_primary_formats);
0827         }
0828     } else {
0829         formats = i8xx_primary_formats;
0830         num_formats = ARRAY_SIZE(i8xx_primary_formats);
0831     }
0832 
0833     if (DISPLAY_VER(dev_priv) >= 4)
0834         plane_funcs = &i965_plane_funcs;
0835     else
0836         plane_funcs = &i8xx_plane_funcs;
0837 
0838     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0839         plane->min_cdclk = vlv_plane_min_cdclk;
0840     else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
0841         plane->min_cdclk = hsw_plane_min_cdclk;
0842     else if (IS_IVYBRIDGE(dev_priv))
0843         plane->min_cdclk = ivb_plane_min_cdclk;
0844     else
0845         plane->min_cdclk = i9xx_plane_min_cdclk;
0846 
0847     if (HAS_GMCH(dev_priv)) {
0848         if (DISPLAY_VER(dev_priv) >= 4)
0849             plane->max_stride = i965_plane_max_stride;
0850         else
0851             plane->max_stride = i9xx_plane_max_stride;
0852     } else {
0853         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
0854             plane->max_stride = hsw_primary_max_stride;
0855         else
0856             plane->max_stride = ilk_primary_max_stride;
0857     }
0858 
0859     if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
0860         plane->update_arm = i830_plane_update_arm;
0861     } else {
0862         plane->update_noarm = i9xx_plane_update_noarm;
0863         plane->update_arm = i9xx_plane_update_arm;
0864     }
0865     plane->disable_arm = i9xx_plane_disable_arm;
0866     plane->get_hw_state = i9xx_plane_get_hw_state;
0867     plane->check_plane = i9xx_plane_check;
0868 
0869     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
0870         plane->async_flip = vlv_primary_async_flip;
0871         plane->enable_flip_done = vlv_primary_enable_flip_done;
0872         plane->disable_flip_done = vlv_primary_disable_flip_done;
0873     } else if (IS_BROADWELL(dev_priv)) {
0874         plane->need_async_flip_disable_wa = true;
0875         plane->async_flip = g4x_primary_async_flip;
0876         plane->enable_flip_done = bdw_primary_enable_flip_done;
0877         plane->disable_flip_done = bdw_primary_disable_flip_done;
0878     } else if (DISPLAY_VER(dev_priv) >= 7) {
0879         plane->async_flip = g4x_primary_async_flip;
0880         plane->enable_flip_done = ivb_primary_enable_flip_done;
0881         plane->disable_flip_done = ivb_primary_disable_flip_done;
0882     } else if (DISPLAY_VER(dev_priv) >= 5) {
0883         plane->async_flip = g4x_primary_async_flip;
0884         plane->enable_flip_done = ilk_primary_enable_flip_done;
0885         plane->disable_flip_done = ilk_primary_disable_flip_done;
0886     }
0887 
0888     modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);
0889 
0890     if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
0891         ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0892                            0, plane_funcs,
0893                            formats, num_formats,
0894                            modifiers,
0895                            DRM_PLANE_TYPE_PRIMARY,
0896                            "primary %c", pipe_name(pipe));
0897     else
0898         ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0899                            0, plane_funcs,
0900                            formats, num_formats,
0901                            modifiers,
0902                            DRM_PLANE_TYPE_PRIMARY,
0903                            "plane %c",
0904                            plane_name(plane->i9xx_plane));
0905 
0906     kfree(modifiers);
0907 
0908     if (ret)
0909         goto fail;
0910 
0911     if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
0912         supported_rotations =
0913             DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
0914             DRM_MODE_REFLECT_X;
0915     } else if (DISPLAY_VER(dev_priv) >= 4) {
0916         supported_rotations =
0917             DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
0918     } else {
0919         supported_rotations = DRM_MODE_ROTATE_0;
0920     }
0921 
0922     if (DISPLAY_VER(dev_priv) >= 4)
0923         drm_plane_create_rotation_property(&plane->base,
0924                            DRM_MODE_ROTATE_0,
0925                            supported_rotations);
0926 
0927     zpos = 0;
0928     drm_plane_create_zpos_immutable_property(&plane->base, zpos);
0929 
0930     intel_plane_helper_add(plane);
0931 
0932     return plane;
0933 
0934 fail:
0935     intel_plane_free(plane);
0936 
0937     return ERR_PTR(ret);
0938 }
0939 
0940 static int i9xx_format_to_fourcc(int format)
0941 {
0942     switch (format) {
0943     case DISP_FORMAT_8BPP:
0944         return DRM_FORMAT_C8;
0945     case DISP_FORMAT_BGRA555:
0946         return DRM_FORMAT_ARGB1555;
0947     case DISP_FORMAT_BGRX555:
0948         return DRM_FORMAT_XRGB1555;
0949     case DISP_FORMAT_BGRX565:
0950         return DRM_FORMAT_RGB565;
0951     default:
0952     case DISP_FORMAT_BGRX888:
0953         return DRM_FORMAT_XRGB8888;
0954     case DISP_FORMAT_RGBX888:
0955         return DRM_FORMAT_XBGR8888;
0956     case DISP_FORMAT_BGRA888:
0957         return DRM_FORMAT_ARGB8888;
0958     case DISP_FORMAT_RGBA888:
0959         return DRM_FORMAT_ABGR8888;
0960     case DISP_FORMAT_BGRX101010:
0961         return DRM_FORMAT_XRGB2101010;
0962     case DISP_FORMAT_RGBX101010:
0963         return DRM_FORMAT_XBGR2101010;
0964     case DISP_FORMAT_BGRA101010:
0965         return DRM_FORMAT_ARGB2101010;
0966     case DISP_FORMAT_RGBA101010:
0967         return DRM_FORMAT_ABGR2101010;
0968     case DISP_FORMAT_RGBX161616:
0969         return DRM_FORMAT_XBGR16161616F;
0970     }
0971 }
0972 
0973 void
0974 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
0975                   struct intel_initial_plane_config *plane_config)
0976 {
0977     struct drm_device *dev = crtc->base.dev;
0978     struct drm_i915_private *dev_priv = to_i915(dev);
0979     struct intel_plane *plane = to_intel_plane(crtc->base.primary);
0980     enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
0981     enum pipe pipe;
0982     u32 val, base, offset;
0983     int fourcc, pixel_format;
0984     unsigned int aligned_height;
0985     struct drm_framebuffer *fb;
0986     struct intel_framebuffer *intel_fb;
0987 
0988     if (!plane->get_hw_state(plane, &pipe))
0989         return;
0990 
0991     drm_WARN_ON(dev, pipe != crtc->pipe);
0992 
0993     intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
0994     if (!intel_fb) {
0995         drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
0996         return;
0997     }
0998 
0999     fb = &intel_fb->base;
1000 
1001     fb->dev = dev;
1002 
1003     val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
1004 
1005     if (DISPLAY_VER(dev_priv) >= 4) {
1006         if (val & DISP_TILED) {
1007             plane_config->tiling = I915_TILING_X;
1008             fb->modifier = I915_FORMAT_MOD_X_TILED;
1009         }
1010 
1011         if (val & DISP_ROTATE_180)
1012             plane_config->rotation = DRM_MODE_ROTATE_180;
1013     }
1014 
1015     if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
1016         val & DISP_MIRROR)
1017         plane_config->rotation |= DRM_MODE_REFLECT_X;
1018 
1019     pixel_format = val & DISP_FORMAT_MASK;
1020     fourcc = i9xx_format_to_fourcc(pixel_format);
1021     fb->format = drm_format_info(fourcc);
1022 
1023     if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1024         offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
1025         base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
1026     } else if (DISPLAY_VER(dev_priv) >= 4) {
1027         if (plane_config->tiling)
1028             offset = intel_de_read(dev_priv,
1029                            DSPTILEOFF(i9xx_plane));
1030         else
1031             offset = intel_de_read(dev_priv,
1032                            DSPLINOFF(i9xx_plane));
1033         base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
1034     } else {
1035         base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
1036     }
1037     plane_config->base = base;
1038 
1039     val = intel_de_read(dev_priv, PIPESRC(pipe));
1040     fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
1041     fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
1042 
1043     val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
1044     fb->pitches[0] = val & 0xffffffc0;
1045 
1046     aligned_height = intel_fb_align_height(fb, 0, fb->height);
1047 
1048     plane_config->size = fb->pitches[0] * aligned_height;
1049 
1050     drm_dbg_kms(&dev_priv->drm,
1051             "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
1052             crtc->base.name, plane->base.name, fb->width, fb->height,
1053             fb->format->cpp[0] * 8, base, fb->pitches[0],
1054             plane_config->size);
1055 
1056     plane_config->fb = intel_fb;
1057 }
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