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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2020 Intel Corporation
0004  *
0005  * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
0006  */
0007 
0008 #include "g4x_hdmi.h"
0009 #include "intel_audio.h"
0010 #include "intel_connector.h"
0011 #include "intel_crtc.h"
0012 #include "intel_de.h"
0013 #include "intel_display_power.h"
0014 #include "intel_display_types.h"
0015 #include "intel_dpio_phy.h"
0016 #include "intel_fifo_underrun.h"
0017 #include "intel_hdmi.h"
0018 #include "intel_hotplug.h"
0019 #include "intel_sdvo.h"
0020 #include "vlv_sideband.h"
0021 
0022 static void intel_hdmi_prepare(struct intel_encoder *encoder,
0023                    const struct intel_crtc_state *crtc_state)
0024 {
0025     struct drm_device *dev = encoder->base.dev;
0026     struct drm_i915_private *dev_priv = to_i915(dev);
0027     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0028     struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
0029     const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
0030     u32 hdmi_val;
0031 
0032     intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0033 
0034     hdmi_val = SDVO_ENCODING_HDMI;
0035     if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
0036         hdmi_val |= HDMI_COLOR_RANGE_16_235;
0037     if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
0038         hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
0039     if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
0040         hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
0041 
0042     if (crtc_state->pipe_bpp > 24)
0043         hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
0044     else
0045         hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
0046 
0047     if (crtc_state->has_hdmi_sink)
0048         hdmi_val |= HDMI_MODE_SELECT_HDMI;
0049 
0050     if (HAS_PCH_CPT(dev_priv))
0051         hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
0052     else if (IS_CHERRYVIEW(dev_priv))
0053         hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
0054     else
0055         hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
0056 
0057     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
0058     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0059 }
0060 
0061 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
0062                     enum pipe *pipe)
0063 {
0064     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0065     struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
0066     intel_wakeref_t wakeref;
0067     bool ret;
0068 
0069     wakeref = intel_display_power_get_if_enabled(dev_priv,
0070                              encoder->power_domain);
0071     if (!wakeref)
0072         return false;
0073 
0074     ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
0075 
0076     intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
0077 
0078     return ret;
0079 }
0080 
0081 static void intel_hdmi_get_config(struct intel_encoder *encoder,
0082                   struct intel_crtc_state *pipe_config)
0083 {
0084     struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
0085     struct drm_device *dev = encoder->base.dev;
0086     struct drm_i915_private *dev_priv = to_i915(dev);
0087     u32 tmp, flags = 0;
0088     int dotclock;
0089 
0090     pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
0091 
0092     tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
0093 
0094     if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
0095         flags |= DRM_MODE_FLAG_PHSYNC;
0096     else
0097         flags |= DRM_MODE_FLAG_NHSYNC;
0098 
0099     if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
0100         flags |= DRM_MODE_FLAG_PVSYNC;
0101     else
0102         flags |= DRM_MODE_FLAG_NVSYNC;
0103 
0104     if (tmp & HDMI_MODE_SELECT_HDMI)
0105         pipe_config->has_hdmi_sink = true;
0106 
0107     pipe_config->infoframes.enable |=
0108         intel_hdmi_infoframes_enabled(encoder, pipe_config);
0109 
0110     if (pipe_config->infoframes.enable)
0111         pipe_config->has_infoframe = true;
0112 
0113     if (tmp & HDMI_AUDIO_ENABLE)
0114         pipe_config->has_audio = true;
0115 
0116     if (!HAS_PCH_SPLIT(dev_priv) &&
0117         tmp & HDMI_COLOR_RANGE_16_235)
0118         pipe_config->limited_color_range = true;
0119 
0120     pipe_config->hw.adjusted_mode.flags |= flags;
0121 
0122     if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
0123         dotclock = pipe_config->port_clock * 2 / 3;
0124     else
0125         dotclock = pipe_config->port_clock;
0126 
0127     if (pipe_config->pixel_multiplier)
0128         dotclock /= pipe_config->pixel_multiplier;
0129 
0130     pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
0131 
0132     pipe_config->lane_count = 4;
0133 
0134     intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
0135 
0136     intel_read_infoframe(encoder, pipe_config,
0137                  HDMI_INFOFRAME_TYPE_AVI,
0138                  &pipe_config->infoframes.avi);
0139     intel_read_infoframe(encoder, pipe_config,
0140                  HDMI_INFOFRAME_TYPE_SPD,
0141                  &pipe_config->infoframes.spd);
0142     intel_read_infoframe(encoder, pipe_config,
0143                  HDMI_INFOFRAME_TYPE_VENDOR,
0144                  &pipe_config->infoframes.hdmi);
0145 }
0146 
0147 static void g4x_enable_hdmi(struct intel_atomic_state *state,
0148                 struct intel_encoder *encoder,
0149                 const struct intel_crtc_state *pipe_config,
0150                 const struct drm_connector_state *conn_state)
0151 {
0152     struct drm_device *dev = encoder->base.dev;
0153     struct drm_i915_private *dev_priv = to_i915(dev);
0154     struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
0155     u32 temp;
0156 
0157     temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
0158 
0159     temp |= SDVO_ENABLE;
0160     if (pipe_config->has_audio)
0161         temp |= HDMI_AUDIO_ENABLE;
0162 
0163     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0164     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0165 
0166     drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
0167             !pipe_config->has_hdmi_sink);
0168     intel_audio_codec_enable(encoder, pipe_config, conn_state);
0169 }
0170 
0171 static void ibx_enable_hdmi(struct intel_atomic_state *state,
0172                 struct intel_encoder *encoder,
0173                 const struct intel_crtc_state *pipe_config,
0174                 const struct drm_connector_state *conn_state)
0175 {
0176     struct drm_device *dev = encoder->base.dev;
0177     struct drm_i915_private *dev_priv = to_i915(dev);
0178     struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
0179     u32 temp;
0180 
0181     temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
0182 
0183     temp |= SDVO_ENABLE;
0184     if (pipe_config->has_audio)
0185         temp |= HDMI_AUDIO_ENABLE;
0186 
0187     /*
0188      * HW workaround, need to write this twice for issue
0189      * that may result in first write getting masked.
0190      */
0191     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0192     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0193     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0194     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0195 
0196     /*
0197      * HW workaround, need to toggle enable bit off and on
0198      * for 12bpc with pixel repeat.
0199      *
0200      * FIXME: BSpec says this should be done at the end of
0201      * the modeset sequence, so not sure if this isn't too soon.
0202      */
0203     if (pipe_config->pipe_bpp > 24 &&
0204         pipe_config->pixel_multiplier > 1) {
0205         intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
0206                    temp & ~SDVO_ENABLE);
0207         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0208 
0209         /*
0210          * HW workaround, need to write this twice for issue
0211          * that may result in first write getting masked.
0212          */
0213         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0214         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0215         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0216         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0217     }
0218 
0219     drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
0220             !pipe_config->has_hdmi_sink);
0221     intel_audio_codec_enable(encoder, pipe_config, conn_state);
0222 }
0223 
0224 static void cpt_enable_hdmi(struct intel_atomic_state *state,
0225                 struct intel_encoder *encoder,
0226                 const struct intel_crtc_state *pipe_config,
0227                 const struct drm_connector_state *conn_state)
0228 {
0229     struct drm_device *dev = encoder->base.dev;
0230     struct drm_i915_private *dev_priv = to_i915(dev);
0231     struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
0232     struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
0233     enum pipe pipe = crtc->pipe;
0234     u32 temp;
0235 
0236     temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
0237 
0238     temp |= SDVO_ENABLE;
0239     if (pipe_config->has_audio)
0240         temp |= HDMI_AUDIO_ENABLE;
0241 
0242     /*
0243      * WaEnableHDMI8bpcBefore12bpc:snb,ivb
0244      *
0245      * The procedure for 12bpc is as follows:
0246      * 1. disable HDMI clock gating
0247      * 2. enable HDMI with 8bpc
0248      * 3. enable HDMI with 12bpc
0249      * 4. enable HDMI clock gating
0250      */
0251 
0252     if (pipe_config->pipe_bpp > 24) {
0253         intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
0254                    intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
0255 
0256         temp &= ~SDVO_COLOR_FORMAT_MASK;
0257         temp |= SDVO_COLOR_FORMAT_8bpc;
0258     }
0259 
0260     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0261     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0262 
0263     if (pipe_config->pipe_bpp > 24) {
0264         temp &= ~SDVO_COLOR_FORMAT_MASK;
0265         temp |= HDMI_COLOR_FORMAT_12bpc;
0266 
0267         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0268         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0269 
0270         intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
0271                    intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
0272     }
0273 
0274     drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
0275             !pipe_config->has_hdmi_sink);
0276     intel_audio_codec_enable(encoder, pipe_config, conn_state);
0277 }
0278 
0279 static void vlv_enable_hdmi(struct intel_atomic_state *state,
0280                 struct intel_encoder *encoder,
0281                 const struct intel_crtc_state *pipe_config,
0282                 const struct drm_connector_state *conn_state)
0283 {
0284 }
0285 
0286 static void intel_disable_hdmi(struct intel_atomic_state *state,
0287                    struct intel_encoder *encoder,
0288                    const struct intel_crtc_state *old_crtc_state,
0289                    const struct drm_connector_state *old_conn_state)
0290 {
0291     struct drm_device *dev = encoder->base.dev;
0292     struct drm_i915_private *dev_priv = to_i915(dev);
0293     struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
0294     struct intel_digital_port *dig_port =
0295         hdmi_to_dig_port(intel_hdmi);
0296     struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
0297     u32 temp;
0298 
0299     temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
0300 
0301     temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
0302     intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0303     intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0304 
0305     /*
0306      * HW workaround for IBX, we need to move the port
0307      * to transcoder A after disabling it to allow the
0308      * matching DP port to be enabled on transcoder A.
0309      */
0310     if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0311         /*
0312          * We get CPU/PCH FIFO underruns on the other pipe when
0313          * doing the workaround. Sweep them under the rug.
0314          */
0315         intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
0316         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
0317 
0318         temp &= ~SDVO_PIPE_SEL_MASK;
0319         temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
0320         /*
0321          * HW workaround, need to write this twice for issue
0322          * that may result in first write getting masked.
0323          */
0324         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0325         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0326         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0327         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0328 
0329         temp &= ~SDVO_ENABLE;
0330         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
0331         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
0332 
0333         intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0334         intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
0335         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
0336     }
0337 
0338     dig_port->set_infoframes(encoder,
0339                        false,
0340                        old_crtc_state, old_conn_state);
0341 
0342     intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
0343 }
0344 
0345 static void g4x_disable_hdmi(struct intel_atomic_state *state,
0346                  struct intel_encoder *encoder,
0347                  const struct intel_crtc_state *old_crtc_state,
0348                  const struct drm_connector_state *old_conn_state)
0349 {
0350     intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
0351 
0352     intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
0353 }
0354 
0355 static void pch_disable_hdmi(struct intel_atomic_state *state,
0356                  struct intel_encoder *encoder,
0357                  const struct intel_crtc_state *old_crtc_state,
0358                  const struct drm_connector_state *old_conn_state)
0359 {
0360     intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
0361 }
0362 
0363 static void pch_post_disable_hdmi(struct intel_atomic_state *state,
0364                   struct intel_encoder *encoder,
0365                   const struct intel_crtc_state *old_crtc_state,
0366                   const struct drm_connector_state *old_conn_state)
0367 {
0368     intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
0369 }
0370 
0371 static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
0372                   struct intel_encoder *encoder,
0373                   const struct intel_crtc_state *pipe_config,
0374                   const struct drm_connector_state *conn_state)
0375 {
0376     struct intel_digital_port *dig_port =
0377         enc_to_dig_port(encoder);
0378 
0379     intel_hdmi_prepare(encoder, pipe_config);
0380 
0381     dig_port->set_infoframes(encoder,
0382                        pipe_config->has_infoframe,
0383                        pipe_config, conn_state);
0384 }
0385 
0386 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
0387                 struct intel_encoder *encoder,
0388                 const struct intel_crtc_state *pipe_config,
0389                 const struct drm_connector_state *conn_state)
0390 {
0391     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
0392     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0393 
0394     vlv_phy_pre_encoder_enable(encoder, pipe_config);
0395 
0396     /* HDMI 1.0V-2dB */
0397     vlv_set_phy_signal_level(encoder, pipe_config,
0398                  0x2b245f5f, 0x00002000,
0399                  0x5578b83a, 0x2b247878);
0400 
0401     dig_port->set_infoframes(encoder,
0402                   pipe_config->has_infoframe,
0403                   pipe_config, conn_state);
0404 
0405     g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
0406 
0407     vlv_wait_port_ready(dev_priv, dig_port, 0x0);
0408 }
0409 
0410 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
0411                     struct intel_encoder *encoder,
0412                     const struct intel_crtc_state *pipe_config,
0413                     const struct drm_connector_state *conn_state)
0414 {
0415     intel_hdmi_prepare(encoder, pipe_config);
0416 
0417     vlv_phy_pre_pll_enable(encoder, pipe_config);
0418 }
0419 
0420 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
0421                     struct intel_encoder *encoder,
0422                     const struct intel_crtc_state *pipe_config,
0423                     const struct drm_connector_state *conn_state)
0424 {
0425     intel_hdmi_prepare(encoder, pipe_config);
0426 
0427     chv_phy_pre_pll_enable(encoder, pipe_config);
0428 }
0429 
0430 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
0431                       struct intel_encoder *encoder,
0432                       const struct intel_crtc_state *old_crtc_state,
0433                       const struct drm_connector_state *old_conn_state)
0434 {
0435     chv_phy_post_pll_disable(encoder, old_crtc_state);
0436 }
0437 
0438 static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
0439                   struct intel_encoder *encoder,
0440                   const struct intel_crtc_state *old_crtc_state,
0441                   const struct drm_connector_state *old_conn_state)
0442 {
0443     /* Reset lanes to avoid HDMI flicker (VLV w/a) */
0444     vlv_phy_reset_lanes(encoder, old_crtc_state);
0445 }
0446 
0447 static void chv_hdmi_post_disable(struct intel_atomic_state *state,
0448                   struct intel_encoder *encoder,
0449                   const struct intel_crtc_state *old_crtc_state,
0450                   const struct drm_connector_state *old_conn_state)
0451 {
0452     struct drm_device *dev = encoder->base.dev;
0453     struct drm_i915_private *dev_priv = to_i915(dev);
0454 
0455     vlv_dpio_get(dev_priv);
0456 
0457     /* Assert data lane reset */
0458     chv_data_lane_soft_reset(encoder, old_crtc_state, true);
0459 
0460     vlv_dpio_put(dev_priv);
0461 }
0462 
0463 static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
0464                 struct intel_encoder *encoder,
0465                 const struct intel_crtc_state *pipe_config,
0466                 const struct drm_connector_state *conn_state)
0467 {
0468     struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
0469     struct drm_device *dev = encoder->base.dev;
0470     struct drm_i915_private *dev_priv = to_i915(dev);
0471 
0472     chv_phy_pre_encoder_enable(encoder, pipe_config);
0473 
0474     /* FIXME: Program the support xxx V-dB */
0475     /* Use 800mV-0dB */
0476     chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
0477 
0478     dig_port->set_infoframes(encoder,
0479                   pipe_config->has_infoframe,
0480                   pipe_config, conn_state);
0481 
0482     g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
0483 
0484     vlv_wait_port_ready(dev_priv, dig_port, 0x0);
0485 
0486     /* Second common lane will stay alive on its own now */
0487     chv_phy_release_cl2_override(encoder);
0488 }
0489 
0490 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
0491     .destroy = intel_encoder_destroy,
0492 };
0493 
0494 static enum intel_hotplug_state
0495 intel_hdmi_hotplug(struct intel_encoder *encoder,
0496            struct intel_connector *connector)
0497 {
0498     enum intel_hotplug_state state;
0499 
0500     state = intel_encoder_hotplug(encoder, connector);
0501 
0502     /*
0503      * On many platforms the HDMI live state signal is known to be
0504      * unreliable, so we can't use it to detect if a sink is connected or
0505      * not. Instead we detect if it's connected based on whether we can
0506      * read the EDID or not. That in turn has a problem during disconnect,
0507      * since the HPD interrupt may be raised before the DDC lines get
0508      * disconnected (due to how the required length of DDC vs. HPD
0509      * connector pins are specified) and so we'll still be able to get a
0510      * valid EDID. To solve this schedule another detection cycle if this
0511      * time around we didn't detect any change in the sink's connection
0512      * status.
0513      */
0514     if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
0515         state = INTEL_HOTPLUG_RETRY;
0516 
0517     return state;
0518 }
0519 
0520 void g4x_hdmi_init(struct drm_i915_private *dev_priv,
0521            i915_reg_t hdmi_reg, enum port port)
0522 {
0523     struct intel_digital_port *dig_port;
0524     struct intel_encoder *intel_encoder;
0525     struct intel_connector *intel_connector;
0526 
0527     dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
0528     if (!dig_port)
0529         return;
0530 
0531     intel_connector = intel_connector_alloc();
0532     if (!intel_connector) {
0533         kfree(dig_port);
0534         return;
0535     }
0536 
0537     intel_encoder = &dig_port->base;
0538 
0539     mutex_init(&dig_port->hdcp_mutex);
0540 
0541     drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
0542              &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
0543              "HDMI %c", port_name(port));
0544 
0545     intel_encoder->hotplug = intel_hdmi_hotplug;
0546     intel_encoder->compute_config = intel_hdmi_compute_config;
0547     if (HAS_PCH_SPLIT(dev_priv)) {
0548         intel_encoder->disable = pch_disable_hdmi;
0549         intel_encoder->post_disable = pch_post_disable_hdmi;
0550     } else {
0551         intel_encoder->disable = g4x_disable_hdmi;
0552     }
0553     intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
0554     intel_encoder->get_config = intel_hdmi_get_config;
0555     if (IS_CHERRYVIEW(dev_priv)) {
0556         intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
0557         intel_encoder->pre_enable = chv_hdmi_pre_enable;
0558         intel_encoder->enable = vlv_enable_hdmi;
0559         intel_encoder->post_disable = chv_hdmi_post_disable;
0560         intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
0561     } else if (IS_VALLEYVIEW(dev_priv)) {
0562         intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
0563         intel_encoder->pre_enable = vlv_hdmi_pre_enable;
0564         intel_encoder->enable = vlv_enable_hdmi;
0565         intel_encoder->post_disable = vlv_hdmi_post_disable;
0566     } else {
0567         intel_encoder->pre_enable = intel_hdmi_pre_enable;
0568         if (HAS_PCH_CPT(dev_priv))
0569             intel_encoder->enable = cpt_enable_hdmi;
0570         else if (HAS_PCH_IBX(dev_priv))
0571             intel_encoder->enable = ibx_enable_hdmi;
0572         else
0573             intel_encoder->enable = g4x_enable_hdmi;
0574     }
0575     intel_encoder->shutdown = intel_hdmi_encoder_shutdown;
0576 
0577     intel_encoder->type = INTEL_OUTPUT_HDMI;
0578     intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
0579     intel_encoder->port = port;
0580     if (IS_CHERRYVIEW(dev_priv)) {
0581         if (port == PORT_D)
0582             intel_encoder->pipe_mask = BIT(PIPE_C);
0583         else
0584             intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
0585     } else {
0586         intel_encoder->pipe_mask = ~0;
0587     }
0588     intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
0589     intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
0590     /*
0591      * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
0592      * to work on real hardware. And since g4x can send infoframes to
0593      * only one port anyway, nothing is lost by allowing it.
0594      */
0595     if (IS_G4X(dev_priv))
0596         intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
0597 
0598     dig_port->hdmi.hdmi_reg = hdmi_reg;
0599     dig_port->dp.output_reg = INVALID_MMIO_REG;
0600     dig_port->max_lanes = 4;
0601 
0602     intel_infoframe_init(dig_port);
0603 
0604     dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
0605     intel_hdmi_init_connector(dig_port, intel_connector);
0606 }
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