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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2020 Intel Corporation
0004  *
0005  * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
0006  */
0007 
0008 #include <linux/string_helpers.h>
0009 
0010 #include "g4x_dp.h"
0011 #include "intel_audio.h"
0012 #include "intel_backlight.h"
0013 #include "intel_connector.h"
0014 #include "intel_crtc.h"
0015 #include "intel_de.h"
0016 #include "intel_display_power.h"
0017 #include "intel_display_types.h"
0018 #include "intel_dp.h"
0019 #include "intel_dp_link_training.h"
0020 #include "intel_dpio_phy.h"
0021 #include "intel_fifo_underrun.h"
0022 #include "intel_hdmi.h"
0023 #include "intel_hotplug.h"
0024 #include "intel_pch_display.h"
0025 #include "intel_pps.h"
0026 #include "vlv_sideband.h"
0027 
0028 static const struct dpll g4x_dpll[] = {
0029     { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
0030     { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
0031 };
0032 
0033 static const struct dpll pch_dpll[] = {
0034     { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
0035     { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
0036 };
0037 
0038 static const struct dpll vlv_dpll[] = {
0039     { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
0040     { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
0041 };
0042 
0043 static const struct dpll chv_dpll[] = {
0044     /* m2 is .22 binary fixed point  */
0045     { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
0046     { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
0047 };
0048 
0049 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
0050 {
0051     return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
0052 }
0053 
0054 void g4x_dp_set_clock(struct intel_encoder *encoder,
0055               struct intel_crtc_state *pipe_config)
0056 {
0057     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0058     const struct dpll *divisor = NULL;
0059     int i, count = 0;
0060 
0061     if (IS_G4X(dev_priv)) {
0062         divisor = g4x_dpll;
0063         count = ARRAY_SIZE(g4x_dpll);
0064     } else if (HAS_PCH_SPLIT(dev_priv)) {
0065         divisor = pch_dpll;
0066         count = ARRAY_SIZE(pch_dpll);
0067     } else if (IS_CHERRYVIEW(dev_priv)) {
0068         divisor = chv_dpll;
0069         count = ARRAY_SIZE(chv_dpll);
0070     } else if (IS_VALLEYVIEW(dev_priv)) {
0071         divisor = vlv_dpll;
0072         count = ARRAY_SIZE(vlv_dpll);
0073     }
0074 
0075     if (divisor && count) {
0076         for (i = 0; i < count; i++) {
0077             if (pipe_config->port_clock == divisor[i].dot) {
0078                 pipe_config->dpll = divisor[i];
0079                 pipe_config->clock_set = true;
0080                 break;
0081             }
0082         }
0083     }
0084 }
0085 
0086 static void intel_dp_prepare(struct intel_encoder *encoder,
0087                  const struct intel_crtc_state *pipe_config)
0088 {
0089     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0090     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0091     enum port port = encoder->port;
0092     struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
0093     const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
0094 
0095     intel_dp_set_link_params(intel_dp,
0096                  pipe_config->port_clock,
0097                  pipe_config->lane_count);
0098 
0099     /*
0100      * There are four kinds of DP registers:
0101      * IBX PCH
0102      * SNB CPU
0103      * IVB CPU
0104      * CPT PCH
0105      *
0106      * IBX PCH and CPU are the same for almost everything,
0107      * except that the CPU DP PLL is configured in this
0108      * register
0109      *
0110      * CPT PCH is quite different, having many bits moved
0111      * to the TRANS_DP_CTL register instead. That
0112      * configuration happens (oddly) in ilk_pch_enable
0113      */
0114 
0115     /* Preserve the BIOS-computed detected bit. This is
0116      * supposed to be read-only.
0117      */
0118     intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
0119 
0120     /* Handle DP bits in common between all three register formats */
0121     intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
0122     intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
0123 
0124     /* Split out the IBX/CPU vs CPT settings */
0125 
0126     if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
0127         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
0128             intel_dp->DP |= DP_SYNC_HS_HIGH;
0129         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
0130             intel_dp->DP |= DP_SYNC_VS_HIGH;
0131         intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
0132 
0133         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
0134             intel_dp->DP |= DP_ENHANCED_FRAMING;
0135 
0136         intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
0137     } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
0138         u32 trans_dp;
0139 
0140         intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
0141 
0142         trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
0143         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
0144             trans_dp |= TRANS_DP_ENH_FRAMING;
0145         else
0146             trans_dp &= ~TRANS_DP_ENH_FRAMING;
0147         intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
0148     } else {
0149         if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
0150             intel_dp->DP |= DP_COLOR_RANGE_16_235;
0151 
0152         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
0153             intel_dp->DP |= DP_SYNC_HS_HIGH;
0154         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
0155             intel_dp->DP |= DP_SYNC_VS_HIGH;
0156         intel_dp->DP |= DP_LINK_TRAIN_OFF;
0157 
0158         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
0159             intel_dp->DP |= DP_ENHANCED_FRAMING;
0160 
0161         if (IS_CHERRYVIEW(dev_priv))
0162             intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
0163         else
0164             intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
0165     }
0166 }
0167 
0168 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
0169 {
0170     struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
0171     struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
0172     bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
0173 
0174     I915_STATE_WARN(cur_state != state,
0175             "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
0176             dig_port->base.base.base.id, dig_port->base.base.name,
0177             str_on_off(state), str_on_off(cur_state));
0178 }
0179 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
0180 
0181 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
0182 {
0183     bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
0184 
0185     I915_STATE_WARN(cur_state != state,
0186             "eDP PLL state assertion failure (expected %s, current %s)\n",
0187             str_on_off(state), str_on_off(cur_state));
0188 }
0189 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
0190 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
0191 
0192 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
0193                const struct intel_crtc_state *pipe_config)
0194 {
0195     struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
0196     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0197 
0198     assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
0199     assert_dp_port_disabled(intel_dp);
0200     assert_edp_pll_disabled(dev_priv);
0201 
0202     drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
0203             pipe_config->port_clock);
0204 
0205     intel_dp->DP &= ~DP_PLL_FREQ_MASK;
0206 
0207     if (pipe_config->port_clock == 162000)
0208         intel_dp->DP |= DP_PLL_FREQ_162MHZ;
0209     else
0210         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
0211 
0212     intel_de_write(dev_priv, DP_A, intel_dp->DP);
0213     intel_de_posting_read(dev_priv, DP_A);
0214     udelay(500);
0215 
0216     /*
0217      * [DevILK] Work around required when enabling DP PLL
0218      * while a pipe is enabled going to FDI:
0219      * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
0220      * 2. Program DP PLL enable
0221      */
0222     if (IS_IRONLAKE(dev_priv))
0223         intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
0224 
0225     intel_dp->DP |= DP_PLL_ENABLE;
0226 
0227     intel_de_write(dev_priv, DP_A, intel_dp->DP);
0228     intel_de_posting_read(dev_priv, DP_A);
0229     udelay(200);
0230 }
0231 
0232 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
0233                 const struct intel_crtc_state *old_crtc_state)
0234 {
0235     struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
0236     struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
0237 
0238     assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
0239     assert_dp_port_disabled(intel_dp);
0240     assert_edp_pll_enabled(dev_priv);
0241 
0242     drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
0243 
0244     intel_dp->DP &= ~DP_PLL_ENABLE;
0245 
0246     intel_de_write(dev_priv, DP_A, intel_dp->DP);
0247     intel_de_posting_read(dev_priv, DP_A);
0248     udelay(200);
0249 }
0250 
0251 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
0252                  enum port port, enum pipe *pipe)
0253 {
0254     enum pipe p;
0255 
0256     for_each_pipe(dev_priv, p) {
0257         u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
0258 
0259         if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
0260             *pipe = p;
0261             return true;
0262         }
0263     }
0264 
0265     drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
0266             port_name(port));
0267 
0268     /* must initialize pipe to something for the asserts */
0269     *pipe = PIPE_A;
0270 
0271     return false;
0272 }
0273 
0274 bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
0275              i915_reg_t dp_reg, enum port port,
0276              enum pipe *pipe)
0277 {
0278     bool ret;
0279     u32 val;
0280 
0281     val = intel_de_read(dev_priv, dp_reg);
0282 
0283     ret = val & DP_PORT_EN;
0284 
0285     /* asserts want to know the pipe even if the port is disabled */
0286     if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
0287         *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
0288     else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
0289         ret &= cpt_dp_port_selected(dev_priv, port, pipe);
0290     else if (IS_CHERRYVIEW(dev_priv))
0291         *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
0292     else
0293         *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
0294 
0295     return ret;
0296 }
0297 
0298 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
0299                   enum pipe *pipe)
0300 {
0301     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0302     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0303     intel_wakeref_t wakeref;
0304     bool ret;
0305 
0306     wakeref = intel_display_power_get_if_enabled(dev_priv,
0307                              encoder->power_domain);
0308     if (!wakeref)
0309         return false;
0310 
0311     ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
0312                   encoder->port, pipe);
0313 
0314     intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
0315 
0316     return ret;
0317 }
0318 
0319 static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
0320 {
0321     struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
0322 
0323     if (crtc_state->has_pch_encoder) {
0324         intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);
0325         intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);
0326     } else {
0327         intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
0328                            &crtc_state->dp_m_n);
0329         intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,
0330                            &crtc_state->dp_m2_n2);
0331     }
0332 }
0333 
0334 static void intel_dp_get_config(struct intel_encoder *encoder,
0335                 struct intel_crtc_state *pipe_config)
0336 {
0337     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0338     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0339     u32 tmp, flags = 0;
0340     enum port port = encoder->port;
0341     struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
0342 
0343     if (encoder->type == INTEL_OUTPUT_EDP)
0344         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
0345     else
0346         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
0347 
0348     tmp = intel_de_read(dev_priv, intel_dp->output_reg);
0349 
0350     pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
0351 
0352     if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
0353         u32 trans_dp = intel_de_read(dev_priv,
0354                          TRANS_DP_CTL(crtc->pipe));
0355 
0356         if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
0357             flags |= DRM_MODE_FLAG_PHSYNC;
0358         else
0359             flags |= DRM_MODE_FLAG_NHSYNC;
0360 
0361         if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
0362             flags |= DRM_MODE_FLAG_PVSYNC;
0363         else
0364             flags |= DRM_MODE_FLAG_NVSYNC;
0365     } else {
0366         if (tmp & DP_SYNC_HS_HIGH)
0367             flags |= DRM_MODE_FLAG_PHSYNC;
0368         else
0369             flags |= DRM_MODE_FLAG_NHSYNC;
0370 
0371         if (tmp & DP_SYNC_VS_HIGH)
0372             flags |= DRM_MODE_FLAG_PVSYNC;
0373         else
0374             flags |= DRM_MODE_FLAG_NVSYNC;
0375     }
0376 
0377     pipe_config->hw.adjusted_mode.flags |= flags;
0378 
0379     if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
0380         pipe_config->limited_color_range = true;
0381 
0382     pipe_config->lane_count =
0383         ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
0384 
0385     g4x_dp_get_m_n(pipe_config);
0386 
0387     if (port == PORT_A) {
0388         if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
0389             pipe_config->port_clock = 162000;
0390         else
0391             pipe_config->port_clock = 270000;
0392     }
0393 
0394     pipe_config->hw.adjusted_mode.crtc_clock =
0395         intel_dotclock_calculate(pipe_config->port_clock,
0396                      &pipe_config->dp_m_n);
0397 
0398     if (intel_dp_is_edp(intel_dp))
0399         intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
0400 }
0401 
0402 static void
0403 intel_dp_link_down(struct intel_encoder *encoder,
0404            const struct intel_crtc_state *old_crtc_state)
0405 {
0406     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0407     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0408     struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
0409     enum port port = encoder->port;
0410 
0411     if (drm_WARN_ON(&dev_priv->drm,
0412             (intel_de_read(dev_priv, intel_dp->output_reg) &
0413              DP_PORT_EN) == 0))
0414         return;
0415 
0416     drm_dbg_kms(&dev_priv->drm, "\n");
0417 
0418     if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
0419         (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
0420         intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
0421         intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
0422     } else {
0423         intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
0424         intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
0425     }
0426     intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
0427     intel_de_posting_read(dev_priv, intel_dp->output_reg);
0428 
0429     intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
0430     intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
0431     intel_de_posting_read(dev_priv, intel_dp->output_reg);
0432 
0433     /*
0434      * HW workaround for IBX, we need to move the port
0435      * to transcoder A after disabling it to allow the
0436      * matching HDMI port to be enabled on transcoder A.
0437      */
0438     if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
0439         /*
0440          * We get CPU/PCH FIFO underruns on the other pipe when
0441          * doing the workaround. Sweep them under the rug.
0442          */
0443         intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
0444         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
0445 
0446         /* always enable with pattern 1 (as per spec) */
0447         intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
0448         intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
0449             DP_LINK_TRAIN_PAT_1;
0450         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
0451         intel_de_posting_read(dev_priv, intel_dp->output_reg);
0452 
0453         intel_dp->DP &= ~DP_PORT_EN;
0454         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
0455         intel_de_posting_read(dev_priv, intel_dp->output_reg);
0456 
0457         intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0458         intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
0459         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
0460     }
0461 
0462     msleep(intel_dp->pps.panel_power_down_delay);
0463 
0464     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
0465         intel_wakeref_t wakeref;
0466 
0467         with_intel_pps_lock(intel_dp, wakeref)
0468             intel_dp->pps.active_pipe = INVALID_PIPE;
0469     }
0470 }
0471 
0472 static void intel_disable_dp(struct intel_atomic_state *state,
0473                  struct intel_encoder *encoder,
0474                  const struct intel_crtc_state *old_crtc_state,
0475                  const struct drm_connector_state *old_conn_state)
0476 {
0477     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0478 
0479     intel_dp->link_trained = false;
0480 
0481     intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
0482 
0483     /*
0484      * Make sure the panel is off before trying to change the mode.
0485      * But also ensure that we have vdd while we switch off the panel.
0486      */
0487     intel_pps_vdd_on(intel_dp);
0488     intel_edp_backlight_off(old_conn_state);
0489     intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
0490     intel_pps_off(intel_dp);
0491 }
0492 
0493 static void g4x_disable_dp(struct intel_atomic_state *state,
0494                struct intel_encoder *encoder,
0495                const struct intel_crtc_state *old_crtc_state,
0496                const struct drm_connector_state *old_conn_state)
0497 {
0498     intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
0499 }
0500 
0501 static void vlv_disable_dp(struct intel_atomic_state *state,
0502                struct intel_encoder *encoder,
0503                const struct intel_crtc_state *old_crtc_state,
0504                const struct drm_connector_state *old_conn_state)
0505 {
0506     intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
0507 }
0508 
0509 static void g4x_post_disable_dp(struct intel_atomic_state *state,
0510                 struct intel_encoder *encoder,
0511                 const struct intel_crtc_state *old_crtc_state,
0512                 const struct drm_connector_state *old_conn_state)
0513 {
0514     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0515     enum port port = encoder->port;
0516 
0517     /*
0518      * Bspec does not list a specific disable sequence for g4x DP.
0519      * Follow the ilk+ sequence (disable pipe before the port) for
0520      * g4x DP as it does not suffer from underruns like the normal
0521      * g4x modeset sequence (disable pipe after the port).
0522      */
0523     intel_dp_link_down(encoder, old_crtc_state);
0524 
0525     /* Only ilk+ has port A */
0526     if (port == PORT_A)
0527         ilk_edp_pll_off(intel_dp, old_crtc_state);
0528 }
0529 
0530 static void vlv_post_disable_dp(struct intel_atomic_state *state,
0531                 struct intel_encoder *encoder,
0532                 const struct intel_crtc_state *old_crtc_state,
0533                 const struct drm_connector_state *old_conn_state)
0534 {
0535     intel_dp_link_down(encoder, old_crtc_state);
0536 }
0537 
0538 static void chv_post_disable_dp(struct intel_atomic_state *state,
0539                 struct intel_encoder *encoder,
0540                 const struct intel_crtc_state *old_crtc_state,
0541                 const struct drm_connector_state *old_conn_state)
0542 {
0543     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0544 
0545     intel_dp_link_down(encoder, old_crtc_state);
0546 
0547     vlv_dpio_get(dev_priv);
0548 
0549     /* Assert data lane reset */
0550     chv_data_lane_soft_reset(encoder, old_crtc_state, true);
0551 
0552     vlv_dpio_put(dev_priv);
0553 }
0554 
0555 static void
0556 cpt_set_link_train(struct intel_dp *intel_dp,
0557            const struct intel_crtc_state *crtc_state,
0558            u8 dp_train_pat)
0559 {
0560     struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
0561 
0562     intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
0563 
0564     switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
0565     case DP_TRAINING_PATTERN_DISABLE:
0566         intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
0567         break;
0568     case DP_TRAINING_PATTERN_1:
0569         intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;
0570         break;
0571     case DP_TRAINING_PATTERN_2:
0572         intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;
0573         break;
0574     default:
0575         MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
0576         return;
0577     }
0578 
0579     intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
0580     intel_de_posting_read(dev_priv, intel_dp->output_reg);
0581 }
0582 
0583 static void
0584 g4x_set_link_train(struct intel_dp *intel_dp,
0585            const struct intel_crtc_state *crtc_state,
0586            u8 dp_train_pat)
0587 {
0588     struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
0589 
0590     intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
0591 
0592     switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
0593     case DP_TRAINING_PATTERN_DISABLE:
0594         intel_dp->DP |= DP_LINK_TRAIN_OFF;
0595         break;
0596     case DP_TRAINING_PATTERN_1:
0597         intel_dp->DP |= DP_LINK_TRAIN_PAT_1;
0598         break;
0599     case DP_TRAINING_PATTERN_2:
0600         intel_dp->DP |= DP_LINK_TRAIN_PAT_2;
0601         break;
0602     default:
0603         MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
0604         return;
0605     }
0606 
0607     intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
0608     intel_de_posting_read(dev_priv, intel_dp->output_reg);
0609 }
0610 
0611 static void intel_dp_enable_port(struct intel_dp *intel_dp,
0612                  const struct intel_crtc_state *crtc_state)
0613 {
0614     struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
0615 
0616     /* enable with pattern 1 (as per spec) */
0617 
0618     intel_dp_program_link_training_pattern(intel_dp, crtc_state,
0619                            DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
0620 
0621     /*
0622      * Magic for VLV/CHV. We _must_ first set up the register
0623      * without actually enabling the port, and then do another
0624      * write to enable the port. Otherwise link training will
0625      * fail when the power sequencer is freshly used for this port.
0626      */
0627     intel_dp->DP |= DP_PORT_EN;
0628     if (crtc_state->has_audio)
0629         intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
0630 
0631     intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
0632     intel_de_posting_read(dev_priv, intel_dp->output_reg);
0633 }
0634 
0635 static void intel_enable_dp(struct intel_atomic_state *state,
0636                 struct intel_encoder *encoder,
0637                 const struct intel_crtc_state *pipe_config,
0638                 const struct drm_connector_state *conn_state)
0639 {
0640     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0641     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0642     u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
0643     intel_wakeref_t wakeref;
0644 
0645     if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
0646         return;
0647 
0648     with_intel_pps_lock(intel_dp, wakeref) {
0649         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0650             vlv_pps_init(encoder, pipe_config);
0651 
0652         intel_dp_enable_port(intel_dp, pipe_config);
0653 
0654         intel_pps_vdd_on_unlocked(intel_dp);
0655         intel_pps_on_unlocked(intel_dp);
0656         intel_pps_vdd_off_unlocked(intel_dp, true);
0657     }
0658 
0659     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
0660         unsigned int lane_mask = 0x0;
0661 
0662         if (IS_CHERRYVIEW(dev_priv))
0663             lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
0664 
0665         vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
0666                     lane_mask);
0667     }
0668 
0669     intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
0670     intel_dp_configure_protocol_converter(intel_dp, pipe_config);
0671     intel_dp_check_frl_training(intel_dp);
0672     intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
0673     intel_dp_start_link_train(intel_dp, pipe_config);
0674     intel_dp_stop_link_train(intel_dp, pipe_config);
0675 
0676     intel_audio_codec_enable(encoder, pipe_config, conn_state);
0677 }
0678 
0679 static void g4x_enable_dp(struct intel_atomic_state *state,
0680               struct intel_encoder *encoder,
0681               const struct intel_crtc_state *pipe_config,
0682               const struct drm_connector_state *conn_state)
0683 {
0684     intel_enable_dp(state, encoder, pipe_config, conn_state);
0685     intel_edp_backlight_on(pipe_config, conn_state);
0686 }
0687 
0688 static void vlv_enable_dp(struct intel_atomic_state *state,
0689               struct intel_encoder *encoder,
0690               const struct intel_crtc_state *pipe_config,
0691               const struct drm_connector_state *conn_state)
0692 {
0693     intel_edp_backlight_on(pipe_config, conn_state);
0694 }
0695 
0696 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
0697                   struct intel_encoder *encoder,
0698                   const struct intel_crtc_state *pipe_config,
0699                   const struct drm_connector_state *conn_state)
0700 {
0701     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0702     enum port port = encoder->port;
0703 
0704     intel_dp_prepare(encoder, pipe_config);
0705 
0706     /* Only ilk+ has port A */
0707     if (port == PORT_A)
0708         ilk_edp_pll_on(intel_dp, pipe_config);
0709 }
0710 
0711 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
0712                   struct intel_encoder *encoder,
0713                   const struct intel_crtc_state *pipe_config,
0714                   const struct drm_connector_state *conn_state)
0715 {
0716     vlv_phy_pre_encoder_enable(encoder, pipe_config);
0717 
0718     intel_enable_dp(state, encoder, pipe_config, conn_state);
0719 }
0720 
0721 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
0722                   struct intel_encoder *encoder,
0723                   const struct intel_crtc_state *pipe_config,
0724                   const struct drm_connector_state *conn_state)
0725 {
0726     intel_dp_prepare(encoder, pipe_config);
0727 
0728     vlv_phy_pre_pll_enable(encoder, pipe_config);
0729 }
0730 
0731 static void chv_pre_enable_dp(struct intel_atomic_state *state,
0732                   struct intel_encoder *encoder,
0733                   const struct intel_crtc_state *pipe_config,
0734                   const struct drm_connector_state *conn_state)
0735 {
0736     chv_phy_pre_encoder_enable(encoder, pipe_config);
0737 
0738     intel_enable_dp(state, encoder, pipe_config, conn_state);
0739 
0740     /* Second common lane will stay alive on its own now */
0741     chv_phy_release_cl2_override(encoder);
0742 }
0743 
0744 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
0745                   struct intel_encoder *encoder,
0746                   const struct intel_crtc_state *pipe_config,
0747                   const struct drm_connector_state *conn_state)
0748 {
0749     intel_dp_prepare(encoder, pipe_config);
0750 
0751     chv_phy_pre_pll_enable(encoder, pipe_config);
0752 }
0753 
0754 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
0755                     struct intel_encoder *encoder,
0756                     const struct intel_crtc_state *old_crtc_state,
0757                     const struct drm_connector_state *old_conn_state)
0758 {
0759     chv_phy_post_pll_disable(encoder, old_crtc_state);
0760 }
0761 
0762 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
0763                  const struct intel_crtc_state *crtc_state)
0764 {
0765     return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
0766 }
0767 
0768 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
0769                  const struct intel_crtc_state *crtc_state)
0770 {
0771     return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
0772 }
0773 
0774 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
0775 {
0776     return DP_TRAIN_PRE_EMPH_LEVEL_2;
0777 }
0778 
0779 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
0780 {
0781     return DP_TRAIN_PRE_EMPH_LEVEL_3;
0782 }
0783 
0784 static void vlv_set_signal_levels(struct intel_encoder *encoder,
0785                   const struct intel_crtc_state *crtc_state)
0786 {
0787     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0788     unsigned long demph_reg_value, preemph_reg_value,
0789         uniqtranscale_reg_value;
0790     u8 train_set = intel_dp->train_set[0];
0791 
0792     switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
0793     case DP_TRAIN_PRE_EMPH_LEVEL_0:
0794         preemph_reg_value = 0x0004000;
0795         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0796         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0797             demph_reg_value = 0x2B405555;
0798             uniqtranscale_reg_value = 0x552AB83A;
0799             break;
0800         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
0801             demph_reg_value = 0x2B404040;
0802             uniqtranscale_reg_value = 0x5548B83A;
0803             break;
0804         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
0805             demph_reg_value = 0x2B245555;
0806             uniqtranscale_reg_value = 0x5560B83A;
0807             break;
0808         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
0809             demph_reg_value = 0x2B405555;
0810             uniqtranscale_reg_value = 0x5598DA3A;
0811             break;
0812         default:
0813             return;
0814         }
0815         break;
0816     case DP_TRAIN_PRE_EMPH_LEVEL_1:
0817         preemph_reg_value = 0x0002000;
0818         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0819         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0820             demph_reg_value = 0x2B404040;
0821             uniqtranscale_reg_value = 0x5552B83A;
0822             break;
0823         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
0824             demph_reg_value = 0x2B404848;
0825             uniqtranscale_reg_value = 0x5580B83A;
0826             break;
0827         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
0828             demph_reg_value = 0x2B404040;
0829             uniqtranscale_reg_value = 0x55ADDA3A;
0830             break;
0831         default:
0832             return;
0833         }
0834         break;
0835     case DP_TRAIN_PRE_EMPH_LEVEL_2:
0836         preemph_reg_value = 0x0000000;
0837         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0838         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0839             demph_reg_value = 0x2B305555;
0840             uniqtranscale_reg_value = 0x5570B83A;
0841             break;
0842         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
0843             demph_reg_value = 0x2B2B4040;
0844             uniqtranscale_reg_value = 0x55ADDA3A;
0845             break;
0846         default:
0847             return;
0848         }
0849         break;
0850     case DP_TRAIN_PRE_EMPH_LEVEL_3:
0851         preemph_reg_value = 0x0006000;
0852         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0853         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0854             demph_reg_value = 0x1B405555;
0855             uniqtranscale_reg_value = 0x55ADDA3A;
0856             break;
0857         default:
0858             return;
0859         }
0860         break;
0861     default:
0862         return;
0863     }
0864 
0865     vlv_set_phy_signal_level(encoder, crtc_state,
0866                  demph_reg_value, preemph_reg_value,
0867                  uniqtranscale_reg_value, 0);
0868 }
0869 
0870 static void chv_set_signal_levels(struct intel_encoder *encoder,
0871                   const struct intel_crtc_state *crtc_state)
0872 {
0873     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0874     u32 deemph_reg_value, margin_reg_value;
0875     bool uniq_trans_scale = false;
0876     u8 train_set = intel_dp->train_set[0];
0877 
0878     switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
0879     case DP_TRAIN_PRE_EMPH_LEVEL_0:
0880         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0881         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0882             deemph_reg_value = 128;
0883             margin_reg_value = 52;
0884             break;
0885         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
0886             deemph_reg_value = 128;
0887             margin_reg_value = 77;
0888             break;
0889         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
0890             deemph_reg_value = 128;
0891             margin_reg_value = 102;
0892             break;
0893         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
0894             deemph_reg_value = 128;
0895             margin_reg_value = 154;
0896             uniq_trans_scale = true;
0897             break;
0898         default:
0899             return;
0900         }
0901         break;
0902     case DP_TRAIN_PRE_EMPH_LEVEL_1:
0903         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0904         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0905             deemph_reg_value = 85;
0906             margin_reg_value = 78;
0907             break;
0908         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
0909             deemph_reg_value = 85;
0910             margin_reg_value = 116;
0911             break;
0912         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
0913             deemph_reg_value = 85;
0914             margin_reg_value = 154;
0915             break;
0916         default:
0917             return;
0918         }
0919         break;
0920     case DP_TRAIN_PRE_EMPH_LEVEL_2:
0921         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0922         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0923             deemph_reg_value = 64;
0924             margin_reg_value = 104;
0925             break;
0926         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
0927             deemph_reg_value = 64;
0928             margin_reg_value = 154;
0929             break;
0930         default:
0931             return;
0932         }
0933         break;
0934     case DP_TRAIN_PRE_EMPH_LEVEL_3:
0935         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0936         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0937             deemph_reg_value = 43;
0938             margin_reg_value = 154;
0939             break;
0940         default:
0941             return;
0942         }
0943         break;
0944     default:
0945         return;
0946     }
0947 
0948     chv_set_phy_signal_level(encoder, crtc_state,
0949                  deemph_reg_value, margin_reg_value,
0950                  uniq_trans_scale);
0951 }
0952 
0953 static u32 g4x_signal_levels(u8 train_set)
0954 {
0955     u32 signal_levels = 0;
0956 
0957     switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
0958     case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
0959     default:
0960         signal_levels |= DP_VOLTAGE_0_4;
0961         break;
0962     case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
0963         signal_levels |= DP_VOLTAGE_0_6;
0964         break;
0965     case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
0966         signal_levels |= DP_VOLTAGE_0_8;
0967         break;
0968     case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
0969         signal_levels |= DP_VOLTAGE_1_2;
0970         break;
0971     }
0972     switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
0973     case DP_TRAIN_PRE_EMPH_LEVEL_0:
0974     default:
0975         signal_levels |= DP_PRE_EMPHASIS_0;
0976         break;
0977     case DP_TRAIN_PRE_EMPH_LEVEL_1:
0978         signal_levels |= DP_PRE_EMPHASIS_3_5;
0979         break;
0980     case DP_TRAIN_PRE_EMPH_LEVEL_2:
0981         signal_levels |= DP_PRE_EMPHASIS_6;
0982         break;
0983     case DP_TRAIN_PRE_EMPH_LEVEL_3:
0984         signal_levels |= DP_PRE_EMPHASIS_9_5;
0985         break;
0986     }
0987     return signal_levels;
0988 }
0989 
0990 static void
0991 g4x_set_signal_levels(struct intel_encoder *encoder,
0992               const struct intel_crtc_state *crtc_state)
0993 {
0994     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0995     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
0996     u8 train_set = intel_dp->train_set[0];
0997     u32 signal_levels;
0998 
0999     signal_levels = g4x_signal_levels(train_set);
1000 
1001     drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1002             signal_levels);
1003 
1004     intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
1005     intel_dp->DP |= signal_levels;
1006 
1007     intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
1008     intel_de_posting_read(dev_priv, intel_dp->output_reg);
1009 }
1010 
1011 /* SNB CPU eDP voltage swing and pre-emphasis control */
1012 static u32 snb_cpu_edp_signal_levels(u8 train_set)
1013 {
1014     u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1015                     DP_TRAIN_PRE_EMPHASIS_MASK);
1016 
1017     switch (signal_levels) {
1018     case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1019     case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1020         return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1021     case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1022         return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1023     case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1024     case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1025         return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1026     case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1027     case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1028         return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1029     case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1030     case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1031         return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1032     default:
1033         MISSING_CASE(signal_levels);
1034         return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1035     }
1036 }
1037 
1038 static void
1039 snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1040                   const struct intel_crtc_state *crtc_state)
1041 {
1042     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1043     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1044     u8 train_set = intel_dp->train_set[0];
1045     u32 signal_levels;
1046 
1047     signal_levels = snb_cpu_edp_signal_levels(train_set);
1048 
1049     drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1050             signal_levels);
1051 
1052     intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1053     intel_dp->DP |= signal_levels;
1054 
1055     intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
1056     intel_de_posting_read(dev_priv, intel_dp->output_reg);
1057 }
1058 
1059 /* IVB CPU eDP voltage swing and pre-emphasis control */
1060 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
1061 {
1062     u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1063                     DP_TRAIN_PRE_EMPHASIS_MASK);
1064 
1065     switch (signal_levels) {
1066     case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1067         return EDP_LINK_TRAIN_400MV_0DB_IVB;
1068     case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1069         return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1070     case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1071     case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1072         return EDP_LINK_TRAIN_400MV_6DB_IVB;
1073 
1074     case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1075         return EDP_LINK_TRAIN_600MV_0DB_IVB;
1076     case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1077         return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1078 
1079     case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1080         return EDP_LINK_TRAIN_800MV_0DB_IVB;
1081     case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1082         return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1083 
1084     default:
1085         MISSING_CASE(signal_levels);
1086         return EDP_LINK_TRAIN_500MV_0DB_IVB;
1087     }
1088 }
1089 
1090 static void
1091 ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1092                   const struct intel_crtc_state *crtc_state)
1093 {
1094     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1095     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1096     u8 train_set = intel_dp->train_set[0];
1097     u32 signal_levels;
1098 
1099     signal_levels = ivb_cpu_edp_signal_levels(train_set);
1100 
1101     drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1102             signal_levels);
1103 
1104     intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1105     intel_dp->DP |= signal_levels;
1106 
1107     intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
1108     intel_de_posting_read(dev_priv, intel_dp->output_reg);
1109 }
1110 
1111 /*
1112  * If display is now connected check links status,
1113  * there has been known issues of link loss triggering
1114  * long pulse.
1115  *
1116  * Some sinks (eg. ASUS PB287Q) seem to perform some
1117  * weird HPD ping pong during modesets. So we can apparently
1118  * end up with HPD going low during a modeset, and then
1119  * going back up soon after. And once that happens we must
1120  * retrain the link to get a picture. That's in case no
1121  * userspace component reacted to intermittent HPD dip.
1122  */
1123 static enum intel_hotplug_state
1124 intel_dp_hotplug(struct intel_encoder *encoder,
1125          struct intel_connector *connector)
1126 {
1127     struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1128     struct drm_modeset_acquire_ctx ctx;
1129     enum intel_hotplug_state state;
1130     int ret;
1131 
1132     if (intel_dp->compliance.test_active &&
1133         intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
1134         intel_dp_phy_test(encoder);
1135         /* just do the PHY test and nothing else */
1136         return INTEL_HOTPLUG_UNCHANGED;
1137     }
1138 
1139     state = intel_encoder_hotplug(encoder, connector);
1140 
1141     drm_modeset_acquire_init(&ctx, 0);
1142 
1143     for (;;) {
1144         ret = intel_dp_retrain_link(encoder, &ctx);
1145 
1146         if (ret == -EDEADLK) {
1147             drm_modeset_backoff(&ctx);
1148             continue;
1149         }
1150 
1151         break;
1152     }
1153 
1154     drm_modeset_drop_locks(&ctx);
1155     drm_modeset_acquire_fini(&ctx);
1156     drm_WARN(encoder->base.dev, ret,
1157          "Acquiring modeset locks failed with %i\n", ret);
1158 
1159     /*
1160      * Keeping it consistent with intel_ddi_hotplug() and
1161      * intel_hdmi_hotplug().
1162      */
1163     if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
1164         state = INTEL_HOTPLUG_RETRY;
1165 
1166     return state;
1167 }
1168 
1169 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
1170 {
1171     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1172     u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
1173 
1174     return intel_de_read(dev_priv, SDEISR) & bit;
1175 }
1176 
1177 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
1178 {
1179     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1180     u32 bit;
1181 
1182     switch (encoder->hpd_pin) {
1183     case HPD_PORT_B:
1184         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
1185         break;
1186     case HPD_PORT_C:
1187         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
1188         break;
1189     case HPD_PORT_D:
1190         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
1191         break;
1192     default:
1193         MISSING_CASE(encoder->hpd_pin);
1194         return false;
1195     }
1196 
1197     return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
1198 }
1199 
1200 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
1201 {
1202     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1203     u32 bit;
1204 
1205     switch (encoder->hpd_pin) {
1206     case HPD_PORT_B:
1207         bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
1208         break;
1209     case HPD_PORT_C:
1210         bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
1211         break;
1212     case HPD_PORT_D:
1213         bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
1214         break;
1215     default:
1216         MISSING_CASE(encoder->hpd_pin);
1217         return false;
1218     }
1219 
1220     return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
1221 }
1222 
1223 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
1224 {
1225     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1226     u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
1227 
1228     return intel_de_read(dev_priv, DEISR) & bit;
1229 }
1230 
1231 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1232 {
1233     intel_dp_encoder_flush_work(encoder);
1234 
1235     drm_encoder_cleanup(encoder);
1236     kfree(enc_to_dig_port(to_intel_encoder(encoder)));
1237 }
1238 
1239 enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
1240 {
1241     struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1242     struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1243     enum pipe pipe;
1244 
1245     if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
1246                 encoder->port, &pipe))
1247         return pipe;
1248 
1249     return INVALID_PIPE;
1250 }
1251 
1252 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
1253 {
1254     struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1255     struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
1256 
1257     intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
1258 
1259     intel_dp->reset_link_params = true;
1260 
1261     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1262         intel_wakeref_t wakeref;
1263 
1264         with_intel_pps_lock(intel_dp, wakeref)
1265             intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
1266     }
1267 
1268     intel_pps_encoder_reset(intel_dp);
1269 }
1270 
1271 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1272     .reset = intel_dp_encoder_reset,
1273     .destroy = intel_dp_encoder_destroy,
1274 };
1275 
1276 bool g4x_dp_init(struct drm_i915_private *dev_priv,
1277          i915_reg_t output_reg, enum port port)
1278 {
1279     struct intel_digital_port *dig_port;
1280     struct intel_encoder *intel_encoder;
1281     struct drm_encoder *encoder;
1282     struct intel_connector *intel_connector;
1283 
1284     dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
1285     if (!dig_port)
1286         return false;
1287 
1288     intel_connector = intel_connector_alloc();
1289     if (!intel_connector)
1290         goto err_connector_alloc;
1291 
1292     intel_encoder = &dig_port->base;
1293     encoder = &intel_encoder->base;
1294 
1295     mutex_init(&dig_port->hdcp_mutex);
1296 
1297     if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
1298                  &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
1299                  "DP %c", port_name(port)))
1300         goto err_encoder_init;
1301 
1302     intel_encoder->hotplug = intel_dp_hotplug;
1303     intel_encoder->compute_config = intel_dp_compute_config;
1304     intel_encoder->get_hw_state = intel_dp_get_hw_state;
1305     intel_encoder->get_config = intel_dp_get_config;
1306     intel_encoder->sync_state = intel_dp_sync_state;
1307     intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
1308     intel_encoder->update_pipe = intel_backlight_update;
1309     intel_encoder->suspend = intel_dp_encoder_suspend;
1310     intel_encoder->shutdown = intel_dp_encoder_shutdown;
1311     if (IS_CHERRYVIEW(dev_priv)) {
1312         intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
1313         intel_encoder->pre_enable = chv_pre_enable_dp;
1314         intel_encoder->enable = vlv_enable_dp;
1315         intel_encoder->disable = vlv_disable_dp;
1316         intel_encoder->post_disable = chv_post_disable_dp;
1317         intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
1318     } else if (IS_VALLEYVIEW(dev_priv)) {
1319         intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
1320         intel_encoder->pre_enable = vlv_pre_enable_dp;
1321         intel_encoder->enable = vlv_enable_dp;
1322         intel_encoder->disable = vlv_disable_dp;
1323         intel_encoder->post_disable = vlv_post_disable_dp;
1324     } else {
1325         intel_encoder->pre_enable = g4x_pre_enable_dp;
1326         intel_encoder->enable = g4x_enable_dp;
1327         intel_encoder->disable = g4x_disable_dp;
1328         intel_encoder->post_disable = g4x_post_disable_dp;
1329     }
1330 
1331     if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
1332         (HAS_PCH_CPT(dev_priv) && port != PORT_A))
1333         dig_port->dp.set_link_train = cpt_set_link_train;
1334     else
1335         dig_port->dp.set_link_train = g4x_set_link_train;
1336 
1337     if (IS_CHERRYVIEW(dev_priv))
1338         intel_encoder->set_signal_levels = chv_set_signal_levels;
1339     else if (IS_VALLEYVIEW(dev_priv))
1340         intel_encoder->set_signal_levels = vlv_set_signal_levels;
1341     else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
1342         intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;
1343     else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
1344         intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;
1345     else
1346         intel_encoder->set_signal_levels = g4x_set_signal_levels;
1347 
1348     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
1349         (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
1350         dig_port->dp.preemph_max = intel_dp_preemph_max_3;
1351         dig_port->dp.voltage_max = intel_dp_voltage_max_3;
1352     } else {
1353         dig_port->dp.preemph_max = intel_dp_preemph_max_2;
1354         dig_port->dp.voltage_max = intel_dp_voltage_max_2;
1355     }
1356 
1357     dig_port->dp.output_reg = output_reg;
1358     dig_port->max_lanes = 4;
1359 
1360     intel_encoder->type = INTEL_OUTPUT_DP;
1361     intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
1362     if (IS_CHERRYVIEW(dev_priv)) {
1363         if (port == PORT_D)
1364             intel_encoder->pipe_mask = BIT(PIPE_C);
1365         else
1366             intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
1367     } else {
1368         intel_encoder->pipe_mask = ~0;
1369     }
1370     intel_encoder->cloneable = 0;
1371     intel_encoder->port = port;
1372     intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
1373 
1374     dig_port->hpd_pulse = intel_dp_hpd_pulse;
1375 
1376     if (HAS_GMCH(dev_priv)) {
1377         if (IS_GM45(dev_priv))
1378             dig_port->connected = gm45_digital_port_connected;
1379         else
1380             dig_port->connected = g4x_digital_port_connected;
1381     } else {
1382         if (port == PORT_A)
1383             dig_port->connected = ilk_digital_port_connected;
1384         else
1385             dig_port->connected = ibx_digital_port_connected;
1386     }
1387 
1388     if (port != PORT_A)
1389         intel_infoframe_init(dig_port);
1390 
1391     dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
1392     if (!intel_dp_init_connector(dig_port, intel_connector))
1393         goto err_init_connector;
1394 
1395     return true;
1396 
1397 err_init_connector:
1398     drm_encoder_cleanup(encoder);
1399 err_encoder_init:
1400     kfree(intel_connector);
1401 err_connector_alloc:
1402     kfree(dig_port);
1403     return false;
1404 }
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