drm/i810/i810_drv.h

0001 /* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
0002  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
0003  *
0004  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
0005  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
0006  * All rights reserved.
0007  *
0008  * Permission is hereby granted, free of charge, to any person obtaining a
0009  * copy of this software and associated documentation files (the "Software"),
0010  * to deal in the Software without restriction, including without limitation
0011  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0012  * and/or sell copies of the Software, and to permit persons to whom the
0013  * Software is furnished to do so, subject to the following conditions:
0014  *
0015  * The above copyright notice and this permission notice (including the next
0016  * paragraph) shall be included in all copies or substantial portions of the
0017  * Software.
0018  *
0019  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0020  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0021  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0022  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0023  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0024  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0025  * DEALINGS IN THE SOFTWARE.
0026  *
0027  * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
0028  *      Jeff Hartmann <jhartmann@valinux.com>
0029  *
0030  */
0031
0032 #ifndef _I810_DRV_H_
0033 #define _I810_DRV_H_
0034
0035 #include <drm/drm_ioctl.h>
0036 #include <drm/drm_legacy.h>
0037 #include <drm/i810_drm.h>
0038
0039 /* General customization:
0040  */
0041
0042 #define DRIVER_AUTHOR       "VA Linux Systems Inc."
0043
0044 #define DRIVER_NAME     "i810"
0045 #define DRIVER_DESC     "Intel i810"
0046 #define DRIVER_DATE     "20030605"
0047
0048 /* Interface history
0049  *
0050  * 1.1   - XFree86 4.1
0051  * 1.2   - XvMC interfaces
0052  *       - XFree86 4.2
0053  * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
0054  *       - Remove requirement for interrupt (leave stubs again)
0055  * 1.3   - Add page flipping.
0056  * 1.4   - fix DRM interface
0057  */
0058 #define DRIVER_MAJOR        1
0059 #define DRIVER_MINOR        4
0060 #define DRIVER_PATCHLEVEL   0
0061
0062 typedef struct drm_i810_buf_priv {
0063     u32 *in_use;
0064     int my_use_idx;
0065     int currently_mapped;
0066     void *virtual;
0067     void *kernel_virtual;
0068     drm_local_map_t map;
0069 } drm_i810_buf_priv_t;
0070
0071 typedef struct _drm_i810_ring_buffer {
0072     int tail_mask;
0073     unsigned long Start;
0074     unsigned long End;
0075     unsigned long Size;
0076     u8 *virtual_start;
0077     int head;
0078     int tail;
0079     int space;
0080     drm_local_map_t map;
0081 } drm_i810_ring_buffer_t;
0082
0083 typedef struct drm_i810_private {
0084     struct drm_local_map *sarea_map;
0085     struct drm_local_map *mmio_map;
0086
0087     drm_i810_sarea_t *sarea_priv;
0088     drm_i810_ring_buffer_t ring;
0089
0090     void *hw_status_page;
0091     unsigned long counter;
0092
0093     dma_addr_t dma_status_page;
0094
0095     struct drm_buf *mmap_buffer;
0096
0097     u32 front_di1, back_di1, zi1;
0098
0099     int back_offset;
0100     int depth_offset;
0101     int overlay_offset;
0102     int overlay_physical;
0103     int w, h;
0104     int pitch;
0105     int back_pitch;
0106     int depth_pitch;
0107
0108     int do_boxes;
0109     int dma_used;
0110
0111     int current_page;
0112     int page_flipping;
0113
0114     wait_queue_head_t irq_queue;
0115     atomic_t irq_received;
0116     atomic_t irq_emitted;
0117
0118     int front_offset;
0119 } drm_i810_private_t;
0120
0121                 /* i810_dma.c */
0122 extern int i810_driver_dma_quiescent(struct drm_device *dev);
0123 void i810_driver_reclaim_buffers(struct drm_device *dev,
0124                      struct drm_file *file_priv);
0125 extern int i810_driver_load(struct drm_device *, unsigned long flags);
0126 extern void i810_driver_lastclose(struct drm_device *dev);
0127 extern void i810_driver_preclose(struct drm_device *dev,
0128                  struct drm_file *file_priv);
0129
0130 extern long i810_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
0131 extern const struct drm_ioctl_desc i810_ioctls[];
0132 extern int i810_max_ioctl;
0133
0134 #define I810_BASE(reg)      ((unsigned long) \
0135                 dev_priv->mmio_map->handle)
0136 #define I810_ADDR(reg)      (I810_BASE(reg) + reg)
0137 #define I810_DEREF(reg)     (*(__volatile__ int *)I810_ADDR(reg))
0138 #define I810_READ(reg)      I810_DEREF(reg)
0139 #define I810_WRITE(reg, val)    do { I810_DEREF(reg) = val; } while (0)
0140 #define I810_DEREF16(reg)   (*(__volatile__ u16 *)I810_ADDR(reg))
0141 #define I810_READ16(reg)    I810_DEREF16(reg)
0142 #define I810_WRITE16(reg, val)  do { I810_DEREF16(reg) = val; } while (0)
0143
0144 #define I810_VERBOSE 0
0145 #define RING_LOCALS unsigned int outring, ringmask; \
0146             volatile char *virt;
0147
0148 #define BEGIN_LP_RING(n) do {                   \
0149     if (I810_VERBOSE)                   \
0150         DRM_DEBUG("BEGIN_LP_RING(%d)\n", n);        \
0151     if (dev_priv->ring.space < n*4)             \
0152         i810_wait_ring(dev, n*4);           \
0153     dev_priv->ring.space -= n*4;                \
0154     outring = dev_priv->ring.tail;              \
0155     ringmask = dev_priv->ring.tail_mask;            \
0156     virt = dev_priv->ring.virtual_start;            \
0157 } while (0)
0158
0159 #define ADVANCE_LP_RING() do {                  \
0160     if (I810_VERBOSE)                   \
0161         DRM_DEBUG("ADVANCE_LP_RING\n");         \
0162     dev_priv->ring.tail = outring;              \
0163     I810_WRITE(LP_RING + RING_TAIL, outring);       \
0164 } while (0)
0165
0166 #define OUT_RING(n) do {                    \
0167     if (I810_VERBOSE)                   \
0168         DRM_DEBUG("   OUT_RING %x\n", (int)(n));    \
0169     *(volatile unsigned int *)(virt + outring) = n;     \
0170     outring += 4;                       \
0171     outring &= ringmask;                    \
0172 } while (0)
0173
0174 #define GFX_OP_USER_INTERRUPT       ((0<<29)|(2<<23))
0175 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
0176 #define CMD_REPORT_HEAD         (7<<23)
0177 #define CMD_STORE_DWORD_IDX     ((0x21<<23) | 0x1)
0178 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
0179
0180 #define INST_PARSER_CLIENT   0x00000000
0181 #define INST_OP_FLUSH        0x02000000
0182 #define INST_FLUSH_MAP_CACHE 0x00000001
0183
0184 #define BB1_START_ADDR_MASK   (~0x7)
0185 #define BB1_PROTECTED         (1<<0)
0186 #define BB1_UNPROTECTED       (0<<0)
0187 #define BB2_END_ADDR_MASK     (~0x7)
0188
0189 #define I810REG_HWSTAM      0x02098
0190 #define I810REG_INT_IDENTITY_R  0x020a4
0191 #define I810REG_INT_MASK_R  0x020a8
0192 #define I810REG_INT_ENABLE_R    0x020a0
0193
0194 #define LP_RING         0x2030
0195 #define HP_RING         0x2040
0196 #define RING_TAIL       0x00
0197 #define TAIL_ADDR       0x000FFFF8
0198 #define RING_HEAD       0x04
0199 #define HEAD_WRAP_COUNT     0xFFE00000
0200 #define HEAD_WRAP_ONE       0x00200000
0201 #define HEAD_ADDR       0x001FFFFC
0202 #define RING_START      0x08
0203 #define START_ADDR      0x00FFFFF8
0204 #define RING_LEN        0x0C
0205 #define RING_NR_PAGES       0x000FF000
0206 #define RING_REPORT_MASK    0x00000006
0207 #define RING_REPORT_64K     0x00000002
0208 #define RING_REPORT_128K    0x00000004
0209 #define RING_NO_REPORT      0x00000000
0210 #define RING_VALID_MASK     0x00000001
0211 #define RING_VALID      0x00000001
0212 #define RING_INVALID        0x00000000
0213
0214 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
0215 #define SC_UPDATE_SCISSOR       (0x1<<1)
0216 #define SC_ENABLE_MASK          (0x1<<0)
0217 #define SC_ENABLE               (0x1<<0)
0218
0219 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
0220 #define SCI_YMIN_MASK      (0xffff<<16)
0221 #define SCI_XMIN_MASK      (0xffff<<0)
0222 #define SCI_YMAX_MASK      (0xffff<<16)
0223 #define SCI_XMAX_MASK      (0xffff<<0)
0224
0225 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
0226 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
0227 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x2)
0228 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
0229 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
0230 #define GFX_OP_PRIMITIVE         ((0x3<<29)|(0x1f<<24))
0231
0232 #define CMD_OP_Z_BUFFER_INFO     ((0x0<<29)|(0x16<<23))
0233 #define CMD_OP_DESTBUFFER_INFO   ((0x0<<29)|(0x15<<23))
0234 #define CMD_OP_FRONTBUFFER_INFO  ((0x0<<29)|(0x14<<23))
0235 #define CMD_OP_WAIT_FOR_EVENT    ((0x0<<29)|(0x03<<23))
0236
0237 #define BR00_BITBLT_CLIENT   0x40000000
0238 #define BR00_OP_COLOR_BLT    0x10000000
0239 #define BR00_OP_SRC_COPY_BLT 0x10C00000
0240 #define BR13_SOLID_PATTERN   0x80000000
0241
0242 #define WAIT_FOR_PLANE_A_SCANLINES (1<<1)
0243 #define WAIT_FOR_PLANE_A_FLIP      (1<<2)
0244 #define WAIT_FOR_VBLANK (1<<3)
0245
0246 #endif