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0001 /*
0002  * Copyright (C) 2009 Francisco Jerez.
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining
0006  * a copy of this software and associated documentation files (the
0007  * "Software"), to deal in the Software without restriction, including
0008  * without limitation the rights to use, copy, modify, merge, publish,
0009  * distribute, sublicense, and/or sell copies of the Software, and to
0010  * permit persons to whom the Software is furnished to do so, subject to
0011  * the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the
0014  * next paragraph) shall be included in all copies or substantial
0015  * portions of the Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0018  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
0020  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
0021  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
0022  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0023  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0024  *
0025  */
0026 
0027 #include "ch7006_priv.h"
0028 
0029 const char * const ch7006_tv_norm_names[] = {
0030     [TV_NORM_PAL] = "PAL",
0031     [TV_NORM_PAL_M] = "PAL-M",
0032     [TV_NORM_PAL_N] = "PAL-N",
0033     [TV_NORM_PAL_NC] = "PAL-Nc",
0034     [TV_NORM_PAL_60] = "PAL-60",
0035     [TV_NORM_NTSC_M] = "NTSC-M",
0036     [TV_NORM_NTSC_J] = "NTSC-J",
0037 };
0038 
0039 #define NTSC_LIKE_TIMINGS .vrefresh = 60 * fixed1/1.001,        \
0040         .vdisplay = 480,                    \
0041         .vtotal = 525,                      \
0042         .hvirtual = 660
0043 
0044 #define PAL_LIKE_TIMINGS .vrefresh = 50 * fixed1,       \
0045         .vdisplay = 576,                \
0046         .vtotal = 625,                  \
0047         .hvirtual = 810
0048 
0049 const struct ch7006_tv_norm_info ch7006_tv_norms[] = {
0050     [TV_NORM_NTSC_M] = {
0051         NTSC_LIKE_TIMINGS,
0052         .black_level = 0.339 * fixed1,
0053         .subc_freq = 3579545 * fixed1,
0054         .dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, NTSC),
0055         .voffset = 0,
0056     },
0057     [TV_NORM_NTSC_J] = {
0058         NTSC_LIKE_TIMINGS,
0059         .black_level = 0.286 * fixed1,
0060         .subc_freq = 3579545 * fixed1,
0061         .dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, NTSC_J),
0062         .voffset = 0,
0063     },
0064     [TV_NORM_PAL] = {
0065         PAL_LIKE_TIMINGS,
0066         .black_level = 0.3 * fixed1,
0067         .subc_freq = 4433618.75 * fixed1,
0068         .dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
0069         .voffset = 0,
0070     },
0071     [TV_NORM_PAL_M] = {
0072         NTSC_LIKE_TIMINGS,
0073         .black_level = 0.339 * fixed1,
0074         .subc_freq = 3575611.433 * fixed1,
0075         .dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL_M),
0076         .voffset = 16,
0077     },
0078 
0079     /* The following modes seem to work right but they're
0080      * undocumented */
0081 
0082     [TV_NORM_PAL_N] = {
0083         PAL_LIKE_TIMINGS,
0084         .black_level = 0.339 * fixed1,
0085         .subc_freq = 4433618.75 * fixed1,
0086         .dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
0087         .voffset = 0,
0088     },
0089     [TV_NORM_PAL_NC] = {
0090         PAL_LIKE_TIMINGS,
0091         .black_level = 0.3 * fixed1,
0092         .subc_freq = 3582056.25 * fixed1,
0093         .dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL),
0094         .voffset = 0,
0095     },
0096     [TV_NORM_PAL_60] = {
0097         NTSC_LIKE_TIMINGS,
0098         .black_level = 0.3 * fixed1,
0099         .subc_freq = 4433618.75 * fixed1,
0100         .dispmode = bitfs(CH7006_DISPMODE_OUTPUT_STD, PAL_M),
0101         .voffset = 16,
0102     },
0103 };
0104 
0105 #define __MODE(f, hd, vd, ht, vt, hsynp, vsynp,             \
0106            subc, scale, scale_mask, norm_mask, e_hd, e_vd) {    \
0107         .mode = {                       \
0108             .name = #hd "x" #vd,                \
0109             .status = 0,                    \
0110             .type = DRM_MODE_TYPE_DRIVER,           \
0111             .clock = f,                 \
0112             .hdisplay = hd,                 \
0113             .hsync_start = e_hd + 16,           \
0114             .hsync_end = e_hd + 80,             \
0115             .htotal = ht,                   \
0116             .hskew = 0,                 \
0117             .vdisplay = vd,                 \
0118             .vsync_start = vd + 10,             \
0119             .vsync_end = vd + 26,               \
0120             .vtotal = vt,                   \
0121             .vscan = 0,                 \
0122             .flags = DRM_MODE_FLAG_##hsynp##HSYNC |     \
0123                 DRM_MODE_FLAG_##vsynp##VSYNC,       \
0124         },                          \
0125         .enc_hdisp = e_hd,                  \
0126         .enc_vdisp = e_vd,                  \
0127         .subc_coeff = subc * fixed1,                \
0128         .dispmode = bitfs(CH7006_DISPMODE_SCALING_RATIO, scale) | \
0129                 bitfs(CH7006_DISPMODE_INPUT_RES, e_hd##x##e_vd), \
0130         .valid_scales = scale_mask,             \
0131         .valid_norms = norm_mask                \
0132      }
0133 
0134 #define MODE(f, hd, vd, ht, vt, hsynp, vsynp,               \
0135          subc, scale, scale_mask, norm_mask)            \
0136     __MODE(f, hd, vd, ht, vt, hsynp, vsynp, subc, scale,        \
0137            scale_mask, norm_mask, hd, vd)
0138 
0139 #define NTSC_LIKE (1 << TV_NORM_NTSC_M | 1 << TV_NORM_NTSC_J |      \
0140            1 << TV_NORM_PAL_M | 1 << TV_NORM_PAL_60)
0141 
0142 #define PAL_LIKE (1 << TV_NORM_PAL | 1 << TV_NORM_PAL_N | 1 << TV_NORM_PAL_NC)
0143 
0144 const struct ch7006_mode ch7006_modes[] = {
0145     MODE(21000, 512, 384, 840, 500, N, N, 181.797557582, 5_4, 0x6, PAL_LIKE),
0146     MODE(26250, 512, 384, 840, 625, N, N, 145.438046066, 1_1, 0x1, PAL_LIKE),
0147     MODE(20140, 512, 384, 800, 420, N, N, 213.257083791, 5_4, 0x4, NTSC_LIKE),
0148     MODE(24671, 512, 384, 784, 525, N, N, 174.0874153, 1_1, 0x3, NTSC_LIKE),
0149     MODE(28125, 720, 400, 1125, 500, N, N, 135.742176298, 5_4, 0x6, PAL_LIKE),
0150     MODE(34875, 720, 400, 1116, 625, N, N, 109.469496898, 1_1, 0x1, PAL_LIKE),
0151     MODE(23790, 720, 400, 945, 420, N, N, 160.475642016, 5_4, 0x4, NTSC_LIKE),
0152     MODE(29455, 720, 400, 936, 525, N, N, 129.614941843, 1_1, 0x3, NTSC_LIKE),
0153     MODE(25000, 640, 400, 1000, 500, N, N, 152.709948279, 5_4, 0x6, PAL_LIKE),
0154     MODE(31500, 640, 400, 1008, 625, N, N, 121.198371646, 1_1, 0x1, PAL_LIKE),
0155     MODE(21147, 640, 400, 840, 420, N, N, 180.535097338, 5_4, 0x4, NTSC_LIKE),
0156     MODE(26434, 640, 400, 840, 525, N, N, 144.42807787, 1_1, 0x2, NTSC_LIKE),
0157     MODE(30210, 640, 400, 840, 600, N, N, 126.374568276, 7_8, 0x1, NTSC_LIKE),
0158     MODE(21000, 640, 480, 840, 500, N, N, 181.797557582, 5_4, 0x4, PAL_LIKE),
0159     MODE(26250, 640, 480, 840, 625, N, N, 145.438046066, 1_1, 0x2, PAL_LIKE),
0160     MODE(31500, 640, 480, 840, 750, N, N, 121.198371646, 5_6, 0x1, PAL_LIKE),
0161     MODE(24671, 640, 480, 784, 525, N, N, 174.0874153, 1_1, 0x4, NTSC_LIKE),
0162     MODE(28196, 640, 480, 784, 600, N, N, 152.326488422, 7_8, 0x2, NTSC_LIKE),
0163     MODE(30210, 640, 480, 800, 630, N, N, 142.171389101, 5_6, 0x1, NTSC_LIKE),
0164     __MODE(29500, 720, 576, 944, 625, P, P, 145.592111636, 1_1, 0x7, PAL_LIKE, 800, 600),
0165     MODE(36000, 800, 600, 960, 750, P, P, 119.304647022, 5_6, 0x6, PAL_LIKE),
0166     MODE(39000, 800, 600, 936, 836, P, P, 110.127366499, 3_4, 0x1, PAL_LIKE),
0167     MODE(39273, 800, 600, 1040, 630, P, P, 145.816809399, 5_6, 0x4, NTSC_LIKE),
0168     MODE(43636, 800, 600, 1040, 700, P, P, 131.235128487, 3_4, 0x2, NTSC_LIKE),
0169     MODE(47832, 800, 600, 1064, 750, P, P, 119.723275165, 7_10, 0x1, NTSC_LIKE),
0170     {}
0171 };
0172 
0173 const struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder,
0174                          const struct drm_display_mode *drm_mode)
0175 {
0176     struct ch7006_priv *priv = to_ch7006_priv(encoder);
0177     const struct ch7006_mode *mode;
0178 
0179     for (mode = ch7006_modes; mode->mode.clock; mode++) {
0180 
0181         if (~mode->valid_norms & 1<<priv->norm)
0182             continue;
0183 
0184         if (mode->mode.hdisplay != drm_mode->hdisplay ||
0185             mode->mode.vdisplay != drm_mode->vdisplay ||
0186             mode->mode.vtotal != drm_mode->vtotal ||
0187             mode->mode.htotal != drm_mode->htotal ||
0188             mode->mode.clock != drm_mode->clock)
0189             continue;
0190 
0191         return mode;
0192     }
0193 
0194     return NULL;
0195 }
0196 
0197 /* Some common HW state calculation code */
0198 
0199 void ch7006_setup_levels(struct drm_encoder *encoder)
0200 {
0201     struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
0202     struct ch7006_priv *priv = to_ch7006_priv(encoder);
0203     uint8_t *regs = priv->state.regs;
0204     const struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
0205     int gain;
0206     int black_level;
0207 
0208     /* Set DAC_GAIN if the voltage drop between white and black is
0209      * high enough. */
0210     if (norm->black_level < 339*fixed1/1000) {
0211         gain = 76;
0212 
0213         regs[CH7006_INPUT_FORMAT] |= CH7006_INPUT_FORMAT_DAC_GAIN;
0214     } else {
0215         gain = 71;
0216 
0217         regs[CH7006_INPUT_FORMAT] &= ~CH7006_INPUT_FORMAT_DAC_GAIN;
0218     }
0219 
0220     black_level = round_fixed(norm->black_level*26625)/gain;
0221 
0222     /* Correct it with the specified brightness. */
0223     black_level = interpolate(90, black_level, 208, priv->brightness);
0224 
0225     regs[CH7006_BLACK_LEVEL] = bitf(CH7006_BLACK_LEVEL_0, black_level);
0226 
0227     ch7006_dbg(client, "black level: %d\n", black_level);
0228 }
0229 
0230 void ch7006_setup_subcarrier(struct drm_encoder *encoder)
0231 {
0232     struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
0233     struct ch7006_priv *priv = to_ch7006_priv(encoder);
0234     struct ch7006_state *state = &priv->state;
0235     const struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
0236     const struct ch7006_mode *mode = priv->mode;
0237     uint32_t subc_inc;
0238 
0239     subc_inc = round_fixed((mode->subc_coeff >> 8)
0240                    * (norm->subc_freq >> 24));
0241 
0242     setbitf(state, CH7006_SUBC_INC0, 28, subc_inc);
0243     setbitf(state, CH7006_SUBC_INC1, 24, subc_inc);
0244     setbitf(state, CH7006_SUBC_INC2, 20, subc_inc);
0245     setbitf(state, CH7006_SUBC_INC3, 16, subc_inc);
0246     setbitf(state, CH7006_SUBC_INC4, 12, subc_inc);
0247     setbitf(state, CH7006_SUBC_INC5, 8, subc_inc);
0248     setbitf(state, CH7006_SUBC_INC6, 4, subc_inc);
0249     setbitf(state, CH7006_SUBC_INC7, 0, subc_inc);
0250 
0251     ch7006_dbg(client, "subcarrier inc: %u\n", subc_inc);
0252 }
0253 
0254 void ch7006_setup_pll(struct drm_encoder *encoder)
0255 {
0256     struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
0257     struct ch7006_priv *priv = to_ch7006_priv(encoder);
0258     uint8_t *regs = priv->state.regs;
0259     const struct ch7006_mode *mode = priv->mode;
0260     int n, best_n = 0;
0261     int m, best_m = 0;
0262     int freq, best_freq = 0;
0263 
0264     for (n = 0; n < CH7006_MAXN; n++) {
0265         for (m = 0; m < CH7006_MAXM; m++) {
0266             freq = CH7006_FREQ0*(n+2)/(m+2);
0267 
0268             if (abs(freq - mode->mode.clock) <
0269                 abs(best_freq - mode->mode.clock)) {
0270                 best_freq = freq;
0271                 best_n = n;
0272                 best_m = m;
0273             }
0274         }
0275     }
0276 
0277     regs[CH7006_PLLOV] = bitf(CH7006_PLLOV_N_8, best_n) |
0278         bitf(CH7006_PLLOV_M_8, best_m);
0279 
0280     regs[CH7006_PLLM] = bitf(CH7006_PLLM_0, best_m);
0281     regs[CH7006_PLLN] = bitf(CH7006_PLLN_0, best_n);
0282 
0283     if (best_n < 108)
0284         regs[CH7006_PLL_CONTROL] |= CH7006_PLL_CONTROL_CAPACITOR;
0285     else
0286         regs[CH7006_PLL_CONTROL] &= ~CH7006_PLL_CONTROL_CAPACITOR;
0287 
0288     ch7006_dbg(client, "n=%d m=%d f=%d c=%d\n",
0289            best_n, best_m, best_freq, best_n < 108);
0290 }
0291 
0292 void ch7006_setup_power_state(struct drm_encoder *encoder)
0293 {
0294     struct ch7006_priv *priv = to_ch7006_priv(encoder);
0295     uint8_t *power = &priv->state.regs[CH7006_POWER];
0296     int subconnector;
0297 
0298     subconnector = priv->select_subconnector ? priv->select_subconnector :
0299                             priv->subconnector;
0300 
0301     *power = CH7006_POWER_RESET;
0302 
0303     if (priv->last_dpms == DRM_MODE_DPMS_ON) {
0304         switch (subconnector) {
0305         case DRM_MODE_SUBCONNECTOR_SVIDEO:
0306             *power |= bitfs(CH7006_POWER_LEVEL, CVBS_OFF);
0307             break;
0308         case DRM_MODE_SUBCONNECTOR_Composite:
0309             *power |= bitfs(CH7006_POWER_LEVEL, SVIDEO_OFF);
0310             break;
0311         case DRM_MODE_SUBCONNECTOR_SCART:
0312             *power |= bitfs(CH7006_POWER_LEVEL, NORMAL) |
0313                 CH7006_POWER_SCART;
0314             break;
0315         }
0316 
0317     } else {
0318         if (priv->chip_version >= 0x20)
0319             *power |= bitfs(CH7006_POWER_LEVEL, FULL_POWER_OFF);
0320         else
0321             *power |= bitfs(CH7006_POWER_LEVEL, POWER_OFF);
0322     }
0323 }
0324 
0325 void ch7006_setup_properties(struct drm_encoder *encoder)
0326 {
0327     struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
0328     struct ch7006_priv *priv = to_ch7006_priv(encoder);
0329     struct ch7006_state *state = &priv->state;
0330     const struct ch7006_tv_norm_info *norm = &ch7006_tv_norms[priv->norm];
0331     const struct ch7006_mode *ch_mode = priv->mode;
0332     const struct drm_display_mode *mode = &ch_mode->mode;
0333     uint8_t *regs = state->regs;
0334     int flicker, contrast, hpos, vpos;
0335     uint64_t scale, aspect;
0336 
0337     flicker = interpolate(0, 2, 3, priv->flicker);
0338     regs[CH7006_FFILTER] = bitf(CH7006_FFILTER_TEXT, flicker) |
0339         bitf(CH7006_FFILTER_LUMA, flicker) |
0340         bitf(CH7006_FFILTER_CHROMA, 1);
0341 
0342     contrast = interpolate(0, 5, 7, priv->contrast);
0343     regs[CH7006_CONTRAST] = bitf(CH7006_CONTRAST_0, contrast);
0344 
0345     scale = norm->vtotal*fixed1;
0346     do_div(scale, mode->vtotal);
0347 
0348     aspect = ch_mode->enc_hdisp*fixed1;
0349     do_div(aspect, ch_mode->enc_vdisp);
0350 
0351     hpos = round_fixed((norm->hvirtual * aspect - mode->hdisplay * scale)
0352                * priv->hmargin * mode->vtotal) / norm->vtotal / 100 / 4;
0353 
0354     setbitf(state, CH7006_POV, HPOS_8, hpos);
0355     setbitf(state, CH7006_HPOS, 0, hpos);
0356 
0357     vpos = max(0, norm->vdisplay - round_fixed(mode->vdisplay*scale)
0358            + norm->voffset) * priv->vmargin / 100 / 2;
0359 
0360     setbitf(state, CH7006_POV, VPOS_8, vpos);
0361     setbitf(state, CH7006_VPOS, 0, vpos);
0362 
0363     ch7006_dbg(client, "hpos: %d, vpos: %d\n", hpos, vpos);
0364 }
0365 
0366 /* HW access functions */
0367 
0368 void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val)
0369 {
0370     uint8_t buf[] = {addr, val};
0371     int ret;
0372 
0373     ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
0374     if (ret < 0)
0375         ch7006_err(client, "Error %d writing to subaddress 0x%x\n",
0376                ret, addr);
0377 }
0378 
0379 uint8_t ch7006_read(struct i2c_client *client, uint8_t addr)
0380 {
0381     uint8_t val;
0382     int ret;
0383 
0384     ret = i2c_master_send(client, &addr, sizeof(addr));
0385     if (ret < 0)
0386         goto fail;
0387 
0388     ret = i2c_master_recv(client, &val, sizeof(val));
0389     if (ret < 0)
0390         goto fail;
0391 
0392     return val;
0393 
0394 fail:
0395     ch7006_err(client, "Error %d reading from subaddress 0x%x\n",
0396            ret, addr);
0397     return 0;
0398 }
0399 
0400 void ch7006_state_load(struct i2c_client *client,
0401                struct ch7006_state *state)
0402 {
0403     ch7006_load_reg(client, state, CH7006_POWER);
0404 
0405     ch7006_load_reg(client, state, CH7006_DISPMODE);
0406     ch7006_load_reg(client, state, CH7006_FFILTER);
0407     ch7006_load_reg(client, state, CH7006_BWIDTH);
0408     ch7006_load_reg(client, state, CH7006_INPUT_FORMAT);
0409     ch7006_load_reg(client, state, CH7006_CLKMODE);
0410     ch7006_load_reg(client, state, CH7006_START_ACTIVE);
0411     ch7006_load_reg(client, state, CH7006_POV);
0412     ch7006_load_reg(client, state, CH7006_BLACK_LEVEL);
0413     ch7006_load_reg(client, state, CH7006_HPOS);
0414     ch7006_load_reg(client, state, CH7006_VPOS);
0415     ch7006_load_reg(client, state, CH7006_INPUT_SYNC);
0416     ch7006_load_reg(client, state, CH7006_DETECT);
0417     ch7006_load_reg(client, state, CH7006_CONTRAST);
0418     ch7006_load_reg(client, state, CH7006_PLLOV);
0419     ch7006_load_reg(client, state, CH7006_PLLM);
0420     ch7006_load_reg(client, state, CH7006_PLLN);
0421     ch7006_load_reg(client, state, CH7006_BCLKOUT);
0422     ch7006_load_reg(client, state, CH7006_SUBC_INC0);
0423     ch7006_load_reg(client, state, CH7006_SUBC_INC1);
0424     ch7006_load_reg(client, state, CH7006_SUBC_INC2);
0425     ch7006_load_reg(client, state, CH7006_SUBC_INC3);
0426     ch7006_load_reg(client, state, CH7006_SUBC_INC4);
0427     ch7006_load_reg(client, state, CH7006_SUBC_INC5);
0428     ch7006_load_reg(client, state, CH7006_SUBC_INC6);
0429     ch7006_load_reg(client, state, CH7006_SUBC_INC7);
0430     ch7006_load_reg(client, state, CH7006_PLL_CONTROL);
0431     ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0);
0432 }
0433 
0434 void ch7006_state_save(struct i2c_client *client,
0435                struct ch7006_state *state)
0436 {
0437     ch7006_save_reg(client, state, CH7006_POWER);
0438 
0439     ch7006_save_reg(client, state, CH7006_DISPMODE);
0440     ch7006_save_reg(client, state, CH7006_FFILTER);
0441     ch7006_save_reg(client, state, CH7006_BWIDTH);
0442     ch7006_save_reg(client, state, CH7006_INPUT_FORMAT);
0443     ch7006_save_reg(client, state, CH7006_CLKMODE);
0444     ch7006_save_reg(client, state, CH7006_START_ACTIVE);
0445     ch7006_save_reg(client, state, CH7006_POV);
0446     ch7006_save_reg(client, state, CH7006_BLACK_LEVEL);
0447     ch7006_save_reg(client, state, CH7006_HPOS);
0448     ch7006_save_reg(client, state, CH7006_VPOS);
0449     ch7006_save_reg(client, state, CH7006_INPUT_SYNC);
0450     ch7006_save_reg(client, state, CH7006_DETECT);
0451     ch7006_save_reg(client, state, CH7006_CONTRAST);
0452     ch7006_save_reg(client, state, CH7006_PLLOV);
0453     ch7006_save_reg(client, state, CH7006_PLLM);
0454     ch7006_save_reg(client, state, CH7006_PLLN);
0455     ch7006_save_reg(client, state, CH7006_BCLKOUT);
0456     ch7006_save_reg(client, state, CH7006_SUBC_INC0);
0457     ch7006_save_reg(client, state, CH7006_SUBC_INC1);
0458     ch7006_save_reg(client, state, CH7006_SUBC_INC2);
0459     ch7006_save_reg(client, state, CH7006_SUBC_INC3);
0460     ch7006_save_reg(client, state, CH7006_SUBC_INC4);
0461     ch7006_save_reg(client, state, CH7006_SUBC_INC5);
0462     ch7006_save_reg(client, state, CH7006_SUBC_INC6);
0463     ch7006_save_reg(client, state, CH7006_SUBC_INC7);
0464     ch7006_save_reg(client, state, CH7006_PLL_CONTROL);
0465     ch7006_save_reg(client, state, CH7006_CALC_SUBC_INC0);
0466 
0467     state->regs[CH7006_FFILTER] = (state->regs[CH7006_FFILTER] & 0xf0) |
0468         (state->regs[CH7006_FFILTER] & 0x0c) >> 2 |
0469         (state->regs[CH7006_FFILTER] & 0x03) << 2;
0470 }
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