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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver
0004  *
0005  * Copyright (c) 2016 Linaro Limited.
0006  * Copyright (c) 2014-2016 HiSilicon Limited.
0007  *
0008  * Author:
0009  *  Xinliang Liu <z.liuxinliang@hisilicon.com>
0010  *  Xinliang Liu <xinliang.liu@linaro.org>
0011  *  Xinwei Kong <kong.kongxinwei@hisilicon.com>
0012  */
0013 
0014 #include <linux/bitops.h>
0015 #include <linux/clk.h>
0016 #include <linux/mfd/syscon.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/regmap.h>
0019 #include <linux/reset.h>
0020 
0021 #include <video/display_timing.h>
0022 
0023 #include <drm/drm_atomic.h>
0024 #include <drm/drm_atomic_helper.h>
0025 #include <drm/drm_crtc.h>
0026 #include <drm/drm_drv.h>
0027 #include <drm/drm_fb_cma_helper.h>
0028 #include <drm/drm_fourcc.h>
0029 #include <drm/drm_framebuffer.h>
0030 #include <drm/drm_gem_cma_helper.h>
0031 #include <drm/drm_plane_helper.h>
0032 #include <drm/drm_probe_helper.h>
0033 #include <drm/drm_vblank.h>
0034 #include <drm/drm_gem_framebuffer_helper.h>
0035 
0036 #include "kirin_drm_drv.h"
0037 #include "kirin_ade_reg.h"
0038 
0039 #define OUT_OVLY    ADE_OVLY2 /* output overlay compositor */
0040 #define ADE_DEBUG   1
0041 
0042 
0043 struct ade_hw_ctx {
0044     void __iomem  *base;
0045     struct regmap *noc_regmap;
0046     struct clk *ade_core_clk;
0047     struct clk *media_noc_clk;
0048     struct clk *ade_pix_clk;
0049     struct reset_control *reset;
0050     bool power_on;
0051     int irq;
0052 
0053     struct drm_crtc *crtc;
0054 };
0055 
0056 static const struct kirin_format ade_formats[] = {
0057     /* 16bpp RGB: */
0058     { DRM_FORMAT_RGB565, ADE_RGB_565 },
0059     { DRM_FORMAT_BGR565, ADE_BGR_565 },
0060     /* 24bpp RGB: */
0061     { DRM_FORMAT_RGB888, ADE_RGB_888 },
0062     { DRM_FORMAT_BGR888, ADE_BGR_888 },
0063     /* 32bpp [A]RGB: */
0064     { DRM_FORMAT_XRGB8888, ADE_XRGB_8888 },
0065     { DRM_FORMAT_XBGR8888, ADE_XBGR_8888 },
0066     { DRM_FORMAT_RGBA8888, ADE_RGBA_8888 },
0067     { DRM_FORMAT_BGRA8888, ADE_BGRA_8888 },
0068     { DRM_FORMAT_ARGB8888, ADE_ARGB_8888 },
0069     { DRM_FORMAT_ABGR8888, ADE_ABGR_8888 },
0070 };
0071 
0072 static const u32 channel_formats[] = {
0073     /* channel 1,2,3,4 */
0074     DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
0075     DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
0076     DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
0077     DRM_FORMAT_ABGR8888
0078 };
0079 
0080 /* convert from fourcc format to ade format */
0081 static u32 ade_get_format(u32 pixel_format)
0082 {
0083     int i;
0084 
0085     for (i = 0; i < ARRAY_SIZE(ade_formats); i++)
0086         if (ade_formats[i].pixel_format == pixel_format)
0087             return ade_formats[i].hw_format;
0088 
0089     /* not found */
0090     DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",
0091           pixel_format);
0092     return ADE_FORMAT_UNSUPPORT;
0093 }
0094 
0095 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val)
0096 {
0097     u32 bit_ofst, reg_num;
0098 
0099     bit_ofst = bit_num % 32;
0100     reg_num = bit_num / 32;
0101 
0102     ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst,
0103             MASK(1), !!val);
0104 }
0105 
0106 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num)
0107 {
0108     u32 tmp, bit_ofst, reg_num;
0109 
0110     bit_ofst = bit_num % 32;
0111     reg_num = bit_num / 32;
0112 
0113     tmp = readl(base + ADE_RELOAD_DIS(reg_num));
0114     return !!(BIT(bit_ofst) & tmp);
0115 }
0116 
0117 static void ade_init(struct ade_hw_ctx *ctx)
0118 {
0119     void __iomem *base = ctx->base;
0120 
0121     /* enable clk gate */
0122     ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST,
0123             AUTO_CLK_GATE_EN, ADE_ENABLE);
0124     /* clear overlay */
0125     writel(0, base + ADE_OVLY1_TRANS_CFG);
0126     writel(0, base + ADE_OVLY_CTL);
0127     writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
0128     /* clear reset and reload regs */
0129     writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
0130     writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
0131     writel(MASK(32), base + ADE_RELOAD_DIS(0));
0132     writel(MASK(32), base + ADE_RELOAD_DIS(1));
0133     /*
0134      * for video mode, all the ade registers should
0135      * become effective at frame end.
0136      */
0137     ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
0138             FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
0139 }
0140 
0141 static bool ade_crtc_mode_fixup(struct drm_crtc *crtc,
0142                 const struct drm_display_mode *mode,
0143                 struct drm_display_mode *adjusted_mode)
0144 {
0145     struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
0146     struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
0147 
0148     adjusted_mode->clock =
0149         clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000;
0150     return true;
0151 }
0152 
0153 
0154 static void ade_set_pix_clk(struct ade_hw_ctx *ctx,
0155                 struct drm_display_mode *mode,
0156                 struct drm_display_mode *adj_mode)
0157 {
0158     u32 clk_Hz = mode->clock * 1000;
0159     int ret;
0160 
0161     /*
0162      * Success should be guaranteed in mode_valid call back,
0163      * so failure shouldn't happen here
0164      */
0165     ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz);
0166     if (ret)
0167         DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret);
0168     adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
0169 }
0170 
0171 static void ade_ldi_set_mode(struct ade_hw_ctx *ctx,
0172                  struct drm_display_mode *mode,
0173                  struct drm_display_mode *adj_mode)
0174 {
0175     void __iomem *base = ctx->base;
0176     u32 width = mode->hdisplay;
0177     u32 height = mode->vdisplay;
0178     u32 hfp, hbp, hsw, vfp, vbp, vsw;
0179     u32 plr_flags;
0180 
0181     plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0;
0182     plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0;
0183     hfp = mode->hsync_start - mode->hdisplay;
0184     hbp = mode->htotal - mode->hsync_end;
0185     hsw = mode->hsync_end - mode->hsync_start;
0186     vfp = mode->vsync_start - mode->vdisplay;
0187     vbp = mode->vtotal - mode->vsync_end;
0188     vsw = mode->vsync_end - mode->vsync_start;
0189     if (vsw > 15) {
0190         DRM_DEBUG_DRIVER("vsw exceeded 15\n");
0191         vsw = 15;
0192     }
0193 
0194     writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0);
0195      /* the configured value is actual value - 1 */
0196     writel(hsw - 1, base + LDI_HRZ_CTRL1);
0197     writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0);
0198      /* the configured value is actual value - 1 */
0199     writel(vsw - 1, base + LDI_VRT_CTRL1);
0200      /* the configured value is actual value - 1 */
0201     writel(((height - 1) << VSIZE_OFST) | (width - 1),
0202            base + LDI_DSP_SIZE);
0203     writel(plr_flags, base + LDI_PLR_CTRL);
0204 
0205     /* set overlay compositor output size */
0206     writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),
0207            base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY));
0208 
0209     /* ctran6 setting */
0210     writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
0211      /* the configured value is actual value - 1 */
0212     writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6));
0213     ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0);
0214 
0215     ade_set_pix_clk(ctx, mode, adj_mode);
0216 
0217     DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height);
0218 }
0219 
0220 static int ade_power_up(struct ade_hw_ctx *ctx)
0221 {
0222     int ret;
0223 
0224     ret = clk_prepare_enable(ctx->media_noc_clk);
0225     if (ret) {
0226         DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret);
0227         return ret;
0228     }
0229 
0230     ret = reset_control_deassert(ctx->reset);
0231     if (ret) {
0232         DRM_ERROR("failed to deassert reset\n");
0233         return ret;
0234     }
0235 
0236     ret = clk_prepare_enable(ctx->ade_core_clk);
0237     if (ret) {
0238         DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret);
0239         return ret;
0240     }
0241 
0242     ade_init(ctx);
0243     ctx->power_on = true;
0244     return 0;
0245 }
0246 
0247 static void ade_power_down(struct ade_hw_ctx *ctx)
0248 {
0249     void __iomem *base = ctx->base;
0250 
0251     writel(ADE_DISABLE, base + LDI_CTRL);
0252     /* dsi pixel off */
0253     writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT);
0254 
0255     clk_disable_unprepare(ctx->ade_core_clk);
0256     reset_control_assert(ctx->reset);
0257     clk_disable_unprepare(ctx->media_noc_clk);
0258     ctx->power_on = false;
0259 }
0260 
0261 static void ade_set_medianoc_qos(struct ade_hw_ctx *ctx)
0262 {
0263     struct regmap *map = ctx->noc_regmap;
0264 
0265     regmap_update_bits(map, ADE0_QOSGENERATOR_MODE,
0266                QOSGENERATOR_MODE_MASK, BYPASS_MODE);
0267     regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL,
0268                SOCKET_QOS_EN, SOCKET_QOS_EN);
0269 
0270     regmap_update_bits(map, ADE1_QOSGENERATOR_MODE,
0271                QOSGENERATOR_MODE_MASK, BYPASS_MODE);
0272     regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL,
0273                SOCKET_QOS_EN, SOCKET_QOS_EN);
0274 }
0275 
0276 static int ade_crtc_enable_vblank(struct drm_crtc *crtc)
0277 {
0278     struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
0279     struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
0280     void __iomem *base = ctx->base;
0281 
0282     if (!ctx->power_on)
0283         (void)ade_power_up(ctx);
0284 
0285     ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
0286             MASK(1), 1);
0287 
0288     return 0;
0289 }
0290 
0291 static void ade_crtc_disable_vblank(struct drm_crtc *crtc)
0292 {
0293     struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
0294     struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
0295     void __iomem *base = ctx->base;
0296 
0297     if (!ctx->power_on) {
0298         DRM_ERROR("power is down! vblank disable fail\n");
0299         return;
0300     }
0301 
0302     ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
0303             MASK(1), 0);
0304 }
0305 
0306 static irqreturn_t ade_irq_handler(int irq, void *data)
0307 {
0308     struct ade_hw_ctx *ctx = data;
0309     struct drm_crtc *crtc = ctx->crtc;
0310     void __iomem *base = ctx->base;
0311     u32 status;
0312 
0313     status = readl(base + LDI_MSK_INT);
0314     DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status);
0315 
0316     /* vblank irq */
0317     if (status & BIT(FRAME_END_INT_EN_OFST)) {
0318         ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST,
0319                 MASK(1), 1);
0320         drm_crtc_handle_vblank(crtc);
0321     }
0322 
0323     return IRQ_HANDLED;
0324 }
0325 
0326 static void ade_display_enable(struct ade_hw_ctx *ctx)
0327 {
0328     void __iomem *base = ctx->base;
0329     u32 out_fmt = LDI_OUT_RGB_888;
0330 
0331     /* enable output overlay compositor */
0332     writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
0333     ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0);
0334 
0335     /* display source setting */
0336     writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);
0337 
0338     /* enable ade */
0339     writel(ADE_ENABLE, base + ADE_EN);
0340     /* enable ldi */
0341     writel(NORMAL_MODE, base + LDI_WORK_MODE);
0342     writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN,
0343            base + LDI_CTRL);
0344     /* dsi pixel on */
0345     writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
0346 }
0347 
0348 #if ADE_DEBUG
0349 static void ade_rdma_dump_regs(void __iomem *base, u32 ch)
0350 {
0351     u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
0352     u32 val;
0353 
0354     reg_ctrl = RD_CH_CTRL(ch);
0355     reg_addr = RD_CH_ADDR(ch);
0356     reg_size = RD_CH_SIZE(ch);
0357     reg_stride = RD_CH_STRIDE(ch);
0358     reg_space = RD_CH_SPACE(ch);
0359     reg_en = RD_CH_EN(ch);
0360 
0361     val = ade_read_reload_bit(base, RDMA_OFST + ch);
0362     DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val);
0363     val = readl(base + reg_ctrl);
0364     DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val);
0365     val = readl(base + reg_addr);
0366     DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val);
0367     val = readl(base + reg_size);
0368     DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val);
0369     val = readl(base + reg_stride);
0370     DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val);
0371     val = readl(base + reg_space);
0372     DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val);
0373     val = readl(base + reg_en);
0374     DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val);
0375 }
0376 
0377 static void ade_clip_dump_regs(void __iomem *base, u32 ch)
0378 {
0379     u32 val;
0380 
0381     val = ade_read_reload_bit(base, CLIP_OFST + ch);
0382     DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val);
0383     val = readl(base + ADE_CLIP_DISABLE(ch));
0384     DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val);
0385     val = readl(base + ADE_CLIP_SIZE0(ch));
0386     DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val);
0387     val = readl(base + ADE_CLIP_SIZE1(ch));
0388     DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val);
0389 }
0390 
0391 static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch)
0392 {
0393     u8 ovly_ch = 0; /* TODO: Only primary plane now */
0394     u32 val;
0395 
0396     val = readl(base + ADE_OVLY_CH_XY0(ovly_ch));
0397     DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val);
0398     val = readl(base + ADE_OVLY_CH_XY1(ovly_ch));
0399     DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val);
0400     val = readl(base + ADE_OVLY_CH_CTL(ovly_ch));
0401     DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val);
0402 }
0403 
0404 static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp)
0405 {
0406     u32 val;
0407 
0408     val = ade_read_reload_bit(base, OVLY_OFST + comp);
0409     DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val);
0410     writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp));
0411     DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val);
0412     val = readl(base + ADE_OVLY_CTL);
0413     DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val);
0414 }
0415 
0416 static void ade_dump_regs(void __iomem *base)
0417 {
0418     u32 i;
0419 
0420     /* dump channel regs */
0421     for (i = 0; i < ADE_CH_NUM; i++) {
0422         /* dump rdma regs */
0423         ade_rdma_dump_regs(base, i);
0424 
0425         /* dump clip regs */
0426         ade_clip_dump_regs(base, i);
0427 
0428         /* dump compositor routing regs */
0429         ade_compositor_routing_dump_regs(base, i);
0430     }
0431 
0432     /* dump overlay compositor regs */
0433     ade_dump_overlay_compositor_regs(base, OUT_OVLY);
0434 }
0435 #else
0436 static void ade_dump_regs(void __iomem *base) { }
0437 #endif
0438 
0439 static void ade_crtc_atomic_enable(struct drm_crtc *crtc,
0440                    struct drm_atomic_state *state)
0441 {
0442     struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
0443     struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
0444     int ret;
0445 
0446     if (kcrtc->enable)
0447         return;
0448 
0449     if (!ctx->power_on) {
0450         ret = ade_power_up(ctx);
0451         if (ret)
0452             return;
0453     }
0454 
0455     ade_set_medianoc_qos(ctx);
0456     ade_display_enable(ctx);
0457     ade_dump_regs(ctx->base);
0458     drm_crtc_vblank_on(crtc);
0459     kcrtc->enable = true;
0460 }
0461 
0462 static void ade_crtc_atomic_disable(struct drm_crtc *crtc,
0463                     struct drm_atomic_state *state)
0464 {
0465     struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
0466     struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
0467 
0468     if (!kcrtc->enable)
0469         return;
0470 
0471     drm_crtc_vblank_off(crtc);
0472     ade_power_down(ctx);
0473     kcrtc->enable = false;
0474 }
0475 
0476 static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc)
0477 {
0478     struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
0479     struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
0480     struct drm_display_mode *mode = &crtc->state->mode;
0481     struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
0482 
0483     if (!ctx->power_on)
0484         (void)ade_power_up(ctx);
0485     ade_ldi_set_mode(ctx, mode, adj_mode);
0486 }
0487 
0488 static void ade_crtc_atomic_begin(struct drm_crtc *crtc,
0489                   struct drm_atomic_state *state)
0490 {
0491     struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
0492     struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
0493     struct drm_display_mode *mode = &crtc->state->mode;
0494     struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
0495 
0496     if (!ctx->power_on)
0497         (void)ade_power_up(ctx);
0498     ade_ldi_set_mode(ctx, mode, adj_mode);
0499 }
0500 
0501 static void ade_crtc_atomic_flush(struct drm_crtc *crtc,
0502                   struct drm_atomic_state *state)
0503 
0504 {
0505     struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
0506     struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
0507     struct drm_pending_vblank_event *event = crtc->state->event;
0508     void __iomem *base = ctx->base;
0509 
0510     /* only crtc is enabled regs take effect */
0511     if (kcrtc->enable) {
0512         ade_dump_regs(base);
0513         /* flush ade registers */
0514         writel(ADE_ENABLE, base + ADE_EN);
0515     }
0516 
0517     if (event) {
0518         crtc->state->event = NULL;
0519 
0520         spin_lock_irq(&crtc->dev->event_lock);
0521         if (drm_crtc_vblank_get(crtc) == 0)
0522             drm_crtc_arm_vblank_event(crtc, event);
0523         else
0524             drm_crtc_send_vblank_event(crtc, event);
0525         spin_unlock_irq(&crtc->dev->event_lock);
0526     }
0527 }
0528 
0529 static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = {
0530     .mode_fixup = ade_crtc_mode_fixup,
0531     .mode_set_nofb  = ade_crtc_mode_set_nofb,
0532     .atomic_begin   = ade_crtc_atomic_begin,
0533     .atomic_flush   = ade_crtc_atomic_flush,
0534     .atomic_enable  = ade_crtc_atomic_enable,
0535     .atomic_disable = ade_crtc_atomic_disable,
0536 };
0537 
0538 static const struct drm_crtc_funcs ade_crtc_funcs = {
0539     .destroy    = drm_crtc_cleanup,
0540     .set_config = drm_atomic_helper_set_config,
0541     .page_flip  = drm_atomic_helper_page_flip,
0542     .reset      = drm_atomic_helper_crtc_reset,
0543     .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
0544     .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
0545     .enable_vblank  = ade_crtc_enable_vblank,
0546     .disable_vblank = ade_crtc_disable_vblank,
0547 };
0548 
0549 static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb,
0550              u32 ch, u32 y, u32 in_h, u32 fmt)
0551 {
0552     struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0);
0553     u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
0554     u32 stride = fb->pitches[0];
0555     u32 addr = (u32)obj->paddr + y * stride;
0556 
0557     DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",
0558              ch + 1, y, in_h, stride, (u32)obj->paddr);
0559     DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%p4cc)\n",
0560              addr, fb->width, fb->height, fmt,
0561              &fb->format->format);
0562 
0563     /* get reg offset */
0564     reg_ctrl = RD_CH_CTRL(ch);
0565     reg_addr = RD_CH_ADDR(ch);
0566     reg_size = RD_CH_SIZE(ch);
0567     reg_stride = RD_CH_STRIDE(ch);
0568     reg_space = RD_CH_SPACE(ch);
0569     reg_en = RD_CH_EN(ch);
0570 
0571     /*
0572      * TODO: set rotation
0573      */
0574     writel((fmt << 16) & 0x1f0000, base + reg_ctrl);
0575     writel(addr, base + reg_addr);
0576     writel((in_h << 16) | stride, base + reg_size);
0577     writel(stride, base + reg_stride);
0578     writel(in_h * stride, base + reg_space);
0579     writel(ADE_ENABLE, base + reg_en);
0580     ade_update_reload_bit(base, RDMA_OFST + ch, 0);
0581 }
0582 
0583 static void ade_rdma_disable(void __iomem *base, u32 ch)
0584 {
0585     u32 reg_en;
0586 
0587     /* get reg offset */
0588     reg_en = RD_CH_EN(ch);
0589     writel(0, base + reg_en);
0590     ade_update_reload_bit(base, RDMA_OFST + ch, 1);
0591 }
0592 
0593 static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x,
0594              u32 in_w, u32 in_h)
0595 {
0596     u32 disable_val;
0597     u32 clip_left;
0598     u32 clip_right;
0599 
0600     /*
0601      * clip width, no need to clip height
0602      */
0603     if (fb_w == in_w) { /* bypass */
0604         disable_val = 1;
0605         clip_left = 0;
0606         clip_right = 0;
0607     } else {
0608         disable_val = 0;
0609         clip_left = x;
0610         clip_right = fb_w - (x + in_w) - 1;
0611     }
0612 
0613     DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n",
0614              ch + 1, clip_left, clip_right);
0615 
0616     writel(disable_val, base + ADE_CLIP_DISABLE(ch));
0617     writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch));
0618     writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch));
0619     ade_update_reload_bit(base, CLIP_OFST + ch, 0);
0620 }
0621 
0622 static void ade_clip_disable(void __iomem *base, u32 ch)
0623 {
0624     writel(1, base + ADE_CLIP_DISABLE(ch));
0625     ade_update_reload_bit(base, CLIP_OFST + ch, 1);
0626 }
0627 
0628 static bool has_Alpha_channel(int format)
0629 {
0630     switch (format) {
0631     case ADE_ARGB_8888:
0632     case ADE_ABGR_8888:
0633     case ADE_RGBA_8888:
0634     case ADE_BGRA_8888:
0635         return true;
0636     default:
0637         return false;
0638     }
0639 }
0640 
0641 static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode,
0642                     u8 *alp_sel, u8 *under_alp_sel)
0643 {
0644     bool has_alpha = has_Alpha_channel(fmt);
0645 
0646     /*
0647      * get alp_mode
0648      */
0649     if (has_alpha && glb_alpha < 255)
0650         *alp_mode = ADE_ALP_PIXEL_AND_GLB;
0651     else if (has_alpha)
0652         *alp_mode = ADE_ALP_PIXEL;
0653     else
0654         *alp_mode = ADE_ALP_GLOBAL;
0655 
0656     /*
0657      * get alp sel
0658      */
0659     *alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */
0660     *under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */
0661 }
0662 
0663 static void ade_compositor_routing_set(void __iomem *base, u8 ch,
0664                        u32 x0, u32 y0,
0665                        u32 in_w, u32 in_h, u32 fmt)
0666 {
0667     u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */
0668     u8 glb_alpha = 255;
0669     u32 x1 = x0 + in_w - 1;
0670     u32 y1 = y0 + in_h - 1;
0671     u32 val;
0672     u8 alp_sel;
0673     u8 under_alp_sel;
0674     u8 alp_mode;
0675 
0676     ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel,
0677                 &under_alp_sel);
0678 
0679     /* overlay routing setting
0680      */
0681     writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch));
0682     writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch));
0683     val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) |
0684         alp_sel << CH_ALP_SEL_OFST |
0685         under_alp_sel << CH_UNDER_ALP_SEL_OFST |
0686         glb_alpha << CH_ALP_GBL_OFST |
0687         alp_mode << CH_ALP_MODE_OFST;
0688     writel(val, base + ADE_OVLY_CH_CTL(ovly_ch));
0689     /* connect this plane/channel to overlay2 compositor */
0690     ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
0691             CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY));
0692 }
0693 
0694 static void ade_compositor_routing_disable(void __iomem *base, u32 ch)
0695 {
0696     u8 ovly_ch = 0; /* TODO: Only primary plane now */
0697 
0698     /* disable this plane/channel */
0699     ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST,
0700             MASK(1), 0);
0701     /* dis-connect this plane/channel of overlay2 compositor */
0702     ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
0703             CH_OVLY_SEL_MASK, 0);
0704 }
0705 
0706 /*
0707  * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor
0708  */
0709 static void ade_update_channel(struct kirin_plane *kplane,
0710                    struct drm_framebuffer *fb, int crtc_x,
0711                    int crtc_y, unsigned int crtc_w,
0712                    unsigned int crtc_h, u32 src_x,
0713                    u32 src_y, u32 src_w, u32 src_h)
0714 {
0715     struct ade_hw_ctx *ctx = kplane->hw_ctx;
0716     void __iomem *base = ctx->base;
0717     u32 fmt = ade_get_format(fb->format->format);
0718     u32 ch = kplane->ch;
0719     u32 in_w;
0720     u32 in_h;
0721 
0722     DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d",
0723              ch + 1, src_x, src_y, src_w, src_h,
0724              crtc_x, crtc_y, crtc_w, crtc_h);
0725 
0726     /* 1) DMA setting */
0727     in_w = src_w;
0728     in_h = src_h;
0729     ade_rdma_set(base, fb, ch, src_y, in_h, fmt);
0730 
0731     /* 2) clip setting */
0732     ade_clip_set(base, ch, fb->width, src_x, in_w, in_h);
0733 
0734     /* 3) TODO: scale setting for overlay planes */
0735 
0736     /* 4) TODO: ctran/csc setting for overlay planes */
0737 
0738     /* 5) compositor routing setting */
0739     ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt);
0740 }
0741 
0742 static void ade_disable_channel(struct kirin_plane *kplane)
0743 {
0744     struct ade_hw_ctx *ctx = kplane->hw_ctx;
0745     void __iomem *base = ctx->base;
0746     u32 ch = kplane->ch;
0747 
0748     DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1);
0749 
0750     /* disable read DMA */
0751     ade_rdma_disable(base, ch);
0752 
0753     /* disable clip */
0754     ade_clip_disable(base, ch);
0755 
0756     /* disable compositor routing */
0757     ade_compositor_routing_disable(base, ch);
0758 }
0759 
0760 static int ade_plane_atomic_check(struct drm_plane *plane,
0761                   struct drm_atomic_state *state)
0762 {
0763     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0764                                          plane);
0765     struct drm_framebuffer *fb = new_plane_state->fb;
0766     struct drm_crtc *crtc = new_plane_state->crtc;
0767     struct drm_crtc_state *crtc_state;
0768     u32 src_x = new_plane_state->src_x >> 16;
0769     u32 src_y = new_plane_state->src_y >> 16;
0770     u32 src_w = new_plane_state->src_w >> 16;
0771     u32 src_h = new_plane_state->src_h >> 16;
0772     int crtc_x = new_plane_state->crtc_x;
0773     int crtc_y = new_plane_state->crtc_y;
0774     u32 crtc_w = new_plane_state->crtc_w;
0775     u32 crtc_h = new_plane_state->crtc_h;
0776     u32 fmt;
0777 
0778     if (!crtc || !fb)
0779         return 0;
0780 
0781     fmt = ade_get_format(fb->format->format);
0782     if (fmt == ADE_FORMAT_UNSUPPORT)
0783         return -EINVAL;
0784 
0785     crtc_state = drm_atomic_get_crtc_state(state, crtc);
0786     if (IS_ERR(crtc_state))
0787         return PTR_ERR(crtc_state);
0788 
0789     if (src_w != crtc_w || src_h != crtc_h) {
0790         return -EINVAL;
0791     }
0792 
0793     if (src_x + src_w > fb->width ||
0794         src_y + src_h > fb->height)
0795         return -EINVAL;
0796 
0797     if (crtc_x < 0 || crtc_y < 0)
0798         return -EINVAL;
0799 
0800     if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay ||
0801         crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay)
0802         return -EINVAL;
0803 
0804     return 0;
0805 }
0806 
0807 static void ade_plane_atomic_update(struct drm_plane *plane,
0808                     struct drm_atomic_state *state)
0809 {
0810     struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
0811                                        plane);
0812     struct kirin_plane *kplane = to_kirin_plane(plane);
0813 
0814     ade_update_channel(kplane, new_state->fb, new_state->crtc_x,
0815                new_state->crtc_y,
0816                new_state->crtc_w, new_state->crtc_h,
0817                new_state->src_x >> 16, new_state->src_y >> 16,
0818                new_state->src_w >> 16, new_state->src_h >> 16);
0819 }
0820 
0821 static void ade_plane_atomic_disable(struct drm_plane *plane,
0822                      struct drm_atomic_state *state)
0823 {
0824     struct kirin_plane *kplane = to_kirin_plane(plane);
0825 
0826     ade_disable_channel(kplane);
0827 }
0828 
0829 static const struct drm_plane_helper_funcs ade_plane_helper_funcs = {
0830     .atomic_check = ade_plane_atomic_check,
0831     .atomic_update = ade_plane_atomic_update,
0832     .atomic_disable = ade_plane_atomic_disable,
0833 };
0834 
0835 static struct drm_plane_funcs ade_plane_funcs = {
0836     .update_plane   = drm_atomic_helper_update_plane,
0837     .disable_plane  = drm_atomic_helper_disable_plane,
0838     .destroy = drm_plane_cleanup,
0839     .reset = drm_atomic_helper_plane_reset,
0840     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
0841     .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
0842 };
0843 
0844 static void *ade_hw_ctx_alloc(struct platform_device *pdev,
0845                   struct drm_crtc *crtc)
0846 {
0847     struct resource *res;
0848     struct device *dev = &pdev->dev;
0849     struct device_node *np = pdev->dev.of_node;
0850     struct ade_hw_ctx *ctx = NULL;
0851     int ret;
0852 
0853     ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
0854     if (!ctx) {
0855         DRM_ERROR("failed to alloc ade_hw_ctx\n");
0856         return ERR_PTR(-ENOMEM);
0857     }
0858 
0859     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0860     ctx->base = devm_ioremap_resource(dev, res);
0861     if (IS_ERR(ctx->base)) {
0862         DRM_ERROR("failed to remap ade io base\n");
0863         return ERR_PTR(-EIO);
0864     }
0865 
0866     ctx->reset = devm_reset_control_get(dev, NULL);
0867     if (IS_ERR(ctx->reset))
0868         return ERR_PTR(-ENODEV);
0869 
0870     ctx->noc_regmap =
0871         syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon");
0872     if (IS_ERR(ctx->noc_regmap)) {
0873         DRM_ERROR("failed to get noc regmap\n");
0874         return ERR_PTR(-ENODEV);
0875     }
0876 
0877     ctx->irq = platform_get_irq(pdev, 0);
0878     if (ctx->irq < 0) {
0879         DRM_ERROR("failed to get irq\n");
0880         return ERR_PTR(-ENODEV);
0881     }
0882 
0883     ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core");
0884     if (IS_ERR(ctx->ade_core_clk)) {
0885         DRM_ERROR("failed to parse clk ADE_CORE\n");
0886         return ERR_PTR(-ENODEV);
0887     }
0888 
0889     ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg");
0890     if (IS_ERR(ctx->media_noc_clk)) {
0891         DRM_ERROR("failed to parse clk CODEC_JPEG\n");
0892         return ERR_PTR(-ENODEV);
0893     }
0894 
0895     ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix");
0896     if (IS_ERR(ctx->ade_pix_clk)) {
0897         DRM_ERROR("failed to parse clk ADE_PIX\n");
0898         return ERR_PTR(-ENODEV);
0899     }
0900 
0901     /* vblank irq init */
0902     ret = devm_request_irq(dev, ctx->irq, ade_irq_handler,
0903                    IRQF_SHARED, dev->driver->name, ctx);
0904     if (ret)
0905         return ERR_PTR(-EIO);
0906 
0907     ctx->crtc = crtc;
0908 
0909     return ctx;
0910 }
0911 
0912 static void ade_hw_ctx_cleanup(void *hw_ctx)
0913 {
0914 }
0915 
0916 static const struct drm_mode_config_funcs ade_mode_config_funcs = {
0917     .fb_create = drm_gem_fb_create,
0918     .atomic_check = drm_atomic_helper_check,
0919     .atomic_commit = drm_atomic_helper_commit,
0920 
0921 };
0922 
0923 DEFINE_DRM_GEM_CMA_FOPS(ade_fops);
0924 
0925 static const struct drm_driver ade_driver = {
0926     .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
0927     .fops = &ade_fops,
0928     DRM_GEM_CMA_DRIVER_OPS,
0929     .name = "kirin",
0930     .desc = "Hisilicon Kirin620 SoC DRM Driver",
0931     .date = "20150718",
0932     .major = 1,
0933     .minor = 0,
0934 };
0935 
0936 struct kirin_drm_data ade_driver_data = {
0937     .num_planes = ADE_CH_NUM,
0938     .prim_plane = ADE_CH1,
0939     .channel_formats = channel_formats,
0940     .channel_formats_cnt = ARRAY_SIZE(channel_formats),
0941     .config_max_width = 2048,
0942     .config_max_height = 2048,
0943     .driver = &ade_driver,
0944     .crtc_helper_funcs = &ade_crtc_helper_funcs,
0945     .crtc_funcs = &ade_crtc_funcs,
0946     .plane_helper_funcs = &ade_plane_helper_funcs,
0947     .plane_funcs = &ade_plane_funcs,
0948     .mode_config_funcs = &ade_mode_config_funcs,
0949 
0950     .alloc_hw_ctx = ade_hw_ctx_alloc,
0951     .cleanup_hw_ctx = ade_hw_ctx_cleanup,
0952 };
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