hisilicon/kirin/kirin_ade_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2016 Linaro Limited.
0004  * Copyright (c) 2014-2016 HiSilicon Limited.
0005  */
0006
0007 #ifndef __KIRIN_ADE_REG_H__
0008 #define __KIRIN_ADE_REG_H__
0009
0010 /*
0011  * ADE Registers
0012  */
0013 #define MASK(x)             (BIT(x) - 1)
0014
0015 #define ADE_CTRL            0x0004
0016 #define FRM_END_START_OFST      0
0017 #define FRM_END_START_MASK      MASK(2)
0018 #define AUTO_CLK_GATE_EN_OFST       0
0019 #define AUTO_CLK_GATE_EN        BIT(0)
0020 #define ADE_DISP_SRC_CFG        0x0018
0021 #define ADE_CTRL1           0x008C
0022 #define ADE_EN              0x0100
0023 #define ADE_DISABLE         0
0024 #define ADE_ENABLE          1
0025 /* reset and reload regs */
0026 #define ADE_SOFT_RST_SEL(x)     (0x0078 + (x) * 0x4)
0027 #define ADE_RELOAD_DIS(x)       (0x00AC + (x) * 0x4)
0028 #define RDMA_OFST           0
0029 #define CLIP_OFST           15
0030 #define SCL_OFST            21
0031 #define CTRAN_OFST          24
0032 #define OVLY_OFST           37 /* 32+5 */
0033 /* channel regs */
0034 #define RD_CH_CTRL(x)           (0x1004 + (x) * 0x80)
0035 #define RD_CH_ADDR(x)           (0x1008 + (x) * 0x80)
0036 #define RD_CH_SIZE(x)           (0x100C + (x) * 0x80)
0037 #define RD_CH_STRIDE(x)         (0x1010 + (x) * 0x80)
0038 #define RD_CH_SPACE(x)          (0x1014 + (x) * 0x80)
0039 #define RD_CH_EN(x)         (0x1020 + (x) * 0x80)
0040 /* overlay regs */
0041 #define ADE_OVLY1_TRANS_CFG     0x002C
0042 #define ADE_OVLY_CTL            0x0098
0043 #define ADE_OVLY_CH_XY0(x)      (0x2004 + (x) * 4)
0044 #define ADE_OVLY_CH_XY1(x)      (0x2024 + (x) * 4)
0045 #define ADE_OVLY_CH_CTL(x)      (0x204C + (x) * 4)
0046 #define ADE_OVLY_OUTPUT_SIZE(x)     (0x2070 + (x) * 8)
0047 #define OUTPUT_XSIZE_OFST       16
0048 #define ADE_OVLYX_CTL(x)        (0x209C + (x) * 4)
0049 #define CH_OVLY_SEL_OFST(x)     ((x) * 4)
0050 #define CH_OVLY_SEL_MASK        MASK(2)
0051 #define CH_OVLY_SEL_VAL(x)      ((x) + 1)
0052 #define CH_ALP_MODE_OFST        0
0053 #define CH_ALP_SEL_OFST         2
0054 #define CH_UNDER_ALP_SEL_OFST       4
0055 #define CH_EN_OFST          6
0056 #define CH_ALP_GBL_OFST         15
0057 #define CH_SEL_OFST         28
0058 /* ctran regs */
0059 #define ADE_CTRAN_DIS(x)        (0x5004 + (x) * 0x100)
0060 #define CTRAN_BYPASS_ON         1
0061 #define CTRAN_BYPASS_OFF        0
0062 #define ADE_CTRAN_IMAGE_SIZE(x)     (0x503C + (x) * 0x100)
0063 /* clip regs */
0064 #define ADE_CLIP_DISABLE(x)     (0x6800 + (x) * 0x100)
0065 #define ADE_CLIP_SIZE0(x)       (0x6804 + (x) * 0x100)
0066 #define ADE_CLIP_SIZE1(x)       (0x6808 + (x) * 0x100)
0067
0068 /*
0069  * LDI Registers
0070  */
0071 #define LDI_HRZ_CTRL0           0x7400
0072 #define HBP_OFST            20
0073 #define LDI_HRZ_CTRL1           0x7404
0074 #define LDI_VRT_CTRL0           0x7408
0075 #define VBP_OFST            20
0076 #define LDI_VRT_CTRL1           0x740C
0077 #define LDI_PLR_CTRL            0x7410
0078 #define FLAG_NVSYNC         BIT(0)
0079 #define FLAG_NHSYNC         BIT(1)
0080 #define FLAG_NPIXCLK            BIT(2)
0081 #define FLAG_NDE            BIT(3)
0082 #define LDI_DSP_SIZE            0x7414
0083 #define VSIZE_OFST          20
0084 #define LDI_INT_EN          0x741C
0085 #define FRAME_END_INT_EN_OFST       1
0086 #define LDI_CTRL            0x7420
0087 #define BPP_OFST            3
0088 #define DATA_GATE_EN            BIT(2)
0089 #define LDI_EN              BIT(0)
0090 #define LDI_MSK_INT         0x7428
0091 #define LDI_INT_CLR         0x742C
0092 #define LDI_WORK_MODE           0x7430
0093 #define LDI_HDMI_DSI_GT         0x7434
0094
0095 /*
0096  * ADE media bus service regs
0097  */
0098 #define ADE0_QOSGENERATOR_MODE      0x010C
0099 #define QOSGENERATOR_MODE_MASK      MASK(2)
0100 #define ADE0_QOSGENERATOR_EXTCONTROL    0x0118
0101 #define SOCKET_QOS_EN           BIT(0)
0102 #define ADE1_QOSGENERATOR_MODE      0x020C
0103 #define ADE1_QOSGENERATOR_EXTCONTROL    0x0218
0104
0105 /*
0106  * ADE regs relevant enums
0107  */
0108 enum frame_end_start {
0109     /* regs take effect in every vsync */
0110     REG_EFFECTIVE_IN_VSYNC = 0,
0111     /* regs take effect in fist ade en and every frame end */
0112     REG_EFFECTIVE_IN_ADEEN_FRMEND,
0113     /* regs take effect in ade en immediately */
0114     REG_EFFECTIVE_IN_ADEEN,
0115     /* regs take effect in first vsync and every frame end */
0116     REG_EFFECTIVE_IN_VSYNC_FRMEND
0117 };
0118
0119 enum ade_fb_format {
0120     ADE_RGB_565 = 0,
0121     ADE_BGR_565,
0122     ADE_XRGB_8888,
0123     ADE_XBGR_8888,
0124     ADE_ARGB_8888,
0125     ADE_ABGR_8888,
0126     ADE_RGBA_8888,
0127     ADE_BGRA_8888,
0128     ADE_RGB_888,
0129     ADE_BGR_888 = 9,
0130     ADE_FORMAT_UNSUPPORT = 800
0131 };
0132
0133 enum ade_channel {
0134     ADE_CH1 = 0,    /* channel 1 for primary plane */
0135     ADE_CH_NUM
0136 };
0137
0138 enum ade_scale {
0139     ADE_SCL1 = 0,
0140     ADE_SCL2,
0141     ADE_SCL3,
0142     ADE_SCL_NUM
0143 };
0144
0145 enum ade_ctran {
0146     ADE_CTRAN1 = 0,
0147     ADE_CTRAN2,
0148     ADE_CTRAN3,
0149     ADE_CTRAN4,
0150     ADE_CTRAN5,
0151     ADE_CTRAN6,
0152     ADE_CTRAN_NUM
0153 };
0154
0155 enum ade_overlay {
0156     ADE_OVLY1 = 0,
0157     ADE_OVLY2,
0158     ADE_OVLY3,
0159     ADE_OVLY_NUM
0160 };
0161
0162 enum ade_alpha_mode {
0163     ADE_ALP_GLOBAL = 0,
0164     ADE_ALP_PIXEL,
0165     ADE_ALP_PIXEL_AND_GLB
0166 };
0167
0168 enum ade_alpha_blending_mode {
0169     ADE_ALP_MUL_COEFF_0 = 0,    /* alpha */
0170     ADE_ALP_MUL_COEFF_1,        /* 1-alpha */
0171     ADE_ALP_MUL_COEFF_2,        /* 0 */
0172     ADE_ALP_MUL_COEFF_3     /* 1 */
0173 };
0174
0175 /*
0176  * LDI regs relevant enums
0177  */
0178 enum dsi_pclk_en {
0179     DSI_PCLK_ON = 0,
0180     DSI_PCLK_OFF
0181 };
0182
0183 enum ldi_output_format {
0184     LDI_OUT_RGB_565 = 0,
0185     LDI_OUT_RGB_666,
0186     LDI_OUT_RGB_888
0187 };
0188
0189 enum ldi_work_mode {
0190     TEST_MODE = 0,
0191     NORMAL_MODE
0192 };
0193
0194 enum ldi_input_source {
0195     DISP_SRC_NONE = 0,
0196     DISP_SRC_OVLY2,
0197     DISP_SRC_DISP,
0198     DISP_SRC_ROT,
0199     DISP_SRC_SCL2
0200 };
0201
0202 /*
0203  * ADE media bus service relevant enums
0204  */
0205 enum qos_generator_mode {
0206     FIXED_MODE = 0,
0207     LIMITER_MODE,
0208     BYPASS_MODE,
0209     REGULATOR_MODE
0210 };
0211
0212 /*
0213  * Register Write/Read Helper functions
0214  */
0215 static inline void ade_update_bits(void __iomem *addr, u32 bit_start,
0216                    u32 mask, u32 val)
0217 {
0218     u32 tmp, orig;
0219
0220     orig = readl(addr);
0221     tmp = orig & ~(mask << bit_start);
0222     tmp |= (val & mask) << bit_start;
0223     writel(tmp, addr);
0224 }
0225
0226 #endif