hisilicon/kirin/dw_dsi_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2016 Linaro Limited.
0004  * Copyright (c) 2014-2016 HiSilicon Limited.
0005  */
0006
0007 #ifndef __DW_DSI_REG_H__
0008 #define __DW_DSI_REG_H__
0009
0010 #define MASK(x)             (BIT(x) - 1)
0011
0012 /*
0013  * regs
0014  */
0015 #define PWR_UP                  0x04  /* Core power-up */
0016 #define RESET                   0
0017 #define POWERUP                 BIT(0)
0018 #define PHY_IF_CFG              0xA4  /* D-PHY interface configuration */
0019 #define CLKMGR_CFG              0x08  /* the internal clock dividers */
0020 #define PHY_RSTZ                0xA0  /* D-PHY reset control */
0021 #define PHY_ENABLECLK           BIT(2)
0022 #define PHY_UNRSTZ              BIT(1)
0023 #define PHY_UNSHUTDOWNZ         BIT(0)
0024 #define PHY_TST_CTRL0           0xB4  /* D-PHY test interface control 0 */
0025 #define PHY_TST_CTRL1           0xB8  /* D-PHY test interface control 1 */
0026 #define CLK_TLPX                0x10
0027 #define CLK_THS_PREPARE         0x11
0028 #define CLK_THS_ZERO            0x12
0029 #define CLK_THS_TRAIL           0x13
0030 #define CLK_TWAKEUP             0x14
0031 #define DATA_TLPX(x)            (0x20 + ((x) << 4))
0032 #define DATA_THS_PREPARE(x)     (0x21 + ((x) << 4))
0033 #define DATA_THS_ZERO(x)        (0x22 + ((x) << 4))
0034 #define DATA_THS_TRAIL(x)       (0x23 + ((x) << 4))
0035 #define DATA_TTA_GO(x)          (0x24 + ((x) << 4))
0036 #define DATA_TTA_GET(x)         (0x25 + ((x) << 4))
0037 #define DATA_TWAKEUP(x)         (0x26 + ((x) << 4))
0038 #define PHY_CFG_I               0x60
0039 #define PHY_CFG_PLL_I           0x63
0040 #define PHY_CFG_PLL_II          0x64
0041 #define PHY_CFG_PLL_III         0x65
0042 #define PHY_CFG_PLL_IV          0x66
0043 #define PHY_CFG_PLL_V           0x67
0044 #define DPI_COLOR_CODING        0x10  /* DPI color coding */
0045 #define DPI_CFG_POL             0x14  /* DPI polarity configuration */
0046 #define VID_HSA_TIME            0x48  /* Horizontal Sync Active time */
0047 #define VID_HBP_TIME            0x4C  /* Horizontal Back Porch time */
0048 #define VID_HLINE_TIME          0x50  /* Line time */
0049 #define VID_VSA_LINES           0x54  /* Vertical Sync Active period */
0050 #define VID_VBP_LINES           0x58  /* Vertical Back Porch period */
0051 #define VID_VFP_LINES           0x5C  /* Vertical Front Porch period */
0052 #define VID_VACTIVE_LINES       0x60  /* Vertical resolution */
0053 #define VID_PKT_SIZE            0x3C  /* Video packet size */
0054 #define VID_MODE_CFG            0x38  /* Video mode configuration */
0055 #define PHY_TMR_CFG             0x9C  /* Data lanes timing configuration */
0056 #define BTA_TO_CNT              0x8C  /* Response timeout definition */
0057 #define PHY_TMR_LPCLK_CFG       0x98  /* clock lane timing configuration */
0058 #define CLK_DATA_TMR_CFG        0xCC
0059 #define LPCLK_CTRL              0x94  /* Low-power in clock lane */
0060 #define PHY_TXREQUESTCLKHS      BIT(0)
0061 #define MODE_CFG                0x34  /* Video or Command mode selection */
0062 #define PHY_STATUS              0xB0  /* D-PHY PPI status interface */
0063
0064 #define PHY_STOP_WAIT_TIME      0x30
0065
0066 /*
0067  * regs relevant enum
0068  */
0069 enum dpi_color_coding {
0070     DSI_24BITS_1 = 5,
0071 };
0072
0073 enum dsi_video_mode_type {
0074     DSI_NON_BURST_SYNC_PULSES = 0,
0075     DSI_NON_BURST_SYNC_EVENTS,
0076     DSI_BURST_SYNC_PULSES_1,
0077     DSI_BURST_SYNC_PULSES_2
0078 };
0079
0080 enum dsi_work_mode {
0081     DSI_VIDEO_MODE = 0,
0082     DSI_COMMAND_MODE
0083 };
0084
0085 /*
0086  * Register Write/Read Helper functions
0087  */
0088 static inline void dw_update_bits(void __iomem *addr, u32 bit_start,
0089                   u32 mask, u32 val)
0090 {
0091     u32 tmp, orig;
0092
0093     orig = readl(addr);
0094     tmp = orig & ~(mask << bit_start);
0095     tmp |= (val & mask) << bit_start;
0096     writel(tmp, addr);
0097 }
0098
0099 #endif /* __DW_DRM_DSI_H__ */