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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * DesignWare MIPI DSI Host Controller v1.02 driver
0004  *
0005  * Copyright (c) 2016 Linaro Limited.
0006  * Copyright (c) 2014-2016 HiSilicon Limited.
0007  *
0008  * Author:
0009  *  Xinliang Liu <z.liuxinliang@hisilicon.com>
0010  *  Xinliang Liu <xinliang.liu@linaro.org>
0011  *  Xinwei Kong <kong.kongxinwei@hisilicon.com>
0012  */
0013 
0014 #include <linux/clk.h>
0015 #include <linux/component.h>
0016 #include <linux/delay.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 
0021 #include <drm/drm_atomic_helper.h>
0022 #include <drm/drm_bridge.h>
0023 #include <drm/drm_device.h>
0024 #include <drm/drm_mipi_dsi.h>
0025 #include <drm/drm_of.h>
0026 #include <drm/drm_print.h>
0027 #include <drm/drm_probe_helper.h>
0028 #include <drm/drm_simple_kms_helper.h>
0029 
0030 #include "dw_dsi_reg.h"
0031 
0032 #define MAX_TX_ESC_CLK      10
0033 #define ROUND(x, y)     ((x) / (y) + \
0034                 ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
0035 #define PHY_REF_CLK_RATE    19200000
0036 #define PHY_REF_CLK_PERIOD_PS   (1000000000 / (PHY_REF_CLK_RATE / 1000))
0037 
0038 #define encoder_to_dsi(encoder) \
0039     container_of(encoder, struct dw_dsi, encoder)
0040 #define host_to_dsi(host) \
0041     container_of(host, struct dw_dsi, host)
0042 
0043 struct mipi_phy_params {
0044     u32 clk_t_lpx;
0045     u32 clk_t_hs_prepare;
0046     u32 clk_t_hs_zero;
0047     u32 clk_t_hs_trial;
0048     u32 clk_t_wakeup;
0049     u32 data_t_lpx;
0050     u32 data_t_hs_prepare;
0051     u32 data_t_hs_zero;
0052     u32 data_t_hs_trial;
0053     u32 data_t_ta_go;
0054     u32 data_t_ta_get;
0055     u32 data_t_wakeup;
0056     u32 hstx_ckg_sel;
0057     u32 pll_fbd_div5f;
0058     u32 pll_fbd_div1f;
0059     u32 pll_fbd_2p;
0060     u32 pll_enbwt;
0061     u32 pll_fbd_p;
0062     u32 pll_fbd_s;
0063     u32 pll_pre_div1p;
0064     u32 pll_pre_p;
0065     u32 pll_vco_750M;
0066     u32 pll_lpf_rs;
0067     u32 pll_lpf_cs;
0068     u32 clklp2hs_time;
0069     u32 clkhs2lp_time;
0070     u32 lp2hs_time;
0071     u32 hs2lp_time;
0072     u32 clk_to_data_delay;
0073     u32 data_to_clk_delay;
0074     u32 lane_byte_clk_kHz;
0075     u32 clk_division;
0076 };
0077 
0078 struct dsi_hw_ctx {
0079     void __iomem *base;
0080     struct clk *pclk;
0081 };
0082 
0083 struct dw_dsi {
0084     struct drm_encoder encoder;
0085     struct device *dev;
0086     struct mipi_dsi_host host;
0087     struct drm_display_mode cur_mode;
0088     struct dsi_hw_ctx *ctx;
0089     struct mipi_phy_params phy;
0090 
0091     u32 lanes;
0092     enum mipi_dsi_pixel_format format;
0093     unsigned long mode_flags;
0094     bool enable;
0095 };
0096 
0097 struct dsi_data {
0098     struct dw_dsi dsi;
0099     struct dsi_hw_ctx ctx;
0100 };
0101 
0102 struct dsi_phy_range {
0103     u32 min_range_kHz;
0104     u32 max_range_kHz;
0105     u32 pll_vco_750M;
0106     u32 hstx_ckg_sel;
0107 };
0108 
0109 static const struct dsi_phy_range dphy_range_info[] = {
0110     {   46875,    62500,   1,    7 },
0111     {   62500,    93750,   0,    7 },
0112     {   93750,   125000,   1,    6 },
0113     {  125000,   187500,   0,    6 },
0114     {  187500,   250000,   1,    5 },
0115     {  250000,   375000,   0,    5 },
0116     {  375000,   500000,   1,    4 },
0117     {  500000,   750000,   0,    4 },
0118     {  750000,  1000000,   1,    0 },
0119     { 1000000,  1500000,   0,    0 }
0120 };
0121 
0122 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
0123 {
0124     u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
0125     u32 tmp_kHz = req_kHz;
0126     u32 i = 0;
0127     u32 q_pll = 1;
0128     u32 m_pll = 0;
0129     u32 n_pll = 0;
0130     u32 r_pll = 1;
0131     u32 m_n = 0;
0132     u32 m_n_int = 0;
0133     u32 f_kHz = 0;
0134     u64 temp;
0135 
0136     /*
0137      * Find a rate >= req_kHz.
0138      */
0139     do {
0140         f_kHz = tmp_kHz;
0141 
0142         for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++)
0143             if (f_kHz >= dphy_range_info[i].min_range_kHz &&
0144                 f_kHz <= dphy_range_info[i].max_range_kHz)
0145                 break;
0146 
0147         if (i == ARRAY_SIZE(dphy_range_info)) {
0148             DRM_ERROR("%dkHz out of range\n", f_kHz);
0149             return 0;
0150         }
0151 
0152         phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M;
0153         phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel;
0154 
0155         if (phy->hstx_ckg_sel <= 7 &&
0156             phy->hstx_ckg_sel >= 4)
0157             q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
0158 
0159         temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
0160         m_n_int = temp / (u64)1000000000;
0161         m_n = (temp % (u64)1000000000) / (u64)100000000;
0162 
0163         if (m_n_int % 2 == 0) {
0164             if (m_n * 6 >= 50) {
0165                 n_pll = 2;
0166                 m_pll = (m_n_int + 1) * n_pll;
0167             } else if (m_n * 6 >= 30) {
0168                 n_pll = 3;
0169                 m_pll = m_n_int * n_pll + 2;
0170             } else {
0171                 n_pll = 1;
0172                 m_pll = m_n_int * n_pll;
0173             }
0174         } else {
0175             if (m_n * 6 >= 50) {
0176                 n_pll = 1;
0177                 m_pll = (m_n_int + 1) * n_pll;
0178             } else if (m_n * 6 >= 30) {
0179                 n_pll = 1;
0180                 m_pll = (m_n_int + 1) * n_pll;
0181             } else if (m_n * 6 >= 10) {
0182                 n_pll = 3;
0183                 m_pll = m_n_int * n_pll + 1;
0184             } else {
0185                 n_pll = 2;
0186                 m_pll = m_n_int * n_pll;
0187             }
0188         }
0189 
0190         if (n_pll == 1) {
0191             phy->pll_fbd_p = 0;
0192             phy->pll_pre_div1p = 1;
0193         } else {
0194             phy->pll_fbd_p = n_pll;
0195             phy->pll_pre_div1p = 0;
0196         }
0197 
0198         if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4)
0199             r_pll = 0x10 >> (7 - phy->pll_fbd_2p);
0200 
0201         if (m_pll == 2) {
0202             phy->pll_pre_p = 0;
0203             phy->pll_fbd_s = 0;
0204             phy->pll_fbd_div1f = 0;
0205             phy->pll_fbd_div5f = 1;
0206         } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) {
0207             phy->pll_pre_p = m_pll / (2 * r_pll);
0208             phy->pll_fbd_s = 0;
0209             phy->pll_fbd_div1f = 1;
0210             phy->pll_fbd_div5f = 0;
0211         } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) {
0212             if (((m_pll / (2 * r_pll)) % 2) == 0) {
0213                 phy->pll_pre_p =
0214                     (m_pll / (2 * r_pll)) / 2 - 1;
0215                 phy->pll_fbd_s =
0216                     (m_pll / (2 * r_pll)) % 2 + 2;
0217             } else {
0218                 phy->pll_pre_p =
0219                     (m_pll / (2 * r_pll)) / 2;
0220                 phy->pll_fbd_s =
0221                     (m_pll / (2 * r_pll)) % 2;
0222             }
0223             phy->pll_fbd_div1f = 0;
0224             phy->pll_fbd_div5f = 0;
0225         } else {
0226             phy->pll_pre_p = 0;
0227             phy->pll_fbd_s = 0;
0228             phy->pll_fbd_div1f = 0;
0229             phy->pll_fbd_div5f = 1;
0230         }
0231 
0232         f_kHz = (u64)1000000000 * (u64)m_pll /
0233             ((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
0234 
0235         if (f_kHz >= req_kHz)
0236             break;
0237 
0238         tmp_kHz += 10;
0239 
0240     } while (true);
0241 
0242     return f_kHz;
0243 }
0244 
0245 static void dsi_get_phy_params(u32 phy_req_kHz,
0246                    struct mipi_phy_params *phy)
0247 {
0248     u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
0249     u32 phy_rate_kHz;
0250     u32 ui;
0251 
0252     memset(phy, 0, sizeof(*phy));
0253 
0254     phy_rate_kHz = dsi_calc_phy_rate(phy_req_kHz, phy);
0255     if (!phy_rate_kHz)
0256         return;
0257 
0258     ui = 1000000 / phy_rate_kHz;
0259 
0260     phy->clk_t_lpx = ROUND(50, 8 * ui);
0261     phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
0262 
0263     phy->clk_t_hs_zero = ROUND(262, 8 * ui);
0264     phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
0265     phy->clk_t_wakeup = ROUND(1000000, (ref_clk_ps / 1000) - 1);
0266     if (phy->clk_t_wakeup > 0xff)
0267         phy->clk_t_wakeup = 0xff;
0268     phy->data_t_wakeup = phy->clk_t_wakeup;
0269     phy->data_t_lpx = phy->clk_t_lpx;
0270     phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
0271     phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
0272     phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
0273     phy->data_t_ta_go = 3;
0274     phy->data_t_ta_get = 4;
0275 
0276     phy->pll_enbwt = 1;
0277     phy->clklp2hs_time = ROUND(407, 8 * ui) + 12;
0278     phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
0279     phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
0280     phy->hs2lp_time = phy->clkhs2lp_time;
0281     phy->clk_to_data_delay = 1 + phy->clklp2hs_time;
0282     phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
0283                 phy->clkhs2lp_time;
0284 
0285     phy->lane_byte_clk_kHz = phy_rate_kHz / 8;
0286     phy->clk_division =
0287         DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK);
0288 }
0289 
0290 static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format)
0291 {
0292     u32 val;
0293 
0294     /*
0295      * TODO: only support RGB888 now, to support more
0296      */
0297     switch (format) {
0298     case MIPI_DSI_FMT_RGB888:
0299         val = DSI_24BITS_1;
0300         break;
0301     default:
0302         val = DSI_24BITS_1;
0303         break;
0304     }
0305 
0306     return val;
0307 }
0308 
0309 /*
0310  * dsi phy reg write function
0311  */
0312 static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val)
0313 {
0314     u32 reg_write = 0x10000 + reg;
0315 
0316     /*
0317      * latch reg first
0318      */
0319     writel(reg_write, base + PHY_TST_CTRL1);
0320     writel(0x02, base + PHY_TST_CTRL0);
0321     writel(0x00, base + PHY_TST_CTRL0);
0322 
0323     /*
0324      * then latch value
0325      */
0326     writel(val, base + PHY_TST_CTRL1);
0327     writel(0x02, base + PHY_TST_CTRL0);
0328     writel(0x00, base + PHY_TST_CTRL0);
0329 }
0330 
0331 static void dsi_set_phy_timer(void __iomem *base,
0332                   struct mipi_phy_params *phy,
0333                   u32 lanes)
0334 {
0335     u32 val;
0336 
0337     /*
0338      * Set lane value and phy stop wait time.
0339      */
0340     val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8);
0341     writel(val, base + PHY_IF_CFG);
0342 
0343     /*
0344      * Set phy clk division.
0345      */
0346     val = readl(base + CLKMGR_CFG) | phy->clk_division;
0347     writel(val, base + CLKMGR_CFG);
0348 
0349     /*
0350      * Set lp and hs switching params.
0351      */
0352     dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time);
0353     dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time);
0354     dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10),
0355                phy->clkhs2lp_time);
0356     dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10),
0357                phy->clklp2hs_time);
0358     dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8),
0359                phy->data_to_clk_delay);
0360     dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8),
0361                phy->clk_to_data_delay);
0362 }
0363 
0364 static void dsi_set_mipi_phy(void __iomem *base,
0365                  struct mipi_phy_params *phy,
0366                  u32 lanes)
0367 {
0368     u32 delay_count;
0369     u32 val;
0370     u32 i;
0371 
0372     /* phy timer setting */
0373     dsi_set_phy_timer(base, phy, lanes);
0374 
0375     /*
0376      * Reset to clean up phy tst params.
0377      */
0378     writel(0, base + PHY_RSTZ);
0379     writel(0, base + PHY_TST_CTRL0);
0380     writel(1, base + PHY_TST_CTRL0);
0381     writel(0, base + PHY_TST_CTRL0);
0382 
0383     /*
0384      * Clock lane timing control setting: TLPX, THS-PREPARE,
0385      * THS-ZERO, THS-TRAIL, TWAKEUP.
0386      */
0387     dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx);
0388     dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare);
0389     dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero);
0390     dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial);
0391     dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup);
0392 
0393     /*
0394      * Data lane timing control setting: TLPX, THS-PREPARE,
0395      * THS-ZERO, THS-TRAIL, TTA-GO, TTA-GET, TWAKEUP.
0396      */
0397     for (i = 0; i < lanes; i++) {
0398         dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx);
0399         dsi_phy_tst_set(base, DATA_THS_PREPARE(i),
0400                 phy->data_t_hs_prepare);
0401         dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero);
0402         dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial);
0403         dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go);
0404         dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get);
0405         dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup);
0406     }
0407 
0408     /*
0409      * physical configuration: I, pll I, pll II, pll III,
0410      * pll IV, pll V.
0411      */
0412     dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel);
0413     val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) +
0414                 (phy->pll_fbd_2p << 1) + phy->pll_enbwt;
0415     dsi_phy_tst_set(base, PHY_CFG_PLL_I, val);
0416     dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p);
0417     dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s);
0418     val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p;
0419     dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val);
0420     val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) +
0421         phy->pll_lpf_cs;
0422     dsi_phy_tst_set(base, PHY_CFG_PLL_V, val);
0423 
0424     writel(PHY_ENABLECLK, base + PHY_RSTZ);
0425     udelay(1);
0426     writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
0427     udelay(1);
0428     writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
0429     usleep_range(1000, 1500);
0430 
0431     /*
0432      * wait for phy's clock ready
0433      */
0434     delay_count = 100;
0435     while (delay_count) {
0436         val = readl(base +  PHY_STATUS);
0437         if ((BIT(0) | BIT(2)) & val)
0438             break;
0439 
0440         udelay(1);
0441         delay_count--;
0442     }
0443 
0444     if (!delay_count)
0445         DRM_INFO("phylock and phystopstateclklane is not ready.\n");
0446 }
0447 
0448 static void dsi_set_mode_timing(void __iomem *base,
0449                 u32 lane_byte_clk_kHz,
0450                 struct drm_display_mode *mode,
0451                 enum mipi_dsi_pixel_format format)
0452 {
0453     u32 hfp, hbp, hsw, vfp, vbp, vsw;
0454     u32 hline_time;
0455     u32 hsa_time;
0456     u32 hbp_time;
0457     u32 pixel_clk_kHz;
0458     int htot, vtot;
0459     u32 val;
0460     u64 tmp;
0461 
0462     val = dsi_get_dpi_color_coding(format);
0463     writel(val, base + DPI_COLOR_CODING);
0464 
0465     val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2;
0466     val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1;
0467     writel(val, base +  DPI_CFG_POL);
0468 
0469     /*
0470      * The DSI IP accepts vertical timing using lines as normal,
0471      * but horizontal timing is a mixture of pixel-clocks for the
0472      * active region and byte-lane clocks for the blanking-related
0473      * timings.  hfp is specified as the total hline_time in byte-
0474      * lane clocks minus hsa, hbp and active.
0475      */
0476     pixel_clk_kHz = mode->clock;
0477     htot = mode->htotal;
0478     vtot = mode->vtotal;
0479     hfp = mode->hsync_start - mode->hdisplay;
0480     hbp = mode->htotal - mode->hsync_end;
0481     hsw = mode->hsync_end - mode->hsync_start;
0482     vfp = mode->vsync_start - mode->vdisplay;
0483     vbp = mode->vtotal - mode->vsync_end;
0484     vsw = mode->vsync_end - mode->vsync_start;
0485     if (vsw > 15) {
0486         DRM_DEBUG_DRIVER("vsw exceeded 15\n");
0487         vsw = 15;
0488     }
0489 
0490     hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
0491     hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
0492     tmp = (u64)htot * (u64)lane_byte_clk_kHz;
0493     hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
0494 
0495     /* all specified in byte-lane clocks */
0496     writel(hsa_time, base + VID_HSA_TIME);
0497     writel(hbp_time, base + VID_HBP_TIME);
0498     writel(hline_time, base + VID_HLINE_TIME);
0499 
0500     writel(vsw, base + VID_VSA_LINES);
0501     writel(vbp, base + VID_VBP_LINES);
0502     writel(vfp, base + VID_VFP_LINES);
0503     writel(mode->vdisplay, base + VID_VACTIVE_LINES);
0504     writel(mode->hdisplay, base + VID_PKT_SIZE);
0505 
0506     DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n",
0507              htot, hfp, hbp, hsw);
0508     DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n",
0509              vtot, vfp, vbp, vsw);
0510     DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n",
0511              hsa_time, hbp_time, hline_time);
0512 }
0513 
0514 static void dsi_set_video_mode(void __iomem *base, unsigned long flags)
0515 {
0516     u32 val;
0517     u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
0518         MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
0519     u32 non_burst_sync_pulse = MIPI_DSI_MODE_VIDEO |
0520         MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
0521     u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO;
0522 
0523     /*
0524      * choose video mode type
0525      */
0526     if ((flags & mode_mask) == non_burst_sync_pulse)
0527         val = DSI_NON_BURST_SYNC_PULSES;
0528     else if ((flags & mode_mask) == non_burst_sync_event)
0529         val = DSI_NON_BURST_SYNC_EVENTS;
0530     else
0531         val = DSI_BURST_SYNC_PULSES_1;
0532     writel(val, base + VID_MODE_CFG);
0533 
0534     writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL);
0535     writel(DSI_VIDEO_MODE, base + MODE_CFG);
0536 }
0537 
0538 static void dsi_mipi_init(struct dw_dsi *dsi)
0539 {
0540     struct dsi_hw_ctx *ctx = dsi->ctx;
0541     struct mipi_phy_params *phy = &dsi->phy;
0542     struct drm_display_mode *mode = &dsi->cur_mode;
0543     u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
0544     void __iomem *base = ctx->base;
0545     u32 dphy_req_kHz;
0546 
0547     /*
0548      * count phy params
0549      */
0550     dphy_req_kHz = mode->clock * bpp / dsi->lanes;
0551     dsi_get_phy_params(dphy_req_kHz, phy);
0552 
0553     /* reset Core */
0554     writel(RESET, base + PWR_UP);
0555 
0556     /* set dsi phy params */
0557     dsi_set_mipi_phy(base, phy, dsi->lanes);
0558 
0559     /* set dsi mode timing */
0560     dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format);
0561 
0562     /* set dsi video mode */
0563     dsi_set_video_mode(base, dsi->mode_flags);
0564 
0565     /* dsi wake up */
0566     writel(POWERUP, base + PWR_UP);
0567 
0568     DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n",
0569              dsi->lanes, mode->clock, phy->lane_byte_clk_kHz);
0570 }
0571 
0572 static void dsi_encoder_disable(struct drm_encoder *encoder)
0573 {
0574     struct dw_dsi *dsi = encoder_to_dsi(encoder);
0575     struct dsi_hw_ctx *ctx = dsi->ctx;
0576     void __iomem *base = ctx->base;
0577 
0578     if (!dsi->enable)
0579         return;
0580 
0581     writel(0, base + PWR_UP);
0582     writel(0, base + LPCLK_CTRL);
0583     writel(0, base + PHY_RSTZ);
0584     clk_disable_unprepare(ctx->pclk);
0585 
0586     dsi->enable = false;
0587 }
0588 
0589 static void dsi_encoder_enable(struct drm_encoder *encoder)
0590 {
0591     struct dw_dsi *dsi = encoder_to_dsi(encoder);
0592     struct dsi_hw_ctx *ctx = dsi->ctx;
0593     int ret;
0594 
0595     if (dsi->enable)
0596         return;
0597 
0598     ret = clk_prepare_enable(ctx->pclk);
0599     if (ret) {
0600         DRM_ERROR("fail to enable pclk: %d\n", ret);
0601         return;
0602     }
0603 
0604     dsi_mipi_init(dsi);
0605 
0606     dsi->enable = true;
0607 }
0608 
0609 static enum drm_mode_status dsi_encoder_phy_mode_valid(
0610                     struct drm_encoder *encoder,
0611                     const struct drm_display_mode *mode)
0612 {
0613     struct dw_dsi *dsi = encoder_to_dsi(encoder);
0614     struct mipi_phy_params phy;
0615     u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
0616     u32 req_kHz, act_kHz, lane_byte_clk_kHz;
0617 
0618     /* Calculate the lane byte clk using the adjusted mode clk */
0619     memset(&phy, 0, sizeof(phy));
0620     req_kHz = mode->clock * bpp / dsi->lanes;
0621     act_kHz = dsi_calc_phy_rate(req_kHz, &phy);
0622     lane_byte_clk_kHz = act_kHz / 8;
0623 
0624     DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...",
0625             mode->hdisplay, mode->vdisplay, bpp,
0626             drm_mode_vrefresh(mode), mode->clock);
0627 
0628     /*
0629      * Make sure the adjusted mode clock and the lane byte clk
0630      * have a common denominator base frequency
0631      */
0632     if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) {
0633         DRM_DEBUG_DRIVER("OK!\n");
0634         return MODE_OK;
0635     }
0636 
0637     DRM_DEBUG_DRIVER("BAD!\n");
0638     return MODE_BAD;
0639 }
0640 
0641 static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder,
0642                     const struct drm_display_mode *mode)
0643 
0644 {
0645     const struct drm_crtc_helper_funcs *crtc_funcs = NULL;
0646     struct drm_crtc *crtc = NULL;
0647     struct drm_display_mode adj_mode;
0648     enum drm_mode_status ret;
0649 
0650     /*
0651      * The crtc might adjust the mode, so go through the
0652      * possible crtcs (technically just one) and call
0653      * mode_fixup to figure out the adjusted mode before we
0654      * validate it.
0655      */
0656     drm_for_each_crtc(crtc, encoder->dev) {
0657         /*
0658          * reset adj_mode to the mode value each time,
0659          * so we don't adjust the mode twice
0660          */
0661         drm_mode_copy(&adj_mode, mode);
0662 
0663         crtc_funcs = crtc->helper_private;
0664         if (crtc_funcs && crtc_funcs->mode_fixup)
0665             if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode))
0666                 return MODE_BAD;
0667 
0668         ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode);
0669         if (ret != MODE_OK)
0670             return ret;
0671     }
0672     return MODE_OK;
0673 }
0674 
0675 static void dsi_encoder_mode_set(struct drm_encoder *encoder,
0676                  struct drm_display_mode *mode,
0677                  struct drm_display_mode *adj_mode)
0678 {
0679     struct dw_dsi *dsi = encoder_to_dsi(encoder);
0680 
0681     drm_mode_copy(&dsi->cur_mode, adj_mode);
0682 }
0683 
0684 static int dsi_encoder_atomic_check(struct drm_encoder *encoder,
0685                     struct drm_crtc_state *crtc_state,
0686                     struct drm_connector_state *conn_state)
0687 {
0688     /* do nothing */
0689     return 0;
0690 }
0691 
0692 static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = {
0693     .atomic_check   = dsi_encoder_atomic_check,
0694     .mode_valid = dsi_encoder_mode_valid,
0695     .mode_set   = dsi_encoder_mode_set,
0696     .enable     = dsi_encoder_enable,
0697     .disable    = dsi_encoder_disable
0698 };
0699 
0700 static int dw_drm_encoder_init(struct device *dev,
0701                    struct drm_device *drm_dev,
0702                    struct drm_encoder *encoder)
0703 {
0704     int ret;
0705     u32 crtc_mask = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
0706 
0707     if (!crtc_mask) {
0708         DRM_ERROR("failed to find crtc mask\n");
0709         return -EINVAL;
0710     }
0711 
0712     encoder->possible_crtcs = crtc_mask;
0713     ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
0714     if (ret) {
0715         DRM_ERROR("failed to init dsi encoder\n");
0716         return ret;
0717     }
0718 
0719     drm_encoder_helper_add(encoder, &dw_encoder_helper_funcs);
0720 
0721     return 0;
0722 }
0723 
0724 static const struct component_ops dsi_ops;
0725 static int dsi_host_attach(struct mipi_dsi_host *host,
0726                struct mipi_dsi_device *mdsi)
0727 {
0728     struct dw_dsi *dsi = host_to_dsi(host);
0729     struct device *dev = host->dev;
0730     int ret;
0731 
0732     if (mdsi->lanes < 1 || mdsi->lanes > 4) {
0733         DRM_ERROR("dsi device params invalid\n");
0734         return -EINVAL;
0735     }
0736 
0737     dsi->lanes = mdsi->lanes;
0738     dsi->format = mdsi->format;
0739     dsi->mode_flags = mdsi->mode_flags;
0740 
0741     ret = component_add(dev, &dsi_ops);
0742     if (ret)
0743         return ret;
0744 
0745     return 0;
0746 }
0747 
0748 static int dsi_host_detach(struct mipi_dsi_host *host,
0749                struct mipi_dsi_device *mdsi)
0750 {
0751     struct device *dev = host->dev;
0752 
0753     component_del(dev, &dsi_ops);
0754 
0755     return 0;
0756 }
0757 
0758 static const struct mipi_dsi_host_ops dsi_host_ops = {
0759     .attach = dsi_host_attach,
0760     .detach = dsi_host_detach,
0761 };
0762 
0763 static int dsi_host_init(struct device *dev, struct dw_dsi *dsi)
0764 {
0765     struct mipi_dsi_host *host = &dsi->host;
0766     int ret;
0767 
0768     host->dev = dev;
0769     host->ops = &dsi_host_ops;
0770     ret = mipi_dsi_host_register(host);
0771     if (ret) {
0772         DRM_ERROR("failed to register dsi host\n");
0773         return ret;
0774     }
0775 
0776     return 0;
0777 }
0778 
0779 static int dsi_bridge_init(struct drm_device *dev, struct dw_dsi *dsi)
0780 {
0781     struct drm_encoder *encoder = &dsi->encoder;
0782     struct drm_bridge *bridge;
0783     struct device_node *np = dsi->dev->of_node;
0784     int ret;
0785 
0786     /*
0787      * Get the endpoint node. In our case, dsi has one output port1
0788      * to which the external HDMI bridge is connected.
0789      */
0790     ret = drm_of_find_panel_or_bridge(np, 1, 0, NULL, &bridge);
0791     if (ret)
0792         return ret;
0793 
0794     /* associate the bridge to dsi encoder */
0795     return drm_bridge_attach(encoder, bridge, NULL, 0);
0796 }
0797 
0798 static int dsi_bind(struct device *dev, struct device *master, void *data)
0799 {
0800     struct dsi_data *ddata = dev_get_drvdata(dev);
0801     struct dw_dsi *dsi = &ddata->dsi;
0802     struct drm_device *drm_dev = data;
0803     int ret;
0804 
0805     ret = dw_drm_encoder_init(dev, drm_dev, &dsi->encoder);
0806     if (ret)
0807         return ret;
0808 
0809     ret = dsi_bridge_init(drm_dev, dsi);
0810     if (ret)
0811         return ret;
0812 
0813     return 0;
0814 }
0815 
0816 static void dsi_unbind(struct device *dev, struct device *master, void *data)
0817 {
0818     /* do nothing */
0819 }
0820 
0821 static const struct component_ops dsi_ops = {
0822     .bind   = dsi_bind,
0823     .unbind = dsi_unbind,
0824 };
0825 
0826 static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi)
0827 {
0828     struct dsi_hw_ctx *ctx = dsi->ctx;
0829     struct resource *res;
0830 
0831     ctx->pclk = devm_clk_get(&pdev->dev, "pclk");
0832     if (IS_ERR(ctx->pclk)) {
0833         DRM_ERROR("failed to get pclk clock\n");
0834         return PTR_ERR(ctx->pclk);
0835     }
0836 
0837     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0838     ctx->base = devm_ioremap_resource(&pdev->dev, res);
0839     if (IS_ERR(ctx->base)) {
0840         DRM_ERROR("failed to remap dsi io region\n");
0841         return PTR_ERR(ctx->base);
0842     }
0843 
0844     return 0;
0845 }
0846 
0847 static int dsi_probe(struct platform_device *pdev)
0848 {
0849     struct dsi_data *data;
0850     struct dw_dsi *dsi;
0851     struct dsi_hw_ctx *ctx;
0852     int ret;
0853 
0854     data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
0855     if (!data) {
0856         DRM_ERROR("failed to allocate dsi data.\n");
0857         return -ENOMEM;
0858     }
0859     dsi = &data->dsi;
0860     ctx = &data->ctx;
0861     dsi->ctx = ctx;
0862     dsi->dev = &pdev->dev;
0863 
0864     ret = dsi_parse_dt(pdev, dsi);
0865     if (ret)
0866         return ret;
0867 
0868     platform_set_drvdata(pdev, data);
0869 
0870     ret = dsi_host_init(&pdev->dev, dsi);
0871     if (ret)
0872         return ret;
0873 
0874     return 0;
0875 }
0876 
0877 static int dsi_remove(struct platform_device *pdev)
0878 {
0879     struct dsi_data *data = platform_get_drvdata(pdev);
0880     struct dw_dsi *dsi = &data->dsi;
0881 
0882     mipi_dsi_host_unregister(&dsi->host);
0883 
0884     return 0;
0885 }
0886 
0887 static const struct of_device_id dsi_of_match[] = {
0888     {.compatible = "hisilicon,hi6220-dsi"},
0889     { }
0890 };
0891 MODULE_DEVICE_TABLE(of, dsi_of_match);
0892 
0893 static struct platform_driver dsi_driver = {
0894     .probe = dsi_probe,
0895     .remove = dsi_remove,
0896     .driver = {
0897         .name = "dw-dsi",
0898         .of_match_table = dsi_of_match,
0899     },
0900 };
0901 
0902 module_platform_driver(dsi_driver);
0903 
0904 MODULE_AUTHOR("Xinliang Liu <xinliang.liu@linaro.org>");
0905 MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@hisilicon.com>");
0906 MODULE_AUTHOR("Xinwei Kong <kong.kongxinwei@hisilicon.com>");
0907 MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver");
0908 MODULE_LICENSE("GPL v2");
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