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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Hisilicon Hibmc SoC drm driver
0003  *
0004  * Based on the bochs drm driver.
0005  *
0006  * Copyright (c) 2016 Huawei Limited.
0007  *
0008  * Author:
0009  *  Rongrong Zou <zourongrong@huawei.com>
0010  *  Rongrong Zou <zourongrong@gmail.com>
0011  *  Jianhua Li <lijianhua@huawei.com>
0012  */
0013 
0014 #include <linux/delay.h>
0015 
0016 #include <drm/drm_atomic.h>
0017 #include <drm/drm_atomic_helper.h>
0018 #include <drm/drm_fourcc.h>
0019 #include <drm/drm_gem_vram_helper.h>
0020 #include <drm/drm_vblank.h>
0021 
0022 #include "hibmc_drm_drv.h"
0023 #include "hibmc_drm_regs.h"
0024 
0025 struct hibmc_display_panel_pll {
0026     u64 M;
0027     u64 N;
0028     u64 OD;
0029     u64 POD;
0030 };
0031 
0032 struct hibmc_dislay_pll_config {
0033     u64 hdisplay;
0034     u64 vdisplay;
0035     u32 pll1_config_value;
0036     u32 pll2_config_value;
0037 };
0038 
0039 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
0040     {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ},
0041     {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},
0042     {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},
0043     {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
0044     {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ},
0045     {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},
0046     {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
0047     {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
0048     {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ},
0049     {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
0050     {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},
0051     {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},
0052     {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},
0053 };
0054 
0055 static int hibmc_plane_atomic_check(struct drm_plane *plane,
0056                     struct drm_atomic_state *state)
0057 {
0058     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0059                                          plane);
0060     struct drm_framebuffer *fb = new_plane_state->fb;
0061     struct drm_crtc *crtc = new_plane_state->crtc;
0062     struct drm_crtc_state *crtc_state;
0063     u32 src_w = new_plane_state->src_w >> 16;
0064     u32 src_h = new_plane_state->src_h >> 16;
0065 
0066     if (!crtc || !fb)
0067         return 0;
0068 
0069     crtc_state = drm_atomic_get_crtc_state(state, crtc);
0070     if (IS_ERR(crtc_state))
0071         return PTR_ERR(crtc_state);
0072 
0073     if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) {
0074         drm_dbg_atomic(plane->dev, "scale not support\n");
0075         return -EINVAL;
0076     }
0077 
0078     if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0) {
0079         drm_dbg_atomic(plane->dev, "crtc_x/y of drm_plane state is invalid\n");
0080         return -EINVAL;
0081     }
0082 
0083     if (!crtc_state->enable)
0084         return 0;
0085 
0086     if (new_plane_state->crtc_x + new_plane_state->crtc_w >
0087         crtc_state->adjusted_mode.hdisplay ||
0088         new_plane_state->crtc_y + new_plane_state->crtc_h >
0089         crtc_state->adjusted_mode.vdisplay) {
0090         drm_dbg_atomic(plane->dev, "visible portion of plane is invalid\n");
0091         return -EINVAL;
0092     }
0093 
0094     if (new_plane_state->fb->pitches[0] % 128 != 0) {
0095         drm_dbg_atomic(plane->dev, "wrong stride with 128-byte aligned\n");
0096         return -EINVAL;
0097     }
0098     return 0;
0099 }
0100 
0101 static void hibmc_plane_atomic_update(struct drm_plane *plane,
0102                       struct drm_atomic_state *state)
0103 {
0104     struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
0105                                        plane);
0106     u32 reg;
0107     s64 gpu_addr = 0;
0108     u32 line_l;
0109     struct hibmc_drm_private *priv = to_hibmc_drm_private(plane->dev);
0110     struct drm_gem_vram_object *gbo;
0111 
0112     if (!new_state->fb)
0113         return;
0114 
0115     gbo = drm_gem_vram_of_gem(new_state->fb->obj[0]);
0116 
0117     gpu_addr = drm_gem_vram_offset(gbo);
0118     if (WARN_ON_ONCE(gpu_addr < 0))
0119         return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
0120 
0121     writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
0122 
0123     reg = new_state->fb->width * (new_state->fb->format->cpp[0]);
0124 
0125     line_l = new_state->fb->pitches[0];
0126     writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
0127            HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),
0128            priv->mmio + HIBMC_CRT_FB_WIDTH);
0129 
0130     /* SET PIXEL FORMAT */
0131     reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
0132     reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK;
0133     reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,
0134                new_state->fb->format->cpp[0] * 8 / 16);
0135     writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
0136 }
0137 
0138 static const u32 channel_formats1[] = {
0139     DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
0140     DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
0141     DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
0142     DRM_FORMAT_ABGR8888
0143 };
0144 
0145 static const struct drm_plane_funcs hibmc_plane_funcs = {
0146     .update_plane   = drm_atomic_helper_update_plane,
0147     .disable_plane  = drm_atomic_helper_disable_plane,
0148     .destroy = drm_plane_cleanup,
0149     .reset = drm_atomic_helper_plane_reset,
0150     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
0151     .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
0152 };
0153 
0154 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = {
0155     DRM_GEM_VRAM_PLANE_HELPER_FUNCS,
0156     .atomic_check = hibmc_plane_atomic_check,
0157     .atomic_update = hibmc_plane_atomic_update,
0158 };
0159 
0160 static void hibmc_crtc_dpms(struct drm_crtc *crtc, u32 dpms)
0161 {
0162     struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev);
0163     u32 reg;
0164 
0165     reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
0166     reg &= ~HIBMC_CRT_DISP_CTL_DPMS_MASK;
0167     reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms);
0168     reg &= ~HIBMC_CRT_DISP_CTL_TIMING_MASK;
0169     if (dpms == HIBMC_CRT_DPMS_ON)
0170         reg |= HIBMC_CRT_DISP_CTL_TIMING(1);
0171     writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
0172 }
0173 
0174 static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc,
0175                      struct drm_atomic_state *state)
0176 {
0177     u32 reg;
0178     struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev);
0179 
0180     hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
0181 
0182     /* Enable display power gate & LOCALMEM power gate*/
0183     reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
0184     reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
0185     reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
0186     reg |= HIBMC_CURR_GATE_LOCALMEM(1);
0187     reg |= HIBMC_CURR_GATE_DISPLAY(1);
0188     hibmc_set_current_gate(priv, reg);
0189     drm_crtc_vblank_on(crtc);
0190     hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_ON);
0191 }
0192 
0193 static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc,
0194                       struct drm_atomic_state *state)
0195 {
0196     u32 reg;
0197     struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev);
0198 
0199     hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_OFF);
0200     drm_crtc_vblank_off(crtc);
0201 
0202     hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP);
0203 
0204     /* Enable display power gate & LOCALMEM power gate*/
0205     reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
0206     reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
0207     reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
0208     reg |= HIBMC_CURR_GATE_LOCALMEM(0);
0209     reg |= HIBMC_CURR_GATE_DISPLAY(0);
0210     hibmc_set_current_gate(priv, reg);
0211 }
0212 
0213 static enum drm_mode_status
0214 hibmc_crtc_mode_valid(struct drm_crtc *crtc,
0215               const struct drm_display_mode *mode)
0216 {
0217     size_t i = 0;
0218     int vrefresh = drm_mode_vrefresh(mode);
0219 
0220     if (vrefresh < 59 || vrefresh > 61)
0221         return MODE_NOCLOCK;
0222 
0223     for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) {
0224         if (hibmc_pll_table[i].hdisplay == mode->hdisplay &&
0225             hibmc_pll_table[i].vdisplay == mode->vdisplay)
0226             return MODE_OK;
0227     }
0228 
0229     return MODE_BAD;
0230 }
0231 
0232 static u32 format_pll_reg(void)
0233 {
0234     u32 pllreg = 0;
0235     struct hibmc_display_panel_pll pll = {0};
0236 
0237     /*
0238      * Note that all PLL's have the same format. Here,
0239      * we just use Panel PLL parameter to work out the bit
0240      * fields in the register.On returning a 32 bit number, the value can
0241      * be applied to any PLL in the calling function.
0242      */
0243     pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);
0244     pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);
0245     pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);
0246     pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);
0247     pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);
0248     pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);
0249     pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);
0250 
0251     return pllreg;
0252 }
0253 
0254 static void set_vclock_hisilicon(struct drm_device *dev, u64 pll)
0255 {
0256     u32 val;
0257     struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
0258 
0259     val = readl(priv->mmio + CRT_PLL1_HS);
0260     val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1));
0261     writel(val, priv->mmio + CRT_PLL1_HS);
0262 
0263     val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1);
0264     writel(val, priv->mmio + CRT_PLL1_HS);
0265 
0266     writel(pll, priv->mmio + CRT_PLL1_HS);
0267 
0268     usleep_range(1000, 2000);
0269 
0270     val = pll & ~(CRT_PLL1_HS_POWERON(1));
0271     writel(val, priv->mmio + CRT_PLL1_HS);
0272 
0273     usleep_range(1000, 2000);
0274 
0275     val &= ~(CRT_PLL1_HS_INTER_BYPASS(1));
0276     writel(val, priv->mmio + CRT_PLL1_HS);
0277 
0278     usleep_range(1000, 2000);
0279 
0280     val |= CRT_PLL1_HS_OUTER_BYPASS(1);
0281     writel(val, priv->mmio + CRT_PLL1_HS);
0282 }
0283 
0284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2)
0285 {
0286     size_t i;
0287     size_t count = ARRAY_SIZE(hibmc_pll_table);
0288 
0289     for (i = 0; i < count; i++) {
0290         if (hibmc_pll_table[i].hdisplay == x &&
0291             hibmc_pll_table[i].vdisplay == y) {
0292             *pll1 = hibmc_pll_table[i].pll1_config_value;
0293             *pll2 = hibmc_pll_table[i].pll2_config_value;
0294             return;
0295         }
0296     }
0297 
0298     /* if found none, we use default value */
0299     *pll1 = CRT_PLL1_HS_25MHZ;
0300     *pll2 = CRT_PLL2_HS_25MHZ;
0301 }
0302 
0303 /*
0304  * This function takes care the extra registers and bit fields required to
0305  * setup a mode in board.
0306  * Explanation about Display Control register:
0307  * FPGA only supports 7 predefined pixel clocks, and clock select is
0308  * in bit 4:0 of new register 0x802a8.
0309  */
0310 static u32 display_ctrl_adjust(struct drm_device *dev,
0311                    struct drm_display_mode *mode,
0312                    u32 ctrl)
0313 {
0314     u64 x, y;
0315     u32 pll1; /* bit[31:0] of PLL */
0316     u32 pll2; /* bit[63:32] of PLL */
0317     struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
0318 
0319     x = mode->hdisplay;
0320     y = mode->vdisplay;
0321 
0322     get_pll_config(x, y, &pll1, &pll2);
0323     writel(pll2, priv->mmio + CRT_PLL2_HS);
0324     set_vclock_hisilicon(dev, pll1);
0325 
0326     /*
0327      * Hisilicon has to set up the top-left and bottom-right
0328      * registers as well.
0329      * Note that normal chip only use those two register for
0330      * auto-centering mode.
0331      */
0332     writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |
0333            HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),
0334            priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL);
0335 
0336     writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |
0337            HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),
0338            priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR);
0339 
0340     /*
0341      * Assume common fields in ctrl have been properly set before
0342      * calling this function.
0343      * This function only sets the extra fields in ctrl.
0344      */
0345 
0346     /* Set bit 25 of display controller: Select CRT or VGA clock */
0347     ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK;
0348     ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK;
0349 
0350     ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT);
0351 
0352     /* clock_phase_polarity is 0 */
0353     ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0);
0354 
0355     writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL);
0356 
0357     return ctrl;
0358 }
0359 
0360 static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc)
0361 {
0362     u32 val;
0363     struct drm_display_mode *mode = &crtc->state->mode;
0364     struct drm_device *dev = crtc->dev;
0365     struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
0366     u32 width = mode->hsync_end - mode->hsync_start;
0367     u32 height = mode->vsync_end - mode->vsync_start;
0368 
0369     writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL);
0370     writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |
0371            HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),
0372            priv->mmio + HIBMC_CRT_HORZ_TOTAL);
0373 
0374     writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |
0375            HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),
0376            priv->mmio + HIBMC_CRT_HORZ_SYNC);
0377 
0378     writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |
0379            HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),
0380            priv->mmio + HIBMC_CRT_VERT_TOTAL);
0381 
0382     writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |
0383            HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),
0384            priv->mmio + HIBMC_CRT_VERT_SYNC);
0385 
0386     val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);
0387     val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);
0388     val |= HIBMC_CRT_DISP_CTL_TIMING(1);
0389     val |= HIBMC_CRT_DISP_CTL_PLANE(1);
0390 
0391     display_ctrl_adjust(dev, mode, val);
0392 }
0393 
0394 static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc,
0395                     struct drm_atomic_state *state)
0396 {
0397     u32 reg;
0398     struct drm_device *dev = crtc->dev;
0399     struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
0400 
0401     hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
0402 
0403     /* Enable display power gate & LOCALMEM power gate*/
0404     reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
0405     reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
0406     reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
0407     reg |= HIBMC_CURR_GATE_DISPLAY(1);
0408     reg |= HIBMC_CURR_GATE_LOCALMEM(1);
0409     hibmc_set_current_gate(priv, reg);
0410 
0411     /* We can add more initialization as needed. */
0412 }
0413 
0414 static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc,
0415                     struct drm_atomic_state *state)
0416 
0417 {
0418     unsigned long flags;
0419 
0420     spin_lock_irqsave(&crtc->dev->event_lock, flags);
0421     if (crtc->state->event)
0422         drm_crtc_send_vblank_event(crtc, crtc->state->event);
0423     crtc->state->event = NULL;
0424     spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
0425 }
0426 
0427 static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc)
0428 {
0429     struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev);
0430 
0431     writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1),
0432            priv->mmio + HIBMC_RAW_INTERRUPT_EN);
0433 
0434     return 0;
0435 }
0436 
0437 static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc)
0438 {
0439     struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev);
0440 
0441     writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0),
0442            priv->mmio + HIBMC_RAW_INTERRUPT_EN);
0443 }
0444 
0445 static void hibmc_crtc_load_lut(struct drm_crtc *crtc)
0446 {
0447     struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev);
0448     void __iomem   *mmio = priv->mmio;
0449     u16 *r, *g, *b;
0450     u32 reg;
0451     u32 i;
0452 
0453     r = crtc->gamma_store;
0454     g = r + crtc->gamma_size;
0455     b = g + crtc->gamma_size;
0456 
0457     for (i = 0; i < crtc->gamma_size; i++) {
0458         u32 offset = i << 2;
0459         u8 red = *r++ >> 8;
0460         u8 green = *g++ >> 8;
0461         u8 blue = *b++ >> 8;
0462         u32 rgb = (red << 16) | (green << 8) | blue;
0463 
0464         writel(rgb, mmio + HIBMC_CRT_PALETTE + offset);
0465     }
0466 
0467     reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
0468     reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1);
0469     writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
0470 }
0471 
0472 static int hibmc_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
0473                 u16 *blue, uint32_t size,
0474                 struct drm_modeset_acquire_ctx *ctx)
0475 {
0476     hibmc_crtc_load_lut(crtc);
0477 
0478     return 0;
0479 }
0480 
0481 static const struct drm_crtc_funcs hibmc_crtc_funcs = {
0482     .page_flip = drm_atomic_helper_page_flip,
0483     .set_config = drm_atomic_helper_set_config,
0484     .destroy = drm_crtc_cleanup,
0485     .reset = drm_atomic_helper_crtc_reset,
0486     .atomic_duplicate_state =  drm_atomic_helper_crtc_duplicate_state,
0487     .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
0488     .enable_vblank = hibmc_crtc_enable_vblank,
0489     .disable_vblank = hibmc_crtc_disable_vblank,
0490     .gamma_set = hibmc_crtc_gamma_set,
0491 };
0492 
0493 static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = {
0494     .mode_set_nofb  = hibmc_crtc_mode_set_nofb,
0495     .atomic_begin   = hibmc_crtc_atomic_begin,
0496     .atomic_flush   = hibmc_crtc_atomic_flush,
0497     .atomic_enable  = hibmc_crtc_atomic_enable,
0498     .atomic_disable = hibmc_crtc_atomic_disable,
0499     .mode_valid = hibmc_crtc_mode_valid,
0500 };
0501 
0502 int hibmc_de_init(struct hibmc_drm_private *priv)
0503 {
0504     struct drm_device *dev = &priv->dev;
0505     struct drm_crtc *crtc = &priv->crtc;
0506     struct drm_plane *plane = &priv->primary_plane;
0507     int ret;
0508 
0509     ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs,
0510                        channel_formats1,
0511                        ARRAY_SIZE(channel_formats1),
0512                        NULL,
0513                        DRM_PLANE_TYPE_PRIMARY,
0514                        NULL);
0515 
0516     if (ret) {
0517         drm_err(dev, "failed to init plane: %d\n", ret);
0518         return ret;
0519     }
0520 
0521     drm_plane_helper_add(plane, &hibmc_plane_helper_funcs);
0522 
0523     ret = drm_crtc_init_with_planes(dev, crtc, plane,
0524                     NULL, &hibmc_crtc_funcs, NULL);
0525     if (ret) {
0526         drm_err(dev, "failed to init crtc: %d\n", ret);
0527         return ret;
0528     }
0529 
0530     ret = drm_mode_crtc_set_gamma_size(crtc, 256);
0531     if (ret) {
0532         drm_err(dev, "failed to set gamma size: %d\n", ret);
0533         return ret;
0534     }
0535     drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs);
0536 
0537     return 0;
0538 }
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