drm/gud/gud_internal.h

0001 /* SPDX-License-Identifier: MIT */
0002
0003 #ifndef __LINUX_GUD_INTERNAL_H
0004 #define __LINUX_GUD_INTERNAL_H
0005
0006 #include <linux/list.h>
0007 #include <linux/mutex.h>
0008 #include <linux/scatterlist.h>
0009 #include <linux/usb.h>
0010 #include <linux/workqueue.h>
0011 #include <uapi/drm/drm_fourcc.h>
0012
0013 #include <drm/drm_modes.h>
0014 #include <drm/drm_simple_kms_helper.h>
0015
0016 struct gud_device {
0017     struct drm_device drm;
0018     struct drm_simple_display_pipe pipe;
0019     struct device *dmadev;
0020     struct work_struct work;
0021     u32 flags;
0022     const struct drm_format_info *xrgb8888_emulation_format;
0023
0024     u16 *properties;
0025     unsigned int num_properties;
0026
0027     unsigned int bulk_pipe;
0028     void *bulk_buf;
0029     size_t bulk_len;
0030     struct sg_table bulk_sgt;
0031
0032     u8 compression;
0033     void *lz4_comp_mem;
0034     void *compress_buf;
0035
0036     u64 stats_length;
0037     u64 stats_actual_length;
0038     unsigned int stats_num_errors;
0039
0040     struct mutex ctrl_lock; /* Serialize get/set and status transfers */
0041
0042     struct mutex damage_lock; /* Protects the following members: */
0043     struct drm_framebuffer *fb;
0044     struct drm_rect damage;
0045     bool prev_flush_failed;
0046 };
0047
0048 static inline struct gud_device *to_gud_device(struct drm_device *drm)
0049 {
0050     return container_of(drm, struct gud_device, drm);
0051 }
0052
0053 static inline struct usb_device *gud_to_usb_device(struct gud_device *gdrm)
0054 {
0055     return interface_to_usbdev(to_usb_interface(gdrm->drm.dev));
0056 }
0057
0058 int gud_usb_get(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t len);
0059 int gud_usb_set(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t len);
0060 int gud_usb_get_u8(struct gud_device *gdrm, u8 request, u16 index, u8 *val);
0061 int gud_usb_set_u8(struct gud_device *gdrm, u8 request, u8 val);
0062
0063 void gud_clear_damage(struct gud_device *gdrm);
0064 void gud_flush_work(struct work_struct *work);
0065 int gud_pipe_check(struct drm_simple_display_pipe *pipe,
0066            struct drm_plane_state *new_plane_state,
0067            struct drm_crtc_state *new_crtc_state);
0068 void gud_pipe_update(struct drm_simple_display_pipe *pipe,
0069              struct drm_plane_state *old_state);
0070 int gud_connector_fill_properties(struct drm_connector_state *connector_state,
0071                   struct gud_property_req *properties);
0072 int gud_get_connectors(struct gud_device *gdrm);
0073
0074 /* Driver internal fourcc transfer formats */
0075 #define GUD_DRM_FORMAT_R1       0x00000122
0076 #define GUD_DRM_FORMAT_XRGB1111     0x03121722
0077
0078 static inline u8 gud_from_fourcc(u32 fourcc)
0079 {
0080     switch (fourcc) {
0081     case GUD_DRM_FORMAT_R1:
0082         return GUD_PIXEL_FORMAT_R1;
0083     case DRM_FORMAT_R8:
0084         return GUD_PIXEL_FORMAT_R8;
0085     case GUD_DRM_FORMAT_XRGB1111:
0086         return GUD_PIXEL_FORMAT_XRGB1111;
0087     case DRM_FORMAT_RGB332:
0088         return GUD_PIXEL_FORMAT_RGB332;
0089     case DRM_FORMAT_RGB565:
0090         return GUD_PIXEL_FORMAT_RGB565;
0091     case DRM_FORMAT_RGB888:
0092         return GUD_PIXEL_FORMAT_RGB888;
0093     case DRM_FORMAT_XRGB8888:
0094         return GUD_PIXEL_FORMAT_XRGB8888;
0095     case DRM_FORMAT_ARGB8888:
0096         return GUD_PIXEL_FORMAT_ARGB8888;
0097     }
0098
0099     return 0;
0100 }
0101
0102 static inline u32 gud_to_fourcc(u8 format)
0103 {
0104     switch (format) {
0105     case GUD_PIXEL_FORMAT_R1:
0106         return GUD_DRM_FORMAT_R1;
0107     case GUD_PIXEL_FORMAT_R8:
0108         return DRM_FORMAT_R8;
0109     case GUD_PIXEL_FORMAT_XRGB1111:
0110         return GUD_DRM_FORMAT_XRGB1111;
0111     case GUD_PIXEL_FORMAT_RGB332:
0112         return DRM_FORMAT_RGB332;
0113     case GUD_PIXEL_FORMAT_RGB565:
0114         return DRM_FORMAT_RGB565;
0115     case GUD_PIXEL_FORMAT_RGB888:
0116         return DRM_FORMAT_RGB888;
0117     case GUD_PIXEL_FORMAT_XRGB8888:
0118         return DRM_FORMAT_XRGB8888;
0119     case GUD_PIXEL_FORMAT_ARGB8888:
0120         return DRM_FORMAT_ARGB8888;
0121     }
0122
0123     return 0;
0124 }
0125
0126 static inline void gud_from_display_mode(struct gud_display_mode_req *dst,
0127                      const struct drm_display_mode *src)
0128 {
0129     u32 flags = src->flags & GUD_DISPLAY_MODE_FLAG_USER_MASK;
0130
0131     if (src->type & DRM_MODE_TYPE_PREFERRED)
0132         flags |= GUD_DISPLAY_MODE_FLAG_PREFERRED;
0133
0134     dst->clock = cpu_to_le32(src->clock);
0135     dst->hdisplay = cpu_to_le16(src->hdisplay);
0136     dst->hsync_start = cpu_to_le16(src->hsync_start);
0137     dst->hsync_end = cpu_to_le16(src->hsync_end);
0138     dst->htotal = cpu_to_le16(src->htotal);
0139     dst->vdisplay = cpu_to_le16(src->vdisplay);
0140     dst->vsync_start = cpu_to_le16(src->vsync_start);
0141     dst->vsync_end = cpu_to_le16(src->vsync_end);
0142     dst->vtotal = cpu_to_le16(src->vtotal);
0143     dst->flags = cpu_to_le32(flags);
0144 }
0145
0146 static inline void gud_to_display_mode(struct drm_display_mode *dst,
0147                        const struct gud_display_mode_req *src)
0148 {
0149     u32 flags = le32_to_cpu(src->flags);
0150
0151     memset(dst, 0, sizeof(*dst));
0152     dst->clock = le32_to_cpu(src->clock);
0153     dst->hdisplay = le16_to_cpu(src->hdisplay);
0154     dst->hsync_start = le16_to_cpu(src->hsync_start);
0155     dst->hsync_end = le16_to_cpu(src->hsync_end);
0156     dst->htotal = le16_to_cpu(src->htotal);
0157     dst->vdisplay = le16_to_cpu(src->vdisplay);
0158     dst->vsync_start = le16_to_cpu(src->vsync_start);
0159     dst->vsync_end = le16_to_cpu(src->vsync_end);
0160     dst->vtotal = le16_to_cpu(src->vtotal);
0161     dst->flags = flags & GUD_DISPLAY_MODE_FLAG_USER_MASK;
0162     dst->type = DRM_MODE_TYPE_DRIVER;
0163     if (flags & GUD_DISPLAY_MODE_FLAG_PREFERRED)
0164         dst->type |= DRM_MODE_TYPE_PREFERRED;
0165     drm_mode_set_name(dst);
0166 }
0167
0168 #endif