drm/gma500/psb_irq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /**************************************************************************
0003  * Copyright (c) 2007, Intel Corporation.
0004  * All Rights Reserved.
0005  *
0006  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
0007  * develop this driver.
0008  *
0009  **************************************************************************/
0010
0011 #include <drm/drm_drv.h>
0012 #include <drm/drm_vblank.h>
0013
0014 #include "power.h"
0015 #include "psb_drv.h"
0016 #include "psb_intel_reg.h"
0017 #include "psb_irq.h"
0018 #include "psb_reg.h"
0019
0020 /*
0021  * inline functions
0022  */
0023
0024 static inline u32 gma_pipestat(int pipe)
0025 {
0026     if (pipe == 0)
0027         return PIPEASTAT;
0028     if (pipe == 1)
0029         return PIPEBSTAT;
0030     if (pipe == 2)
0031         return PIPECSTAT;
0032     BUG();
0033 }
0034
0035 static inline u32 gma_pipe_event(int pipe)
0036 {
0037     if (pipe == 0)
0038         return _PSB_PIPEA_EVENT_FLAG;
0039     if (pipe == 1)
0040         return _MDFLD_PIPEB_EVENT_FLAG;
0041     if (pipe == 2)
0042         return _MDFLD_PIPEC_EVENT_FLAG;
0043     BUG();
0044 }
0045
0046 static inline u32 gma_pipeconf(int pipe)
0047 {
0048     if (pipe == 0)
0049         return PIPEACONF;
0050     if (pipe == 1)
0051         return PIPEBCONF;
0052     if (pipe == 2)
0053         return PIPECCONF;
0054     BUG();
0055 }
0056
0057 void gma_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
0058 {
0059     if ((dev_priv->pipestat[pipe] & mask) != mask) {
0060         u32 reg = gma_pipestat(pipe);
0061         dev_priv->pipestat[pipe] |= mask;
0062         /* Enable the interrupt, clear any pending status */
0063         if (gma_power_begin(&dev_priv->dev, false)) {
0064             u32 writeVal = PSB_RVDC32(reg);
0065             writeVal |= (mask | (mask >> 16));
0066             PSB_WVDC32(writeVal, reg);
0067             (void) PSB_RVDC32(reg);
0068             gma_power_end(&dev_priv->dev);
0069         }
0070     }
0071 }
0072
0073 void gma_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
0074 {
0075     if ((dev_priv->pipestat[pipe] & mask) != 0) {
0076         u32 reg = gma_pipestat(pipe);
0077         dev_priv->pipestat[pipe] &= ~mask;
0078         if (gma_power_begin(&dev_priv->dev, false)) {
0079             u32 writeVal = PSB_RVDC32(reg);
0080             writeVal &= ~mask;
0081             PSB_WVDC32(writeVal, reg);
0082             (void) PSB_RVDC32(reg);
0083             gma_power_end(&dev_priv->dev);
0084         }
0085     }
0086 }
0087
0088 /*
0089  * Display controller interrupt handler for pipe event.
0090  */
0091 static void gma_pipe_event_handler(struct drm_device *dev, int pipe)
0092 {
0093     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0094
0095     uint32_t pipe_stat_val = 0;
0096     uint32_t pipe_stat_reg = gma_pipestat(pipe);
0097     uint32_t pipe_enable = dev_priv->pipestat[pipe];
0098     uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
0099     uint32_t pipe_clear;
0100     uint32_t i = 0;
0101
0102     spin_lock(&dev_priv->irqmask_lock);
0103
0104     pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
0105     pipe_stat_val &= pipe_enable | pipe_status;
0106     pipe_stat_val &= pipe_stat_val >> 16;
0107
0108     spin_unlock(&dev_priv->irqmask_lock);
0109
0110     /* Clear the 2nd level interrupt status bits
0111      * Sometimes the bits are very sticky so we repeat until they unstick */
0112     for (i = 0; i < 0xffff; i++) {
0113         PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
0114         pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
0115
0116         if (pipe_clear == 0)
0117             break;
0118     }
0119
0120     if (pipe_clear)
0121         dev_err(dev->dev,
0122         "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
0123         __func__, pipe, PSB_RVDC32(pipe_stat_reg));
0124
0125     if (pipe_stat_val & PIPE_VBLANK_STATUS) {
0126         struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
0127         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0128         unsigned long flags;
0129
0130         drm_handle_vblank(dev, pipe);
0131
0132         spin_lock_irqsave(&dev->event_lock, flags);
0133         if (gma_crtc->page_flip_event) {
0134             drm_crtc_send_vblank_event(crtc,
0135                            gma_crtc->page_flip_event);
0136             gma_crtc->page_flip_event = NULL;
0137             drm_crtc_vblank_put(crtc);
0138         }
0139         spin_unlock_irqrestore(&dev->event_lock, flags);
0140     }
0141 }
0142
0143 /*
0144  * Display controller interrupt handler.
0145  */
0146 static void gma_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
0147 {
0148     if (vdc_stat & _PSB_IRQ_ASLE)
0149         psb_intel_opregion_asle_intr(dev);
0150
0151     if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
0152         gma_pipe_event_handler(dev, 0);
0153
0154     if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
0155         gma_pipe_event_handler(dev, 1);
0156 }
0157
0158 /*
0159  * SGX interrupt handler
0160  */
0161 static void gma_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
0162 {
0163     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0164     u32 val, addr;
0165
0166     if (stat_1 & _PSB_CE_TWOD_COMPLETE)
0167         val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
0168
0169     if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
0170         val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
0171         addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
0172         if (val) {
0173             if (val & _PSB_CBI_STAT_PF_N_RW)
0174                 DRM_ERROR("SGX MMU page fault:");
0175             else
0176                 DRM_ERROR("SGX MMU read / write protection fault:");
0177
0178             if (val & _PSB_CBI_STAT_FAULT_CACHE)
0179                 DRM_ERROR("\tCache requestor");
0180             if (val & _PSB_CBI_STAT_FAULT_TA)
0181                 DRM_ERROR("\tTA requestor");
0182             if (val & _PSB_CBI_STAT_FAULT_VDM)
0183                 DRM_ERROR("\tVDM requestor");
0184             if (val & _PSB_CBI_STAT_FAULT_2D)
0185                 DRM_ERROR("\t2D requestor");
0186             if (val & _PSB_CBI_STAT_FAULT_PBE)
0187                 DRM_ERROR("\tPBE requestor");
0188             if (val & _PSB_CBI_STAT_FAULT_TSP)
0189                 DRM_ERROR("\tTSP requestor");
0190             if (val & _PSB_CBI_STAT_FAULT_ISP)
0191                 DRM_ERROR("\tISP requestor");
0192             if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
0193                 DRM_ERROR("\tUSSEPDS requestor");
0194             if (val & _PSB_CBI_STAT_FAULT_HOST)
0195                 DRM_ERROR("\tHost requestor");
0196
0197             DRM_ERROR("\tMMU failing address is 0x%08x.\n",
0198                   (unsigned int)addr);
0199         }
0200     }
0201
0202     /* Clear bits */
0203     PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
0204     PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
0205     PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
0206 }
0207
0208 static irqreturn_t gma_irq_handler(int irq, void *arg)
0209 {
0210     struct drm_device *dev = arg;
0211     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0212     uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
0213     u32 sgx_stat_1, sgx_stat_2;
0214     int handled = 0;
0215
0216     spin_lock(&dev_priv->irqmask_lock);
0217
0218     vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
0219
0220     if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
0221         dsp_int = 1;
0222
0223     if (vdc_stat & _PSB_IRQ_SGX_FLAG)
0224         sgx_int = 1;
0225     if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
0226         hotplug_int = 1;
0227
0228     vdc_stat &= dev_priv->vdc_irq_mask;
0229     spin_unlock(&dev_priv->irqmask_lock);
0230
0231     if (dsp_int && gma_power_is_on(dev)) {
0232         gma_vdc_interrupt(dev, vdc_stat);
0233         handled = 1;
0234     }
0235
0236     if (sgx_int) {
0237         sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
0238         sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
0239         gma_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
0240         handled = 1;
0241     }
0242
0243     /* Note: this bit has other meanings on some devices, so we will
0244        need to address that later if it ever matters */
0245     if (hotplug_int && dev_priv->ops->hotplug) {
0246         handled = dev_priv->ops->hotplug(dev);
0247         REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
0248     }
0249
0250     PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
0251     (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
0252     rmb();
0253
0254     if (!handled)
0255         return IRQ_NONE;
0256
0257     return IRQ_HANDLED;
0258 }
0259
0260 void gma_irq_preinstall(struct drm_device *dev)
0261 {
0262     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0263     unsigned long irqflags;
0264
0265     spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
0266
0267     if (gma_power_is_on(dev)) {
0268         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
0269         PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
0270         PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
0271         PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
0272         PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
0273     }
0274     if (dev->vblank[0].enabled)
0275         dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
0276     if (dev->vblank[1].enabled)
0277         dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
0278
0279     /* Revisit this area - want per device masks ? */
0280     if (dev_priv->ops->hotplug)
0281         dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
0282     dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
0283
0284     /* This register is safe even if display island is off */
0285     PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
0286     spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
0287 }
0288
0289 void gma_irq_postinstall(struct drm_device *dev)
0290 {
0291     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0292     unsigned long irqflags;
0293     unsigned int i;
0294
0295     spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
0296
0297     /* Enable 2D and MMU fault interrupts */
0298     PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
0299     PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
0300     PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
0301
0302     /* This register is safe even if display island is off */
0303     PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
0304     PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
0305
0306     for (i = 0; i < dev->num_crtcs; ++i) {
0307         if (dev->vblank[i].enabled)
0308             gma_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
0309         else
0310             gma_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
0311     }
0312
0313     if (dev_priv->ops->hotplug_enable)
0314         dev_priv->ops->hotplug_enable(dev, true);
0315
0316     spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
0317 }
0318
0319 int gma_irq_install(struct drm_device *dev)
0320 {
0321     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0322     struct pci_dev *pdev = to_pci_dev(dev->dev);
0323     int ret;
0324
0325     if (dev_priv->use_msi && pci_enable_msi(pdev)) {
0326         dev_warn(dev->dev, "Enabling MSI failed!\n");
0327         dev_priv->use_msi = false;
0328     }
0329
0330     if (pdev->irq == IRQ_NOTCONNECTED)
0331         return -ENOTCONN;
0332
0333     gma_irq_preinstall(dev);
0334
0335     /* PCI devices require shared interrupts. */
0336     ret = request_irq(pdev->irq, gma_irq_handler, IRQF_SHARED, dev->driver->name, dev);
0337     if (ret)
0338         return ret;
0339
0340     gma_irq_postinstall(dev);
0341
0342     return 0;
0343 }
0344
0345 void gma_irq_uninstall(struct drm_device *dev)
0346 {
0347     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0348     struct pci_dev *pdev = to_pci_dev(dev->dev);
0349     unsigned long irqflags;
0350     unsigned int i;
0351
0352     spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
0353
0354     if (dev_priv->ops->hotplug_enable)
0355         dev_priv->ops->hotplug_enable(dev, false);
0356
0357     PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
0358
0359     for (i = 0; i < dev->num_crtcs; ++i) {
0360         if (dev->vblank[i].enabled)
0361             gma_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
0362     }
0363
0364     dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
0365                   _PSB_IRQ_MSVDX_FLAG |
0366                   _LNC_IRQ_TOPAZ_FLAG;
0367
0368     /* These two registers are safe even if display island is off */
0369     PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
0370     PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
0371
0372     wmb();
0373
0374     /* This register is safe even if display island is off */
0375     PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
0376     spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
0377
0378     free_irq(pdev->irq, dev);
0379     if (dev_priv->use_msi)
0380         pci_disable_msi(pdev);
0381 }
0382
0383 int gma_crtc_enable_vblank(struct drm_crtc *crtc)
0384 {
0385     struct drm_device *dev = crtc->dev;
0386     unsigned int pipe = crtc->index;
0387     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0388     unsigned long irqflags;
0389     uint32_t reg_val = 0;
0390     uint32_t pipeconf_reg = gma_pipeconf(pipe);
0391
0392     if (gma_power_begin(dev, false)) {
0393         reg_val = REG_READ(pipeconf_reg);
0394         gma_power_end(dev);
0395     }
0396
0397     if (!(reg_val & PIPEACONF_ENABLE))
0398         return -EINVAL;
0399
0400     spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
0401
0402     if (pipe == 0)
0403         dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
0404     else if (pipe == 1)
0405         dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
0406
0407     PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
0408     PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
0409     gma_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
0410
0411     spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
0412
0413     return 0;
0414 }
0415
0416 void gma_crtc_disable_vblank(struct drm_crtc *crtc)
0417 {
0418     struct drm_device *dev = crtc->dev;
0419     unsigned int pipe = crtc->index;
0420     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0421     unsigned long irqflags;
0422
0423     spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
0424
0425     if (pipe == 0)
0426         dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
0427     else if (pipe == 1)
0428         dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
0429
0430     PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
0431     PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
0432     gma_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
0433
0434     spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
0435 }
0436
0437 /* Called from drm generic code, passed a 'crtc', which
0438  * we use as a pipe index
0439  */
0440 u32 gma_crtc_get_vblank_counter(struct drm_crtc *crtc)
0441 {
0442     struct drm_device *dev = crtc->dev;
0443     unsigned int pipe = crtc->index;
0444     uint32_t high_frame = PIPEAFRAMEHIGH;
0445     uint32_t low_frame = PIPEAFRAMEPIXEL;
0446     uint32_t pipeconf_reg = PIPEACONF;
0447     uint32_t reg_val = 0;
0448     uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
0449
0450     switch (pipe) {
0451     case 0:
0452         break;
0453     case 1:
0454         high_frame = PIPEBFRAMEHIGH;
0455         low_frame = PIPEBFRAMEPIXEL;
0456         pipeconf_reg = PIPEBCONF;
0457         break;
0458     case 2:
0459         high_frame = PIPECFRAMEHIGH;
0460         low_frame = PIPECFRAMEPIXEL;
0461         pipeconf_reg = PIPECCONF;
0462         break;
0463     default:
0464         dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
0465         return 0;
0466     }
0467
0468     if (!gma_power_begin(dev, false))
0469         return 0;
0470
0471     reg_val = REG_READ(pipeconf_reg);
0472
0473     if (!(reg_val & PIPEACONF_ENABLE)) {
0474         dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
0475             pipe);
0476         goto err_gma_power_end;
0477     }
0478
0479     /*
0480      * High & low register fields aren't synchronized, so make sure
0481      * we get a low value that's stable across two reads of the high
0482      * register.
0483      */
0484     do {
0485         high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
0486              PIPE_FRAME_HIGH_SHIFT);
0487         low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
0488             PIPE_FRAME_LOW_SHIFT);
0489         high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
0490              PIPE_FRAME_HIGH_SHIFT);
0491     } while (high1 != high2);
0492
0493     count = (high1 << 8) | low;
0494
0495 err_gma_power_end:
0496     gma_power_end(dev);
0497
0498     return count;
0499 }
0500