drm/gma500/psb_intel_sdvo_regs.h

0001 /*
0002  * Copyright ? 2006-2007 Intel Corporation
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0021  * DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors:
0024  *  Eric Anholt <eric@anholt.net>
0025  */
0026
0027 /**
0028  * @file SDVO command definitions and structures.
0029  */
0030
0031 #define SDVO_OUTPUT_FIRST   (0)
0032 #define SDVO_OUTPUT_TMDS0   (1 << 0)
0033 #define SDVO_OUTPUT_RGB0    (1 << 1)
0034 #define SDVO_OUTPUT_CVBS0   (1 << 2)
0035 #define SDVO_OUTPUT_SVID0   (1 << 3)
0036 #define SDVO_OUTPUT_YPRPB0  (1 << 4)
0037 #define SDVO_OUTPUT_SCART0  (1 << 5)
0038 #define SDVO_OUTPUT_LVDS0   (1 << 6)
0039 #define SDVO_OUTPUT_TMDS1   (1 << 8)
0040 #define SDVO_OUTPUT_RGB1    (1 << 9)
0041 #define SDVO_OUTPUT_CVBS1   (1 << 10)
0042 #define SDVO_OUTPUT_SVID1   (1 << 11)
0043 #define SDVO_OUTPUT_YPRPB1  (1 << 12)
0044 #define SDVO_OUTPUT_SCART1  (1 << 13)
0045 #define SDVO_OUTPUT_LVDS1   (1 << 14)
0046 #define SDVO_OUTPUT_LAST    (14)
0047
0048 struct psb_intel_sdvo_caps {
0049     u8 vendor_id;
0050     u8 device_id;
0051     u8 device_rev_id;
0052     u8 sdvo_version_major;
0053     u8 sdvo_version_minor;
0054     unsigned int sdvo_inputs_mask:2;
0055     unsigned int smooth_scaling:1;
0056     unsigned int sharp_scaling:1;
0057     unsigned int up_scaling:1;
0058     unsigned int down_scaling:1;
0059     unsigned int stall_support:1;
0060     unsigned int pad:1;
0061     u16 output_flags;
0062 } __attribute__((packed));
0063
0064 /** This matches the EDID DTD structure, more or less */
0065 struct psb_intel_sdvo_dtd {
0066     struct {
0067     u16 clock;      /**< pixel clock, in 10kHz units */
0068     u8 h_active;        /**< lower 8 bits (pixels) */
0069     u8 h_blank;     /**< lower 8 bits (pixels) */
0070     u8 h_high;      /**< upper 4 bits each h_active, h_blank */
0071     u8 v_active;        /**< lower 8 bits (lines) */
0072     u8 v_blank;     /**< lower 8 bits (lines) */
0073     u8 v_high;      /**< upper 4 bits each v_active, v_blank */
0074     } part1;
0075
0076     struct {
0077     u8 h_sync_off;  /**< lower 8 bits, from hblank start */
0078     u8 h_sync_width;    /**< lower 8 bits (pixels) */
0079     /** lower 4 bits each vsync offset, vsync width */
0080     u8 v_sync_off_width;
0081     /**
0082      * 2 high bits of hsync offset, 2 high bits of hsync width,
0083      * bits 4-5 of vsync offset, and 2 high bits of vsync width.
0084      */
0085     u8 sync_off_width_high;
0086     u8 dtd_flags;
0087     u8 sdvo_flags;
0088     /** bits 6-7 of vsync offset at bits 6-7 */
0089     u8 v_sync_off_high;
0090     u8 reserved;
0091     } part2;
0092 } __attribute__((packed));
0093
0094 struct psb_intel_sdvo_pixel_clock_range {
0095     u16 min;            /**< pixel clock, in 10kHz units */
0096     u16 max;            /**< pixel clock, in 10kHz units */
0097 } __attribute__((packed));
0098
0099 struct psb_intel_sdvo_preferred_input_timing_args {
0100     u16 clock;
0101     u16 width;
0102     u16 height;
0103     u8  interlace:1;
0104     u8  scaled:1;
0105     u8  pad:6;
0106 } __attribute__((packed));
0107
0108 /* I2C registers for SDVO */
0109 #define SDVO_I2C_ARG_0              0x07
0110 #define SDVO_I2C_ARG_1              0x06
0111 #define SDVO_I2C_ARG_2              0x05
0112 #define SDVO_I2C_ARG_3              0x04
0113 #define SDVO_I2C_ARG_4              0x03
0114 #define SDVO_I2C_ARG_5              0x02
0115 #define SDVO_I2C_ARG_6              0x01
0116 #define SDVO_I2C_ARG_7              0x00
0117 #define SDVO_I2C_OPCODE             0x08
0118 #define SDVO_I2C_CMD_STATUS         0x09
0119 #define SDVO_I2C_RETURN_0           0x0a
0120 #define SDVO_I2C_RETURN_1           0x0b
0121 #define SDVO_I2C_RETURN_2           0x0c
0122 #define SDVO_I2C_RETURN_3           0x0d
0123 #define SDVO_I2C_RETURN_4           0x0e
0124 #define SDVO_I2C_RETURN_5           0x0f
0125 #define SDVO_I2C_RETURN_6           0x10
0126 #define SDVO_I2C_RETURN_7           0x11
0127 #define SDVO_I2C_VENDOR_BEGIN           0x20
0128
0129 /* Status results */
0130 #define SDVO_CMD_STATUS_POWER_ON        0x0
0131 #define SDVO_CMD_STATUS_SUCCESS         0x1
0132 #define SDVO_CMD_STATUS_NOTSUPP         0x2
0133 #define SDVO_CMD_STATUS_INVALID_ARG     0x3
0134 #define SDVO_CMD_STATUS_PENDING         0x4
0135 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED    0x5
0136 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP    0x6
0137
0138 /* SDVO commands, argument/result registers */
0139
0140 #define SDVO_CMD_RESET                  0x01
0141
0142 /** Returns a struct intel_sdvo_caps */
0143 #define SDVO_CMD_GET_DEVICE_CAPS            0x02
0144
0145 #define SDVO_CMD_GET_FIRMWARE_REV           0x86
0146 # define SDVO_DEVICE_FIRMWARE_MINOR         SDVO_I2C_RETURN_0
0147 # define SDVO_DEVICE_FIRMWARE_MAJOR         SDVO_I2C_RETURN_1
0148 # define SDVO_DEVICE_FIRMWARE_PATCH         SDVO_I2C_RETURN_2
0149
0150 /**
0151  * Reports which inputs are trained (managed to sync).
0152  *
0153  * Devices must have trained within 2 vsyncs of a mode change.
0154  */
0155 #define SDVO_CMD_GET_TRAINED_INPUTS         0x03
0156 struct psb_intel_sdvo_get_trained_inputs_response {
0157     unsigned int input0_trained:1;
0158     unsigned int input1_trained:1;
0159     unsigned int pad:6;
0160 } __attribute__((packed));
0161
0162 /** Returns a struct intel_sdvo_output_flags of active outputs. */
0163 #define SDVO_CMD_GET_ACTIVE_OUTPUTS         0x04
0164
0165 /**
0166  * Sets the current set of active outputs.
0167  *
0168  * Takes a struct intel_sdvo_output_flags.  Must be preceded by a SET_IN_OUT_MAP
0169  * on multi-output devices.
0170  */
0171 #define SDVO_CMD_SET_ACTIVE_OUTPUTS         0x05
0172
0173 /**
0174  * Returns the current mapping of SDVO inputs to outputs on the device.
0175  *
0176  * Returns two struct intel_sdvo_output_flags structures.
0177  */
0178 #define SDVO_CMD_GET_IN_OUT_MAP             0x06
0179 struct psb_intel_sdvo_in_out_map {
0180     u16 in0, in1;
0181 };
0182
0183 /**
0184  * Sets the current mapping of SDVO inputs to outputs on the device.
0185  *
0186  * Takes two struct i380_sdvo_output_flags structures.
0187  */
0188 #define SDVO_CMD_SET_IN_OUT_MAP             0x07
0189
0190 /**
0191  * Returns a struct intel_sdvo_output_flags of attached displays.
0192  */
0193 #define SDVO_CMD_GET_ATTACHED_DISPLAYS          0x0b
0194
0195 /**
0196  * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
0197  */
0198 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT           0x0c
0199
0200 /**
0201  * Takes a struct intel_sdvo_output_flags.
0202  */
0203 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG            0x0d
0204
0205 /**
0206  * Returns a struct intel_sdvo_output_flags of displays with hot plug
0207  * interrupts enabled.
0208  */
0209 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG            0x0e
0210
0211 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE     0x0f
0212 struct intel_sdvo_get_interrupt_event_source_response {
0213     u16 interrupt_status;
0214     unsigned int ambient_light_interrupt:1;
0215     unsigned int hdmi_audio_encrypt_change:1;
0216     unsigned int pad:6;
0217 } __attribute__((packed));
0218
0219 /**
0220  * Selects which input is affected by future input commands.
0221  *
0222  * Commands affected include SET_INPUT_TIMINGS_PART[12],
0223  * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
0224  * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
0225  */
0226 #define SDVO_CMD_SET_TARGET_INPUT           0x10
0227 struct psb_intel_sdvo_set_target_input_args {
0228     unsigned int target_1:1;
0229     unsigned int pad:7;
0230 } __attribute__((packed));
0231
0232 /**
0233  * Takes a struct intel_sdvo_output_flags of which outputs are targeted by
0234  * future output commands.
0235  *
0236  * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
0237  * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
0238  */
0239 #define SDVO_CMD_SET_TARGET_OUTPUT          0x11
0240
0241 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1        0x12
0242 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2        0x13
0243 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1        0x14
0244 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2        0x15
0245 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1       0x16
0246 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2       0x17
0247 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1       0x18
0248 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2       0x19
0249 /* Part 1 */
0250 # define SDVO_DTD_CLOCK_LOW             SDVO_I2C_ARG_0
0251 # define SDVO_DTD_CLOCK_HIGH                SDVO_I2C_ARG_1
0252 # define SDVO_DTD_H_ACTIVE              SDVO_I2C_ARG_2
0253 # define SDVO_DTD_H_BLANK               SDVO_I2C_ARG_3
0254 # define SDVO_DTD_H_HIGH                SDVO_I2C_ARG_4
0255 # define SDVO_DTD_V_ACTIVE              SDVO_I2C_ARG_5
0256 # define SDVO_DTD_V_BLANK               SDVO_I2C_ARG_6
0257 # define SDVO_DTD_V_HIGH                SDVO_I2C_ARG_7
0258 /* Part 2 */
0259 # define SDVO_DTD_HSYNC_OFF             SDVO_I2C_ARG_0
0260 # define SDVO_DTD_HSYNC_WIDTH               SDVO_I2C_ARG_1
0261 # define SDVO_DTD_VSYNC_OFF_WIDTH           SDVO_I2C_ARG_2
0262 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH           SDVO_I2C_ARG_3
0263 # define SDVO_DTD_DTD_FLAGS             SDVO_I2C_ARG_4
0264 # define SDVO_DTD_DTD_FLAG_INTERLACED               (1 << 7)
0265 # define SDVO_DTD_DTD_FLAG_STEREO_MASK              (3 << 5)
0266 # define SDVO_DTD_DTD_FLAG_INPUT_MASK               (3 << 3)
0267 # define SDVO_DTD_DTD_FLAG_SYNC_MASK                (3 << 1)
0268 # define SDVO_DTD_SDVO_FLAS             SDVO_I2C_ARG_5
0269 # define SDVO_DTD_SDVO_FLAG_STALL               (1 << 7)
0270 # define SDVO_DTD_SDVO_FLAG_CENTERED                (0 << 6)
0271 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT              (1 << 6)
0272 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK            (3 << 4)
0273 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE            (0 << 4)
0274 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP           (1 << 4)
0275 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH          (2 << 4)
0276 # define SDVO_DTD_VSYNC_OFF_HIGH            SDVO_I2C_ARG_6
0277
0278 /**
0279  * Generates a DTD based on the given width, height, and flags.
0280  *
0281  * This will be supported by any device supporting scaling or interlaced
0282  * modes.
0283  */
0284 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING      0x1a
0285 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW      SDVO_I2C_ARG_0
0286 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH     SDVO_I2C_ARG_1
0287 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW      SDVO_I2C_ARG_2
0288 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH     SDVO_I2C_ARG_3
0289 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW     SDVO_I2C_ARG_4
0290 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH    SDVO_I2C_ARG_5
0291 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS      SDVO_I2C_ARG_6
0292 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED       (1 << 0)
0293 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED       (1 << 1)
0294
0295 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1   0x1b
0296 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2   0x1c
0297
0298 /** Returns a struct intel_sdvo_pixel_clock_range */
0299 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE        0x1d
0300 /** Returns a struct intel_sdvo_pixel_clock_range */
0301 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE       0x1e
0302
0303 /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
0304 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS     0x1f
0305
0306 /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
0307 #define SDVO_CMD_GET_CLOCK_RATE_MULT            0x20
0308 /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
0309 #define SDVO_CMD_SET_CLOCK_RATE_MULT            0x21
0310 # define SDVO_CLOCK_RATE_MULT_1X                (1 << 0)
0311 # define SDVO_CLOCK_RATE_MULT_2X                (1 << 1)
0312 # define SDVO_CLOCK_RATE_MULT_4X                (1 << 3)
0313
0314 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS       0x27
0315 /** 6 bytes of bit flags for TV formats shared by all TV format functions */
0316 struct psb_intel_sdvo_tv_format {
0317     unsigned int ntsc_m:1;
0318     unsigned int ntsc_j:1;
0319     unsigned int ntsc_443:1;
0320     unsigned int pal_b:1;
0321     unsigned int pal_d:1;
0322     unsigned int pal_g:1;
0323     unsigned int pal_h:1;
0324     unsigned int pal_i:1;
0325
0326     unsigned int pal_m:1;
0327     unsigned int pal_n:1;
0328     unsigned int pal_nc:1;
0329     unsigned int pal_60:1;
0330     unsigned int secam_b:1;
0331     unsigned int secam_d:1;
0332     unsigned int secam_g:1;
0333     unsigned int secam_k:1;
0334
0335     unsigned int secam_k1:1;
0336     unsigned int secam_l:1;
0337     unsigned int secam_60:1;
0338     unsigned int hdtv_std_smpte_240m_1080i_59:1;
0339     unsigned int hdtv_std_smpte_240m_1080i_60:1;
0340     unsigned int hdtv_std_smpte_260m_1080i_59:1;
0341     unsigned int hdtv_std_smpte_260m_1080i_60:1;
0342     unsigned int hdtv_std_smpte_274m_1080i_50:1;
0343
0344     unsigned int hdtv_std_smpte_274m_1080i_59:1;
0345     unsigned int hdtv_std_smpte_274m_1080i_60:1;
0346     unsigned int hdtv_std_smpte_274m_1080p_23:1;
0347     unsigned int hdtv_std_smpte_274m_1080p_24:1;
0348     unsigned int hdtv_std_smpte_274m_1080p_25:1;
0349     unsigned int hdtv_std_smpte_274m_1080p_29:1;
0350     unsigned int hdtv_std_smpte_274m_1080p_30:1;
0351     unsigned int hdtv_std_smpte_274m_1080p_50:1;
0352
0353     unsigned int hdtv_std_smpte_274m_1080p_59:1;
0354     unsigned int hdtv_std_smpte_274m_1080p_60:1;
0355     unsigned int hdtv_std_smpte_295m_1080i_50:1;
0356     unsigned int hdtv_std_smpte_295m_1080p_50:1;
0357     unsigned int hdtv_std_smpte_296m_720p_59:1;
0358     unsigned int hdtv_std_smpte_296m_720p_60:1;
0359     unsigned int hdtv_std_smpte_296m_720p_50:1;
0360     unsigned int hdtv_std_smpte_293m_480p_59:1;
0361
0362     unsigned int hdtv_std_smpte_170m_480i_59:1;
0363     unsigned int hdtv_std_iturbt601_576i_50:1;
0364     unsigned int hdtv_std_iturbt601_576p_50:1;
0365     unsigned int hdtv_std_eia_7702a_480i_60:1;
0366     unsigned int hdtv_std_eia_7702a_480p_60:1;
0367     unsigned int pad:3;
0368 } __attribute__((packed));
0369
0370 #define SDVO_CMD_GET_TV_FORMAT              0x28
0371
0372 #define SDVO_CMD_SET_TV_FORMAT              0x29
0373
0374 /** Returns the resolutiosn that can be used with the given TV format */
0375 #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT        0x83
0376 struct psb_intel_sdvo_sdtv_resolution_request {
0377     unsigned int ntsc_m:1;
0378     unsigned int ntsc_j:1;
0379     unsigned int ntsc_443:1;
0380     unsigned int pal_b:1;
0381     unsigned int pal_d:1;
0382     unsigned int pal_g:1;
0383     unsigned int pal_h:1;
0384     unsigned int pal_i:1;
0385
0386     unsigned int pal_m:1;
0387     unsigned int pal_n:1;
0388     unsigned int pal_nc:1;
0389     unsigned int pal_60:1;
0390     unsigned int secam_b:1;
0391     unsigned int secam_d:1;
0392     unsigned int secam_g:1;
0393     unsigned int secam_k:1;
0394
0395     unsigned int secam_k1:1;
0396     unsigned int secam_l:1;
0397     unsigned int secam_60:1;
0398     unsigned int pad:5;
0399 } __attribute__((packed));
0400
0401 struct psb_intel_sdvo_sdtv_resolution_reply {
0402     unsigned int res_320x200:1;
0403     unsigned int res_320x240:1;
0404     unsigned int res_400x300:1;
0405     unsigned int res_640x350:1;
0406     unsigned int res_640x400:1;
0407     unsigned int res_640x480:1;
0408     unsigned int res_704x480:1;
0409     unsigned int res_704x576:1;
0410
0411     unsigned int res_720x350:1;
0412     unsigned int res_720x400:1;
0413     unsigned int res_720x480:1;
0414     unsigned int res_720x540:1;
0415     unsigned int res_720x576:1;
0416     unsigned int res_768x576:1;
0417     unsigned int res_800x600:1;
0418     unsigned int res_832x624:1;
0419
0420     unsigned int res_920x766:1;
0421     unsigned int res_1024x768:1;
0422     unsigned int res_1280x1024:1;
0423     unsigned int pad:5;
0424 } __attribute__((packed));
0425
0426 /* Get supported resolution with squire pixel aspect ratio that can be
0427    scaled for the requested HDTV format */
0428 #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT     0x85
0429
0430 struct psb_intel_sdvo_hdtv_resolution_request {
0431     unsigned int hdtv_std_smpte_240m_1080i_59:1;
0432     unsigned int hdtv_std_smpte_240m_1080i_60:1;
0433     unsigned int hdtv_std_smpte_260m_1080i_59:1;
0434     unsigned int hdtv_std_smpte_260m_1080i_60:1;
0435     unsigned int hdtv_std_smpte_274m_1080i_50:1;
0436     unsigned int hdtv_std_smpte_274m_1080i_59:1;
0437     unsigned int hdtv_std_smpte_274m_1080i_60:1;
0438     unsigned int hdtv_std_smpte_274m_1080p_23:1;
0439
0440     unsigned int hdtv_std_smpte_274m_1080p_24:1;
0441     unsigned int hdtv_std_smpte_274m_1080p_25:1;
0442     unsigned int hdtv_std_smpte_274m_1080p_29:1;
0443     unsigned int hdtv_std_smpte_274m_1080p_30:1;
0444     unsigned int hdtv_std_smpte_274m_1080p_50:1;
0445     unsigned int hdtv_std_smpte_274m_1080p_59:1;
0446     unsigned int hdtv_std_smpte_274m_1080p_60:1;
0447     unsigned int hdtv_std_smpte_295m_1080i_50:1;
0448
0449     unsigned int hdtv_std_smpte_295m_1080p_50:1;
0450     unsigned int hdtv_std_smpte_296m_720p_59:1;
0451     unsigned int hdtv_std_smpte_296m_720p_60:1;
0452     unsigned int hdtv_std_smpte_296m_720p_50:1;
0453     unsigned int hdtv_std_smpte_293m_480p_59:1;
0454     unsigned int hdtv_std_smpte_170m_480i_59:1;
0455     unsigned int hdtv_std_iturbt601_576i_50:1;
0456     unsigned int hdtv_std_iturbt601_576p_50:1;
0457
0458     unsigned int hdtv_std_eia_7702a_480i_60:1;
0459     unsigned int hdtv_std_eia_7702a_480p_60:1;
0460     unsigned int pad:6;
0461 } __attribute__((packed));
0462
0463 struct psb_intel_sdvo_hdtv_resolution_reply {
0464     unsigned int res_640x480:1;
0465     unsigned int res_800x600:1;
0466     unsigned int res_1024x768:1;
0467     unsigned int res_1280x960:1;
0468     unsigned int res_1400x1050:1;
0469     unsigned int res_1600x1200:1;
0470     unsigned int res_1920x1440:1;
0471     unsigned int res_2048x1536:1;
0472
0473     unsigned int res_2560x1920:1;
0474     unsigned int res_3200x2400:1;
0475     unsigned int res_3840x2880:1;
0476     unsigned int pad1:5;
0477
0478     unsigned int res_848x480:1;
0479     unsigned int res_1064x600:1;
0480     unsigned int res_1280x720:1;
0481     unsigned int res_1360x768:1;
0482     unsigned int res_1704x960:1;
0483     unsigned int res_1864x1050:1;
0484     unsigned int res_1920x1080:1;
0485     unsigned int res_2128x1200:1;
0486
0487     unsigned int res_2560x1400:1;
0488     unsigned int res_2728x1536:1;
0489     unsigned int res_3408x1920:1;
0490     unsigned int res_4264x2400:1;
0491     unsigned int res_5120x2880:1;
0492     unsigned int pad2:3;
0493
0494     unsigned int res_768x480:1;
0495     unsigned int res_960x600:1;
0496     unsigned int res_1152x720:1;
0497     unsigned int res_1124x768:1;
0498     unsigned int res_1536x960:1;
0499     unsigned int res_1680x1050:1;
0500     unsigned int res_1728x1080:1;
0501     unsigned int res_1920x1200:1;
0502
0503     unsigned int res_2304x1440:1;
0504     unsigned int res_2456x1536:1;
0505     unsigned int res_3072x1920:1;
0506     unsigned int res_3840x2400:1;
0507     unsigned int res_4608x2880:1;
0508     unsigned int pad3:3;
0509
0510     unsigned int res_1280x1024:1;
0511     unsigned int pad4:7;
0512
0513     unsigned int res_1280x768:1;
0514     unsigned int pad5:7;
0515 } __attribute__((packed));
0516
0517 /* Get supported power state returns info for encoder and monitor, rely on
0518    last SetTargetInput and SetTargetOutput calls */
0519 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES     0x2a
0520 /* Get power state returns info for encoder and monitor, rely on last
0521    SetTargetInput and SetTargetOutput calls */
0522 #define SDVO_CMD_GET_POWER_STATE            0x2b
0523 #define SDVO_CMD_GET_ENCODER_POWER_STATE        0x2b
0524 #define SDVO_CMD_SET_ENCODER_POWER_STATE        0x2c
0525 # define SDVO_ENCODER_STATE_ON                  (1 << 0)
0526 # define SDVO_ENCODER_STATE_STANDBY             (1 << 1)
0527 # define SDVO_ENCODER_STATE_SUSPEND             (1 << 2)
0528 # define SDVO_ENCODER_STATE_OFF                 (1 << 3)
0529 # define SDVO_MONITOR_STATE_ON                  (1 << 4)
0530 # define SDVO_MONITOR_STATE_STANDBY             (1 << 5)
0531 # define SDVO_MONITOR_STATE_SUSPEND             (1 << 6)
0532 # define SDVO_MONITOR_STATE_OFF                 (1 << 7)
0533
0534 #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING     0x2d
0535 #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING     0x2e
0536 #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING     0x2f
0537 /**
0538  * The panel power sequencing parameters are in units of milliseconds.
0539  * The high fields are bits 8:9 of the 10-bit values.
0540  */
0541 struct psb_sdvo_panel_power_sequencing {
0542     u8 t0;
0543     u8 t1;
0544     u8 t2;
0545     u8 t3;
0546     u8 t4;
0547
0548     unsigned int t0_high:2;
0549     unsigned int t1_high:2;
0550     unsigned int t2_high:2;
0551     unsigned int t3_high:2;
0552
0553     unsigned int t4_high:2;
0554     unsigned int pad:6;
0555 } __attribute__((packed));
0556
0557 #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL        0x30
0558 struct sdvo_max_backlight_reply {
0559     u8 max_value;
0560     u8 default_value;
0561 } __attribute__((packed));
0562
0563 #define SDVO_CMD_GET_BACKLIGHT_LEVEL            0x31
0564 #define SDVO_CMD_SET_BACKLIGHT_LEVEL            0x32
0565
0566 #define SDVO_CMD_GET_AMBIENT_LIGHT          0x33
0567 struct sdvo_get_ambient_light_reply {
0568     u16 trip_low;
0569     u16 trip_high;
0570     u16 value;
0571 } __attribute__((packed));
0572 #define SDVO_CMD_SET_AMBIENT_LIGHT          0x34
0573 struct sdvo_set_ambient_light_reply {
0574     u16 trip_low;
0575     u16 trip_high;
0576     unsigned int enable:1;
0577     unsigned int pad:7;
0578 } __attribute__((packed));
0579
0580 /* Set display power state */
0581 #define SDVO_CMD_SET_DISPLAY_POWER_STATE        0x7d
0582 # define SDVO_DISPLAY_STATE_ON              (1 << 0)
0583 # define SDVO_DISPLAY_STATE_STANDBY         (1 << 1)
0584 # define SDVO_DISPLAY_STATE_SUSPEND         (1 << 2)
0585 # define SDVO_DISPLAY_STATE_OFF             (1 << 3)
0586
0587 #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS     0x84
0588 struct psb_intel_sdvo_enhancements_reply {
0589     unsigned int flicker_filter:1;
0590     unsigned int flicker_filter_adaptive:1;
0591     unsigned int flicker_filter_2d:1;
0592     unsigned int saturation:1;
0593     unsigned int hue:1;
0594     unsigned int brightness:1;
0595     unsigned int contrast:1;
0596     unsigned int overscan_h:1;
0597
0598     unsigned int overscan_v:1;
0599     unsigned int hpos:1;
0600     unsigned int vpos:1;
0601     unsigned int sharpness:1;
0602     unsigned int dot_crawl:1;
0603     unsigned int dither:1;
0604     unsigned int tv_chroma_filter:1;
0605     unsigned int tv_luma_filter:1;
0606 } __attribute__((packed));
0607
0608 /* Picture enhancement limits below are dependent on the current TV format,
0609  * and thus need to be queried and set after it.
0610  */
0611 #define SDVO_CMD_GET_MAX_FLICKER_FILTER         0x4d
0612 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE    0x7b
0613 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D      0x52
0614 #define SDVO_CMD_GET_MAX_SATURATION         0x55
0615 #define SDVO_CMD_GET_MAX_HUE                0x58
0616 #define SDVO_CMD_GET_MAX_BRIGHTNESS         0x5b
0617 #define SDVO_CMD_GET_MAX_CONTRAST           0x5e
0618 #define SDVO_CMD_GET_MAX_OVERSCAN_H         0x61
0619 #define SDVO_CMD_GET_MAX_OVERSCAN_V         0x64
0620 #define SDVO_CMD_GET_MAX_HPOS               0x67
0621 #define SDVO_CMD_GET_MAX_VPOS               0x6a
0622 #define SDVO_CMD_GET_MAX_SHARPNESS          0x6d
0623 #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER       0x74
0624 #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER         0x77
0625 struct psb_intel_sdvo_enhancement_limits_reply {
0626     u16 max_value;
0627     u16 default_value;
0628 } __attribute__((packed));
0629
0630 #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION     0x7f
0631 #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION     0x80
0632 # define SDVO_LVDS_COLOR_DEPTH_18           (0 << 0)
0633 # define SDVO_LVDS_COLOR_DEPTH_24           (1 << 0)
0634 # define SDVO_LVDS_CONNECTOR_SPWG           (0 << 2)
0635 # define SDVO_LVDS_CONNECTOR_OPENLDI            (1 << 2)
0636 # define SDVO_LVDS_SINGLE_CHANNEL           (0 << 4)
0637 # define SDVO_LVDS_DUAL_CHANNEL             (1 << 4)
0638
0639 #define SDVO_CMD_GET_FLICKER_FILTER         0x4e
0640 #define SDVO_CMD_SET_FLICKER_FILTER         0x4f
0641 #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE        0x50
0642 #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE        0x51
0643 #define SDVO_CMD_GET_FLICKER_FILTER_2D          0x53
0644 #define SDVO_CMD_SET_FLICKER_FILTER_2D          0x54
0645 #define SDVO_CMD_GET_SATURATION             0x56
0646 #define SDVO_CMD_SET_SATURATION             0x57
0647 #define SDVO_CMD_GET_HUE                0x59
0648 #define SDVO_CMD_SET_HUE                0x5a
0649 #define SDVO_CMD_GET_BRIGHTNESS             0x5c
0650 #define SDVO_CMD_SET_BRIGHTNESS             0x5d
0651 #define SDVO_CMD_GET_CONTRAST               0x5f
0652 #define SDVO_CMD_SET_CONTRAST               0x60
0653 #define SDVO_CMD_GET_OVERSCAN_H             0x62
0654 #define SDVO_CMD_SET_OVERSCAN_H             0x63
0655 #define SDVO_CMD_GET_OVERSCAN_V             0x65
0656 #define SDVO_CMD_SET_OVERSCAN_V             0x66
0657 #define SDVO_CMD_GET_HPOS               0x68
0658 #define SDVO_CMD_SET_HPOS               0x69
0659 #define SDVO_CMD_GET_VPOS               0x6b
0660 #define SDVO_CMD_SET_VPOS               0x6c
0661 #define SDVO_CMD_GET_SHARPNESS              0x6e
0662 #define SDVO_CMD_SET_SHARPNESS              0x6f
0663 #define SDVO_CMD_GET_TV_CHROMA_FILTER           0x75
0664 #define SDVO_CMD_SET_TV_CHROMA_FILTER           0x76
0665 #define SDVO_CMD_GET_TV_LUMA_FILTER         0x78
0666 #define SDVO_CMD_SET_TV_LUMA_FILTER         0x79
0667 struct psb_intel_sdvo_enhancements_arg {
0668     u16 value;
0669 }__attribute__((packed));
0670
0671 #define SDVO_CMD_GET_DOT_CRAWL              0x70
0672 #define SDVO_CMD_SET_DOT_CRAWL              0x71
0673 # define SDVO_DOT_CRAWL_ON                  (1 << 0)
0674 # define SDVO_DOT_CRAWL_DEFAULT_ON              (1 << 1)
0675
0676 #define SDVO_CMD_GET_DITHER             0x72
0677 #define SDVO_CMD_SET_DITHER             0x73
0678 # define SDVO_DITHER_ON                     (1 << 0)
0679 # define SDVO_DITHER_DEFAULT_ON                 (1 << 1)
0680
0681 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH         0x7a
0682 # define SDVO_CONTROL_BUS_PROM              (1 << 0)
0683 # define SDVO_CONTROL_BUS_DDC1              (1 << 1)
0684 # define SDVO_CONTROL_BUS_DDC2              (1 << 2)
0685 # define SDVO_CONTROL_BUS_DDC3              (1 << 3)
0686
0687 /* HDMI op codes */
0688 #define SDVO_CMD_GET_SUPP_ENCODE    0x9d
0689 #define SDVO_CMD_GET_ENCODE     0x9e
0690 #define SDVO_CMD_SET_ENCODE     0x9f
0691   #define SDVO_ENCODE_DVI   0x0
0692   #define SDVO_ENCODE_HDMI  0x1
0693 #define SDVO_CMD_SET_PIXEL_REPLI    0x8b
0694 #define SDVO_CMD_GET_PIXEL_REPLI    0x8c
0695 #define SDVO_CMD_GET_COLORIMETRY_CAP    0x8d
0696 #define SDVO_CMD_SET_COLORIMETRY    0x8e
0697   #define SDVO_COLORIMETRY_RGB256   0x0
0698   #define SDVO_COLORIMETRY_RGB220   0x1
0699   #define SDVO_COLORIMETRY_YCrCb422 0x3
0700   #define SDVO_COLORIMETRY_YCrCb444 0x4
0701 #define SDVO_CMD_GET_COLORIMETRY    0x8f
0702 #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
0703 #define SDVO_CMD_SET_AUDIO_STAT     0x91
0704 #define SDVO_CMD_GET_AUDIO_STAT     0x92
0705 #define SDVO_CMD_SET_HBUF_INDEX     0x93
0706 #define SDVO_CMD_GET_HBUF_INDEX     0x94
0707 #define SDVO_CMD_GET_HBUF_INFO      0x95
0708 #define SDVO_CMD_SET_HBUF_AV_SPLIT  0x96
0709 #define SDVO_CMD_GET_HBUF_AV_SPLIT  0x97
0710 #define SDVO_CMD_SET_HBUF_DATA      0x98
0711 #define SDVO_CMD_GET_HBUF_DATA      0x99
0712 #define SDVO_CMD_SET_HBUF_TXRATE    0x9a
0713 #define SDVO_CMD_GET_HBUF_TXRATE    0x9b
0714   #define SDVO_HBUF_TX_DISABLED (0 << 6)
0715   #define SDVO_HBUF_TX_ONCE (2 << 6)
0716   #define SDVO_HBUF_TX_VSYNC    (3 << 6)
0717 #define SDVO_CMD_GET_AUDIO_TX_INFO  0x9c
0718 #define SDVO_NEED_TO_STALL  (1 << 7)
0719
0720 struct psb_intel_sdvo_encode {
0721     u8 dvi_rev;
0722     u8 hdmi_rev;
0723 } __attribute__ ((packed));