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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright © 2006-2011 Intel Corporation
0004  *
0005  * Authors:
0006  *  Eric Anholt <eric@anholt.net>
0007  */
0008 
0009 #include <linux/delay.h>
0010 #include <linux/i2c.h>
0011 
0012 #include <drm/drm_plane_helper.h>
0013 
0014 #include "framebuffer.h"
0015 #include "gem.h"
0016 #include "gma_display.h"
0017 #include "power.h"
0018 #include "psb_drv.h"
0019 #include "psb_intel_drv.h"
0020 #include "psb_intel_reg.h"
0021 
0022 #define INTEL_LIMIT_I9XX_SDVO_DAC   0
0023 #define INTEL_LIMIT_I9XX_LVDS       1
0024 
0025 static const struct gma_limit_t psb_intel_limits[] = {
0026     {           /* INTEL_LIMIT_I9XX_SDVO_DAC */
0027      .dot = {.min = 20000, .max = 400000},
0028      .vco = {.min = 1400000, .max = 2800000},
0029      .n = {.min = 1, .max = 6},
0030      .m = {.min = 70, .max = 120},
0031      .m1 = {.min = 8, .max = 18},
0032      .m2 = {.min = 3, .max = 7},
0033      .p = {.min = 5, .max = 80},
0034      .p1 = {.min = 1, .max = 8},
0035      .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
0036      .find_pll = gma_find_best_pll,
0037      },
0038     {           /* INTEL_LIMIT_I9XX_LVDS */
0039      .dot = {.min = 20000, .max = 400000},
0040      .vco = {.min = 1400000, .max = 2800000},
0041      .n = {.min = 1, .max = 6},
0042      .m = {.min = 70, .max = 120},
0043      .m1 = {.min = 8, .max = 18},
0044      .m2 = {.min = 3, .max = 7},
0045      .p = {.min = 7, .max = 98},
0046      .p1 = {.min = 1, .max = 8},
0047      /* The single-channel range is 25-112Mhz, and dual-channel
0048       * is 80-224Mhz.  Prefer single channel as much as possible.
0049       */
0050      .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
0051      .find_pll = gma_find_best_pll,
0052      },
0053 };
0054 
0055 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
0056                          int refclk)
0057 {
0058     const struct gma_limit_t *limit;
0059 
0060     if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
0061         limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
0062     else
0063         limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
0064     return limit;
0065 }
0066 
0067 static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
0068 {
0069     clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
0070     clock->p = clock->p1 * clock->p2;
0071     clock->vco = refclk * clock->m / (clock->n + 2);
0072     clock->dot = clock->vco / clock->p;
0073 }
0074 
0075 /*
0076  * Return the pipe currently connected to the panel fitter,
0077  * or -1 if the panel fitter is not present or not in use
0078  */
0079 static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
0080 {
0081     u32 pfit_control;
0082 
0083     pfit_control = REG_READ(PFIT_CONTROL);
0084 
0085     /* See if the panel fitter is in use */
0086     if ((pfit_control & PFIT_ENABLE) == 0)
0087         return -1;
0088     /* Must be on PIPE 1 for PSB */
0089     return 1;
0090 }
0091 
0092 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
0093                    struct drm_display_mode *mode,
0094                    struct drm_display_mode *adjusted_mode,
0095                    int x, int y,
0096                    struct drm_framebuffer *old_fb)
0097 {
0098     struct drm_device *dev = crtc->dev;
0099     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0100     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0101     const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
0102     int pipe = gma_crtc->pipe;
0103     const struct psb_offset *map = &dev_priv->regmap[pipe];
0104     int refclk;
0105     struct gma_clock_t clock;
0106     u32 dpll = 0, fp = 0, dspcntr, pipeconf;
0107     bool ok, is_sdvo = false;
0108     bool is_lvds = false, is_tv = false;
0109     struct drm_connector_list_iter conn_iter;
0110     struct drm_connector *connector;
0111     const struct gma_limit_t *limit;
0112 
0113     /* No scan out no play */
0114     if (crtc->primary->fb == NULL) {
0115         crtc_funcs->mode_set_base(crtc, x, y, old_fb);
0116         return 0;
0117     }
0118 
0119     drm_connector_list_iter_begin(dev, &conn_iter);
0120     drm_for_each_connector_iter(connector, &conn_iter) {
0121         struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
0122 
0123         if (!connector->encoder
0124             || connector->encoder->crtc != crtc)
0125             continue;
0126 
0127         switch (gma_encoder->type) {
0128         case INTEL_OUTPUT_LVDS:
0129             is_lvds = true;
0130             break;
0131         case INTEL_OUTPUT_SDVO:
0132             is_sdvo = true;
0133             break;
0134         case INTEL_OUTPUT_TVOUT:
0135             is_tv = true;
0136             break;
0137         }
0138 
0139         break;
0140     }
0141     drm_connector_list_iter_end(&conn_iter);
0142 
0143     refclk = 96000;
0144 
0145     limit = gma_crtc->clock_funcs->limit(crtc, refclk);
0146 
0147     ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
0148                  &clock);
0149     if (!ok) {
0150         DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
0151               adjusted_mode->clock, clock.dot);
0152         return 0;
0153     }
0154 
0155     fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
0156 
0157     dpll = DPLL_VGA_MODE_DIS;
0158     if (is_lvds) {
0159         dpll |= DPLLB_MODE_LVDS;
0160         dpll |= DPLL_DVO_HIGH_SPEED;
0161     } else
0162         dpll |= DPLLB_MODE_DAC_SERIAL;
0163     if (is_sdvo) {
0164         int sdvo_pixel_multiply =
0165                 adjusted_mode->clock / mode->clock;
0166         dpll |= DPLL_DVO_HIGH_SPEED;
0167         dpll |=
0168             (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
0169     }
0170 
0171     /* compute bitmask from p1 value */
0172     dpll |= (1 << (clock.p1 - 1)) << 16;
0173     switch (clock.p2) {
0174     case 5:
0175         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
0176         break;
0177     case 7:
0178         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
0179         break;
0180     case 10:
0181         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
0182         break;
0183     case 14:
0184         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
0185         break;
0186     }
0187 
0188     if (is_tv) {
0189         /* XXX: just matching BIOS for now */
0190 /*  dpll |= PLL_REF_INPUT_TVCLKINBC; */
0191         dpll |= 3;
0192     }
0193     dpll |= PLL_REF_INPUT_DREFCLK;
0194 
0195     /* setup pipeconf */
0196     pipeconf = REG_READ(map->conf);
0197 
0198     /* Set up the display plane register */
0199     dspcntr = DISPPLANE_GAMMA_ENABLE;
0200 
0201     if (pipe == 0)
0202         dspcntr |= DISPPLANE_SEL_PIPE_A;
0203     else
0204         dspcntr |= DISPPLANE_SEL_PIPE_B;
0205 
0206     dspcntr |= DISPLAY_PLANE_ENABLE;
0207     pipeconf |= PIPEACONF_ENABLE;
0208     dpll |= DPLL_VCO_ENABLE;
0209 
0210 
0211     /* Disable the panel fitter if it was on our pipe */
0212     if (psb_intel_panel_fitter_pipe(dev) == pipe)
0213         REG_WRITE(PFIT_CONTROL, 0);
0214 
0215     drm_mode_debug_printmodeline(mode);
0216 
0217     if (dpll & DPLL_VCO_ENABLE) {
0218         REG_WRITE(map->fp0, fp);
0219         REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
0220         REG_READ(map->dpll);
0221         udelay(150);
0222     }
0223 
0224     /* The LVDS pin pair needs to be on before the DPLLs are enabled.
0225      * This is an exception to the general rule that mode_set doesn't turn
0226      * things on.
0227      */
0228     if (is_lvds) {
0229         u32 lvds = REG_READ(LVDS);
0230 
0231         lvds &= ~LVDS_PIPEB_SELECT;
0232         if (pipe == 1)
0233             lvds |= LVDS_PIPEB_SELECT;
0234 
0235         lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
0236         /* Set the B0-B3 data pairs corresponding to
0237          * whether we're going to
0238          * set the DPLLs for dual-channel mode or not.
0239          */
0240         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
0241         if (clock.p2 == 7)
0242             lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
0243 
0244         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
0245          * appropriately here, but we need to look more
0246          * thoroughly into how panels behave in the two modes.
0247          */
0248 
0249         REG_WRITE(LVDS, lvds);
0250         REG_READ(LVDS);
0251     }
0252 
0253     REG_WRITE(map->fp0, fp);
0254     REG_WRITE(map->dpll, dpll);
0255     REG_READ(map->dpll);
0256     /* Wait for the clocks to stabilize. */
0257     udelay(150);
0258 
0259     /* write it again -- the BIOS does, after all */
0260     REG_WRITE(map->dpll, dpll);
0261 
0262     REG_READ(map->dpll);
0263     /* Wait for the clocks to stabilize. */
0264     udelay(150);
0265 
0266     REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
0267           ((adjusted_mode->crtc_htotal - 1) << 16));
0268     REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
0269           ((adjusted_mode->crtc_hblank_end - 1) << 16));
0270     REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
0271           ((adjusted_mode->crtc_hsync_end - 1) << 16));
0272     REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
0273           ((adjusted_mode->crtc_vtotal - 1) << 16));
0274     REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
0275           ((adjusted_mode->crtc_vblank_end - 1) << 16));
0276     REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
0277           ((adjusted_mode->crtc_vsync_end - 1) << 16));
0278     /* pipesrc and dspsize control the size that is scaled from,
0279      * which should always be the user's requested size.
0280      */
0281     REG_WRITE(map->size,
0282           ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
0283     REG_WRITE(map->pos, 0);
0284     REG_WRITE(map->src,
0285           ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
0286     REG_WRITE(map->conf, pipeconf);
0287     REG_READ(map->conf);
0288 
0289     gma_wait_for_vblank(dev);
0290 
0291     REG_WRITE(map->cntr, dspcntr);
0292 
0293     /* Flush the plane changes */
0294     crtc_funcs->mode_set_base(crtc, x, y, old_fb);
0295 
0296     gma_wait_for_vblank(dev);
0297 
0298     return 0;
0299 }
0300 
0301 /* Returns the clock of the currently programmed mode of the given pipe. */
0302 static int psb_intel_crtc_clock_get(struct drm_device *dev,
0303                 struct drm_crtc *crtc)
0304 {
0305     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0306     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0307     int pipe = gma_crtc->pipe;
0308     const struct psb_offset *map = &dev_priv->regmap[pipe];
0309     u32 dpll;
0310     u32 fp;
0311     struct gma_clock_t clock;
0312     bool is_lvds;
0313     struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
0314 
0315     if (gma_power_begin(dev, false)) {
0316         dpll = REG_READ(map->dpll);
0317         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
0318             fp = REG_READ(map->fp0);
0319         else
0320             fp = REG_READ(map->fp1);
0321         is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
0322         gma_power_end(dev);
0323     } else {
0324         dpll = p->dpll;
0325 
0326         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
0327             fp = p->fp0;
0328         else
0329                 fp = p->fp1;
0330 
0331         is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
0332                                 LVDS_PORT_EN);
0333     }
0334 
0335     clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
0336     clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
0337     clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
0338 
0339     if (is_lvds) {
0340         clock.p1 =
0341             ffs((dpll &
0342              DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
0343             DPLL_FPA01_P1_POST_DIV_SHIFT);
0344         clock.p2 = 14;
0345 
0346         if ((dpll & PLL_REF_INPUT_MASK) ==
0347             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
0348             /* XXX: might not be 66MHz */
0349             psb_intel_clock(66000, &clock);
0350         } else
0351             psb_intel_clock(48000, &clock);
0352     } else {
0353         if (dpll & PLL_P1_DIVIDE_BY_TWO)
0354             clock.p1 = 2;
0355         else {
0356             clock.p1 =
0357                 ((dpll &
0358                   DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
0359                  DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
0360         }
0361         if (dpll & PLL_P2_DIVIDE_BY_4)
0362             clock.p2 = 4;
0363         else
0364             clock.p2 = 2;
0365 
0366         psb_intel_clock(48000, &clock);
0367     }
0368 
0369     /* XXX: It would be nice to validate the clocks, but we can't reuse
0370      * i830PllIsValid() because it relies on the xf86_config connector
0371      * configuration being accurate, which it isn't necessarily.
0372      */
0373 
0374     return clock.dot;
0375 }
0376 
0377 /** Returns the currently programmed mode of the given pipe. */
0378 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
0379                          struct drm_crtc *crtc)
0380 {
0381     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0382     int pipe = gma_crtc->pipe;
0383     struct drm_display_mode *mode;
0384     int htot;
0385     int hsync;
0386     int vtot;
0387     int vsync;
0388     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0389     struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
0390     const struct psb_offset *map = &dev_priv->regmap[pipe];
0391 
0392     if (gma_power_begin(dev, false)) {
0393         htot = REG_READ(map->htotal);
0394         hsync = REG_READ(map->hsync);
0395         vtot = REG_READ(map->vtotal);
0396         vsync = REG_READ(map->vsync);
0397         gma_power_end(dev);
0398     } else {
0399         htot = p->htotal;
0400         hsync = p->hsync;
0401         vtot = p->vtotal;
0402         vsync = p->vsync;
0403     }
0404 
0405     mode = kzalloc(sizeof(*mode), GFP_KERNEL);
0406     if (!mode)
0407         return NULL;
0408 
0409     mode->clock = psb_intel_crtc_clock_get(dev, crtc);
0410     mode->hdisplay = (htot & 0xffff) + 1;
0411     mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
0412     mode->hsync_start = (hsync & 0xffff) + 1;
0413     mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
0414     mode->vdisplay = (vtot & 0xffff) + 1;
0415     mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
0416     mode->vsync_start = (vsync & 0xffff) + 1;
0417     mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
0418 
0419     drm_mode_set_name(mode);
0420     drm_mode_set_crtcinfo(mode, 0);
0421 
0422     return mode;
0423 }
0424 
0425 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
0426     .dpms = gma_crtc_dpms,
0427     .mode_set = psb_intel_crtc_mode_set,
0428     .mode_set_base = gma_pipe_set_base,
0429     .prepare = gma_crtc_prepare,
0430     .commit = gma_crtc_commit,
0431     .disable = gma_crtc_disable,
0432 };
0433 
0434 const struct gma_clock_funcs psb_clock_funcs = {
0435     .clock = psb_intel_clock,
0436     .limit = psb_intel_limit,
0437     .pll_is_valid = gma_pll_is_valid,
0438 };
0439 
0440 /*
0441  * Set the default value of cursor control and base register
0442  * to zero. This is a workaround for h/w defect on Oaktrail
0443  */
0444 static void psb_intel_cursor_init(struct drm_device *dev,
0445                   struct gma_crtc *gma_crtc)
0446 {
0447     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0448     u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
0449     u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
0450     struct psb_gem_object *cursor_pobj;
0451 
0452     if (dev_priv->ops->cursor_needs_phys) {
0453         /* Allocate 4 pages of stolen mem for a hardware cursor. That
0454          * is enough for the 64 x 64 ARGB cursors we support.
0455          */
0456         cursor_pobj = psb_gem_create(dev, 4 * PAGE_SIZE, "cursor", true, PAGE_SIZE);
0457         if (IS_ERR(cursor_pobj)) {
0458             gma_crtc->cursor_pobj = NULL;
0459             goto out;
0460         }
0461         gma_crtc->cursor_pobj = cursor_pobj;
0462         gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_pobj->offset;
0463     } else {
0464         gma_crtc->cursor_pobj = NULL;
0465     }
0466 
0467 out:
0468     REG_WRITE(control[gma_crtc->pipe], 0);
0469     REG_WRITE(base[gma_crtc->pipe], 0);
0470 }
0471 
0472 void psb_intel_crtc_init(struct drm_device *dev, int pipe,
0473              struct psb_intel_mode_device *mode_dev)
0474 {
0475     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0476     struct gma_crtc *gma_crtc;
0477     int i;
0478 
0479     /* We allocate a extra array of drm_connector pointers
0480      * for fbdev after the crtc */
0481     gma_crtc = kzalloc(sizeof(struct gma_crtc) +
0482             (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
0483             GFP_KERNEL);
0484     if (gma_crtc == NULL)
0485         return;
0486 
0487     gma_crtc->crtc_state =
0488         kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
0489     if (!gma_crtc->crtc_state) {
0490         dev_err(dev->dev, "Crtc state error: No memory\n");
0491         kfree(gma_crtc);
0492         return;
0493     }
0494 
0495     drm_crtc_init(dev, &gma_crtc->base, &gma_crtc_funcs);
0496 
0497     /* Set the CRTC clock functions from chip specific data */
0498     gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
0499 
0500     drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
0501     gma_crtc->pipe = pipe;
0502     gma_crtc->plane = pipe;
0503 
0504     for (i = 0; i < 256; i++)
0505         gma_crtc->lut_adj[i] = 0;
0506 
0507     gma_crtc->mode_dev = mode_dev;
0508     gma_crtc->cursor_addr = 0;
0509 
0510     drm_crtc_helper_add(&gma_crtc->base,
0511                         dev_priv->ops->crtc_helper);
0512 
0513     /* Setup the array of drm_connector pointer array */
0514     gma_crtc->mode_set.crtc = &gma_crtc->base;
0515     BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
0516            dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
0517     dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
0518     dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
0519     gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
0520     gma_crtc->mode_set.num_connectors = 0;
0521     psb_intel_cursor_init(dev, gma_crtc);
0522 
0523     /* Set to true so that the pipe is forced off on initial config. */
0524     gma_crtc->active = true;
0525 }
0526 
0527 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
0528 {
0529     struct drm_crtc *crtc;
0530 
0531     list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
0532         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0533 
0534         if (gma_crtc->pipe == pipe)
0535             return crtc;
0536     }
0537     return NULL;
0538 }
0539 
0540 int gma_connector_clones(struct drm_device *dev, int type_mask)
0541 {
0542     struct drm_connector_list_iter conn_iter;
0543     struct drm_connector *connector;
0544     int index_mask = 0;
0545     int entry = 0;
0546 
0547     drm_connector_list_iter_begin(dev, &conn_iter);
0548     drm_for_each_connector_iter(connector, &conn_iter) {
0549         struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
0550         if (type_mask & (1 << gma_encoder->type))
0551             index_mask |= (1 << entry);
0552         entry++;
0553     }
0554     drm_connector_list_iter_end(&conn_iter);
0555 
0556     return index_mask;
0557 }
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